CN105958953A - Data receiver - Google Patents
Data receiver Download PDFInfo
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- CN105958953A CN105958953A CN201610237069.5A CN201610237069A CN105958953A CN 105958953 A CN105958953 A CN 105958953A CN 201610237069 A CN201610237069 A CN 201610237069A CN 105958953 A CN105958953 A CN 105958953A
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- pole
- switching tube
- amplifier
- current source
- data sink
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
- H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
- H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
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Abstract
The invention discloses a data receiver, and the data receiver comprises a first stage amplifier; a second stage amplifier; a first load circuit which is connected with a negative phase output end of the first stage amplifier and the positive phase input end of the second stage amplifier; and a second load circuit which is connected with the positive phase output end of the first stage amplifier and the negative input end of the second stage amplifier. The first and second load circuits are equal in equivalent resistance. The first and second load circuits are used for increasing communication zero points of the first stage amplifier. According to the invention, the first and second load circuits are used for increasing communication zero points, thereby increasing the bandwidth of a pre-amplifier of a data amplifier.
Description
Technical field
The present invention relates to communication device technology field, in particular, relate to a kind of data sink.
Background technology
Current mobile device is to develop towards the longer direction using the time, i.e. under identical electricity,
Needing mobile device work the longest, this is in addition to requiring battery technology, the power consumption to each functional module
It is also proposed challenge.Faster data transmission bauds, lower power consumption, the cost more saved are as newly grinding
The requirement sent out.
As the nucleus module of D-PHY artificial circuit part, the speed of data sink is to determine D-PHY
The leading indicator of performance.Data sink is made up of multistage amplifier, and the bandwidth of amplifier directly determines
The speed of data transmission.The Main Function of data sink is accurately to be received by serial differential small-signal and put
Greatly to the digital signal of CMOS level, it is resent to module below and carries out process such as unstringing.Wherein, D-PHY
It is to be formulated by MIPI alliance, and the communication specification being designed by mobile device manufacturer and using.Letter " D " is taken from
" 500 " in Roman number, are owing to this specification is based on single channel 500Mbps at the beginning of formulating
The typical rate of (Million bits per second) is formulated, and along with progress and the technology of technique develop,
Single channel rate is improving constantly.
Data sink problem encountered is the compromise of gain and bandwidth, and the amplifier of one-level is difficulty with,
So typically using the structure of multistage amplifier cascade, lifting step by step gain on the premise of ensureing bandwidth.
Along with gradually rising of gain, signal swing constantly increases, and the emphasis of design is not quite similar.Input letter
Number amplitude of oscillation is the least the highest to bandwidth requirement, so in data sink, the structure of pre-amplifier is more focused on
Bandwidth.Therefore, how to improve the bandwidth of data amplifier pre-amplifier, be communication device technology field
A problem urgently to be resolved hurrily.
Summary of the invention
For solving the problems referred to above, the invention provides a kind of data sink, described data sink passes through
First load circuit and the second load circuit are used for increasing communication zero point, and then can increase bandwidth.
To achieve these goals, the present invention provides following technical scheme:
A kind of data sink, this data sink includes:
First order amplifier；
Second level amplifier；
For connecting negative outfan and the positive of described second level amplifier of described first order amplifier
First load circuit of input；
The negative input of positive output end and second level amplifier for connecting described first order amplifier
Second load circuit of end；
Wherein, described first load circuit is identical with the equivalent resistance of described second load circuit；Described
One load circuit and described second load circuit are for increasing the communication zero point of described data sink.
Preferably, in above-mentioned data sink, described first load circuit includes: the first switching tube,
Second switch pipe, the 3rd switching tube, the first current source and the second current source；
The control end of described 3rd switching tube inputs the first biasing voltage signal, and its first pole is put with the second level
The normal phase input end of big device connects, and its second pole is connected with the negative outfan of described first order amplifier,
And its second pole is by the second current source ground connection；
The control end of described second switch pipe passes through the first current source ground connection, and its first pole connects power supply, its
Second pole is connected with the first pole of described 3rd switching tube；
The end that controls of described first switching tube is connected with the second pole of described second switch pipe, and its first pole is even
Connecing described power supply, described first current source ground connection is passed through in its second pole.
Preferably, in above-mentioned data sink, described first switching tube is NMOS, and described second opens
Closing pipe is PMOS.
Preferably, in above-mentioned data sink, described second load circuit includes: the 4th switching tube,
5th switching tube, the 6th switching tube, the 3rd current source and the 4th current source；
The control end of described 6th switching tube inputs described first biasing voltage signal, its first pole and second
The negative-phase input of level amplifier connects, and its second pole connects with the positive output end of described first order amplifier
Connect, and its second pole is by the 4th current source ground connection；
The control end of described 5th switching tube passes through the 3rd current source ground connection, and its first pole connects described power supply,
Its second pole is connected with the first pole of described 6th switching tube；
The end that controls of described 4th switching tube is connected with the second pole of described 5th switching tube, and its first pole is even
Connecing described power supply, described 3rd current source ground connection is passed through in its second pole.
Preferably, in above-mentioned data sink, described first current source is the 7th switching tube；Described
First pole of seven switching tubes connects the second pole of described first switching tube, and its second pole ground connection, it controls end
Input the second biasing voltage signal；
Described second current source is the 8th switching tube；First pole of described 8th switching tube is opened with the described 3rd
The second pole closing pipe connects, its second pole ground connection, and it controls end and inputs described second biasing voltage signal.
Preferably, in above-mentioned data sink, described 3rd current source is the 9th switching tube；Described
First pole of nine switching tubes connects the second pole of described 4th switching tube, its second pole ground connection, and it controls single
Input described second biasing voltage signal；
Described 4th current source is the tenth switching tube；First pole of described tenth switching tube connects the described 6th
Second pole of switching tube, its second pole ground connection, it controls end and inputs described second biasing voltage signal.
Preferably, in above-mentioned data sink, described first order amplifier includes: the 11st switching tube,
Twelvemo closes pipe and the 13rd switching tube；
The normal phase input end that control end is described first order amplifier of described 11st switching tube, for defeated
Entering the first input signal, its first pole connects the second pole of described 13rd switching tube, and its second pole connects
Second pole of described 3rd switching tube；
Described twelvemo closes the negative-phase input that control end is described first order amplifier of pipe, for defeated
Entering the second input signal, its first pole connects the second pole of described 13rd switching tube, and its second pole connects
Second pole of described 6th switching tube；The control end of described 13rd switching tube is for input the 3rd biased electrical
Pressure signal, its first pole is used for connecting described power supply.
Preferably, in above-mentioned data sink, described 4th switching tube is NMOS, and the described 5th opens
Closing pipe is PMOS.
Preferably, in above-mentioned data sink, described second level amplifier includes: the computing of symmetric form
Trsanscondutance amplifier；
Described second level amplifier has the Miller negative electricity for reducing described first order amplifier output capacitance
Hold.
Preferably, in above-mentioned data sink, described first load circuit includes load switch pipe, institute
State the equivalent output impedance inverse equal to the mutual conductance of described load switch pipe of load switch pipe.By above-mentioned
Describing and understand, the data sink that the present invention provides includes: first order amplifier；Second level amplifier；
The positive input of negative outfan and described second level amplifier for connecting described first order amplifier
First load circuit of end；Positive output end and the second level for connecting described first order amplifier are put
Second load circuit of the negative-phase input of big device；Wherein, described first load circuit is second negative with described
The equivalent resistance carrying circuit is identical；Described first load circuit and described second load circuit are used for increasing institute
State the communication zero point of first order amplifier.The present invention provide data sink by the first load circuit with
Second load circuit is used for increasing communication zero point, and then can improve the band of data amplifier pre-amplifier
Wide.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is only embodiments of the invention, for those of ordinary skill in the art, not
On the premise of paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
The structural representation of a kind of data sink that Fig. 1 provides for the embodiment of the present invention；
The circuit diagram of the another kind of data sink that Fig. 2 provides for the embodiment of the present invention；
The Computing Principle of the equivalent resistance of a kind of first load circuit that Fig. 3 provides for the embodiment of the present invention shows
It is intended to；
The circuit diagram of another data sink that Fig. 4 provides for the embodiment of the present invention；
A kind of bandwidth simulation result schematic diagram that Fig. 5 provides for the embodiment of the present invention；
The structural representation of a kind of second level amplifier that Fig. 6 provides for the embodiment of the present invention；
The another kind of bandwidth simulation result schematic diagram that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under creative work premise, broadly fall into the scope of protection of the invention.
As the nucleus module of D-PHY artificial circuit part, the speed of data sink is to determine D-PHY
The leading indicator of performance.The structure of data sink is general as it is shown in figure 1, Fig. 1 is the embodiment of the present invention
The structural representation of a kind of data sink provided, this data sink includes: first order amplifier 1,
Second level amplifier 2, third level amplifier 3 and buffer 4.Wherein, third level amplifier is double turning
The amplifier of single output.
Data sink is mainly made up of Differential OPAMP structure, and the bandwidth of amplifier directly determines data and passes
Defeated speed.The Main Function of high-speed receiver is accurately to be received by serial differential small-signal and be amplified to
The digital signal of CMOS level, is resent to module below and carries out process such as unstringing.Receptor is faced
Problem be the compromise of gain and bandwidth, the amplifier of one-level is difficulty with, so typically using multistage
Structure, lifting step by step gain on the premise of ensureing bandwidth.Along with gradually rising of gain, signal swing
Constantly increasing, the emphasis of design is not quite similar.The input signal amplitude of oscillation is the least the highest to bandwidth requirement, institute
Bandwidth is more focused on the structure of prime.Pre-amplifier is the first order amplifier of data sink.
Available data amplifier is in order to increase the bandwidth of pre-amplifier, and a kind of mode is by load electricity
An inductance of connecting in resistance makes circuit become a zero point and a pair conjugate complex limit from single real pole, from
And reach the purpose of broadened bandwidth, passive inductors part takies chip and crosses large area, and power consumption is relatively big simultaneously,
Needs consume more multi-power source voltage nargin, and this is difficult to be suitable at low supply voltages.Another way is logical
Cross active inductance and solve area for cutting, but as upper a kind of embodiment, need to consume more electricity
Source voltage margin, this is difficult to be suitable at low supply voltages.In order to solve the problems referred to above, the present invention implements
Example provides a kind of data sink, and this data sink includes:
First order amplifier；
Second level amplifier；
Normal phase input end for the negative outfan and second level amplifier that connect first order amplifier
First load circuit；
For connecting first order amplifier positive output end and the second of second level amplifier negative-phase input
Load circuit；
Wherein, the equivalent resistance of the first load circuit and the second load circuit is identical；First load circuit with
Second load circuit is for increasing the communication zero point of first order amplifier.
Trsanscondutance amplifier in data sink for as the first order amplifier of data sink, second
Level amplifier is for the second pole amplifier as data sink.The negative outfan of first order amplifier
It is connected by the positive output end of the first load circuit with second level amplifier, the positive of first order amplifier
Outfan is connected with the negative outfan of second level amplifier by the second load circuit, by the first load
Circuit and the second load circuit, as the feedback circuit of first order amplifier, increase the logical of data sink
Letter zero point, it is achieved higher bandwidth.
The data sink that the embodiment of the present invention provides can realize being amplified to undistorted for high-speed-differential small-signal
Rail-to-rail digital signal.First load circuit and the second load circuit are made up of active device completely, use
In realizing increasing the function of bandwidth, the first load circuit and the second load circuit do not use passive device,
Thereby saving major part area and power consumption, effectively achieve the function of active inductance.
Technical scheme in order to make the embodiment of the present invention provide is clearer, below in conjunction with the accompanying drawings to above-mentioned side
Case is described in detail.
With reference to the circuit diagram of the another kind of data sink that Fig. 2, Fig. 2 provide for the embodiment of the present invention, this number
Include according to receptor: first order amplifier 11；Second level amplifier 12；For connecting first order amplifier
The negative outfan of 11 and the first load circuit 13 of the normal phase input end of second level amplifier 12；For
Connect the positive output end of first order amplifier 11 and the second of the negative-phase input of second level amplifier 12
Load circuit 14.
Wherein, the first load circuit 13 is identical with the equivalent resistance of the second load circuit 14；First load
Circuit 13 and the second load circuit 14 are for increasing the communication zero point of first order amplifier.
In embodiment of the present invention data sink, by the first load circuit 13 and the second load circuit
14 as the feedback circuit of first order amplifier 11, increases the communication zero point of first order amplifier 11, real
The highest bandwidth.
As in figure 2 it is shown, the first load circuit 13 includes: the first switching tube M1, second switch pipe M2,
3rd switching tube M3, the first current source ISS1And the second current source ISS2.The control of the 3rd switching tube M3
End processed inputs the first biasing voltage signal Bias1, and its first pole inputs with the positive of second level amplifier 12
End connects, and its second pole is connected with the negative outfan of first order amplifier 11, and its second pole passes through the
Two current source ISS2Ground connection；The control end of second switch pipe M2 passes through the first current source ISS1Ground connection, it is years old
One pole connects power vd D, and its second pole is connected with first pole of the 3rd switching tube M3；First switching tube
The end that controls of M1 is connected with second pole of second switch pipe M2, and its first pole connects power vd D, its
The first current source I is passed through in second poleSS1Ground connection.First switching tube M1 is NMOS, and second switch pipe is
PMOSM2。
Second load circuit 14 includes: the 4th switching tube M4, the 5th switching tube M5, the 6th switching tube
M6, the 3rd current source ISS3And the 4th current source ISS4.The control end input first of the 6th switching tube M6
Biasing voltage signal Bias1, its first pole is connected with the negative-phase input of second level amplifier 12, and it is years old
Two poles are connected with the positive output end of first order amplifier 11, and its second pole is by the 4th current source ISS4
Ground connection；The control end of the 5th switching tube M5 passes through the 3rd current source ISS3Ground connection, its first pole connects power supply
VDD, its second pole is connected with first pole of the 6th switching tube M6；The control end of the 4th switching tube M4
Being connected with second pole of the 5th switching tube M5, its first pole connects power vd D, and its second pole is by the
Three current source ISS3Ground connection.
In the embodiment of the present invention, the first load circuit 13 is identical with the second load circuit 14 structure,
Two output simple forms of one amplifier 11 become symmetrical feedback circuit structure.
It should be noted that it is desirable to provide the front two-stage that can improve data sink bandwidth is amplified
Device, data sink shown in Fig. 2 illustrate only the amplifier of front two-stage.Follow up amplifier (put by the third level
Big device and buffer) structure can be identical with the amplifier architecture in tradition.
In data sink shown in Fig. 2, the first load circuit 13 and the second load circuit 14 structure phase
With.Both is the intersection biasing circuit being made up of in PMOS NMOS.Therefore the first load circuit 13
Consumption with the second load circuit 14 can reduce voltage margin, is carried out only with a voltage source VDD
Drive.
Described first load circuit 13 and described second load circuit 14 are respectively provided with load switch pipe.Institute
The equivalent output impedance stating the first load circuit 13 and described second load circuit 14 is equal to described negative
The inverse of the mutual conductance of load switch pipe.In first load circuit 13, second switch pipe M2 is load switch pipe.
In second load circuit 14, the 5th switching tube M5 is load switch pipe.
The source follower separately constituted by the first switching tube M1 and the 4th switching tube M4 makes the negative of respective place
Carry the load switch pipe in circuit and be similar to diode connection, so the output resistance of load switch pipe maintains
At a less 1/gm, gm is the mutual conductance of load switch pipe.In data sink shown in Fig. 2, two
Load switch pipe is PMOS.
Owing to input signal to be amplified by first order amplifier 11 with certain gain, gain is that the first order is put
The mutual conductance Gm of big device 11 and the ratio of the mutual conductance of load PMOS, so can adjust amplifier easily
Compromise between gain and bandwidth, while can increasing dominant pole frequency, it is ensured that the static state of amplifier
Gain.In combination with the application of Miller negative capacitance in second level amplifier 12, effectively reduce the first order and put
The output capacitance of big device 11, overall structure coordinates the high bandwidth realizing first order amplifier 11.
The meter of the equivalent resistance of a kind of first load circuit that reference Fig. 3, Fig. 3 provide for the embodiment of the present invention
Calculate principle schematic.First load circuit is individually analyzed by Fig. 3, the second load circuit and first negative
The analysis carrying circuit is identical, does not repeats them here.
A voltage source V is replaced in the position equivalence of the second current sourceX, from the figure 3, it may be seen that the first load electricity
The equivalent resistance Rout on road is:
Wherein, CGS2For the parasitic capacitance between the first pole and the control end of second switch pipe M2.S is multiple
Number frequency, for the conversion of granny rag Lars and the corresponding relation of Fourier transformation.S=j* ω, j are complex unit,
ω is phase place.gM1It is the mutual conductance of the first switching tube, gM2Mutual conductance for second switch pipe.By above-mentioned Rout
Computing formula it is known that this structural load circuit has a characteristic: the inductive effect under high frequency, this
Individual characteristic can produce a zero point under certain frequency, to compensate due to the limit of bandwidth in transmission line
The high-frequency signal amplitude that system causes declines.The position of zero point and M1, M2 mutual conductance is directly related, Ke Yitong
Overregulate its channel width-over-length ratio and the position of current source size zeroing, and then the regulation first order is amplified
The bandwidth of device and gain.
Having above-mentioned understanding, data sink shown in Fig. 2 can be by the first load circuit and the second load
Circuit, while increasing dominant pole frequency, it is ensured that the static gain of first order amplifier, adjusts easily
Compromise between gain and the bandwidth of whole amplifier.
Each current source in data sink shown in Fig. 2 and implementation such as Fig. 4 of first order amplifier
Shown in, the circuit diagram of another data sink that Fig. 4 provides for the embodiment of the present invention.Shown in Fig. 4
In data sink, illustrate only first order amplifier, the first load circuit and the second load circuit.
As shown in Figure 4, the first current source is the 7th switching tube M7, and first pole of the 7th switching tube M7 is even
Connecing second pole of the first switching tube M1, its second pole ground connection, it controls end and inputs the second biasing voltage signal
Bias2；Second current source is the 8th switching tube M8, first pole of the 8th switching tube M8 and the 3rd switching tube
Second pole of M3 connects, its second pole ground connection, and it controls end and inputs the second biasing voltage signal.
It should be noted that the embodiment of the present invention can provide ground voltage by power supply VSS, it is achieved
Ground connection.
As shown in Figure 4, the 3rd current source is the 9th switching tube M9, and first pole of the 9th switching tube M9 is even
Connecing second pole of the 4th switching tube M4, its second pole ground connection, it controls single input the second biasing voltage signal
Bias2；4th current source is the tenth switching tube M10, and first pole of the tenth switching tube M10 connects the 6th and opens
Closing second pole of pipe M6, its second pole ground connection, it controls end and inputs the second biasing voltage signal Bias2.
As shown in Figure 4, first order amplifier includes: the 11st switching tube M11, twelvemo close pipe M12
And the 13rd switching tube M13.11st switching tube M11 controls the positive that end is first order amplifier
Input, for input the first input signal Vinp, its first pole connects the of the 13rd switching tube M13
Two poles, its second pole connects second pole of the 3rd switching tube M3.Twelvemo closes the control end of pipe M12
For the negative-phase input of first order amplifier, for input the second input signal Vinn, its first pole connects
Second pole of the 13rd switching tube M13, its second pole connects second pole of the 6th switching tube M6；Tenth
The control end of three switching tube M13 is for input the 3rd biasing voltage signal Bias3, and its first pole is for even
Meet power vd D.4th switching tube is NMOS, and the 5th switching tube is PMOS.
It should be noted that in the embodiment of the present invention, each biased electrical can be provided by a biasing circuit
Pressure signal.
The first order amplifier of the core amplifier of data sink, the circuit structure of first order amplifier is such as
Shown in Fig. 4.First order amplifier is for folding amplifier, and the mutual conductance of first order amplifier is true by M11, M12
Fixed.The outfan of the first load circuit and the second load circuit passes through M3, M6 and M8, M10's
Cascaded structure provides a stable electric current, raises output common mode voltage, in the premise that gain is certain simultaneously
Under, bandwidth can be effectively improved.
Use the first order amplifier of load circuit described in the embodiment of the present invention and use tradition pure resistor load
First order amplifier carry out bandwidth Experimental Comparison, simulation result such as Fig. 5, Fig. 5 are that the embodiment of the present invention carries
A kind of bandwidth simulation result schematic diagram of confession.
In Fig. 5, transverse axis represents frequency f, and unit is Hz, and the longitudinal axis represents gain, and unit is dB.Wherein,
Block curve is the simulation curve of first order amplifier described in the embodiment of the present invention, and dashed region is tradition the
The simulation curve of first stage amplifier.From Fig. 5 curve, under identical gain, bandwidth is by 1.05GHz
Improve to 2GHz, it can be seen that due to the effect of high frequency zero, bandwidth has had further lifting.
In data sink shown in Fig. 2, the structure of second level amplifier can as shown in Figure 6, and Fig. 6 is
The structural representation of a kind of second level amplifier that the embodiment of the present invention provides.The second level shown in Fig. 6 is amplified
Device includes: the operation transconductance amplifier of symmetric form；Second level amplifier has for reducing first order amplification
The Miller negative capacitance of device output capacitance.Second level amplifier shown in Fig. 6 includes: the 14th switching tube M14-
25th switching tube M25, the first Miller negative capacitance C1, the second Miller negative capacitance C2, the first filtering
Electric capacity C3 and the second filter capacitor C4.
Wherein, sixteenmo closes second pole of pipe M16 and the public of first pole of the 19th switching tube M19
Node is the forward outfan outn2 of second level amplifier.Second pole of the 24th switching tube M24 with
The negative sense outfan outp2 that common node is second level amplifier of first pole of the 14th switching tube M14.
The ratio of the channel width-over-length ratio of M16, M17, M18 is B:B:1.The raceway groove of M23, M24, M25
The ratio of breadth length ratio is 1:B:B.The ratio of the channel width-over-length ratio of M21, M14 is 1:1.The ditch of M19, M15
The ratio of road breadth length ratio is 1:1.Wherein, B is the positive integer more than 1.
Second level amplifier is with OTA (OperationalTransconductanceAplifier: the fortune of symmetric form
Calculate trsanscondutance amplifier) based on design, it is possible to obtain two-way be exaggerated differential signal.Miller negative capacitance
C1, C2 arrange the output capacitance that can effectively reduce first order amplifier.Owing to flying capcitor is (described
Flying capcitor is Miller negative capacitance C1 in Fig. 6, C2) positive feedback effect, equally put in the first order
Big device produces another communication zero point, can be further compensate for gain, the position of this communication zero point be decided by across
Connect electric capacity (C1, C2 in Fig. 6) size, use with first order amplifiers and can be obviously improved the first order
The bandwidth of amplifier.
C1=C2=C is setC, the position of zero point is with CCThe simulation result of change is as shown in Figure 7.Fig. 7 is
The another kind of bandwidth simulation result schematic diagram that the embodiment of the present invention provides.Fig. 7 shows CCFor 25fF,
Three simulation curves corresponding during 15fF and 5fF.In Fig. 7, transverse axis represents frequency f, and unit is Hz,
The longitudinal axis represents gain, and unit is dB.As shown in Figure 7, as capacitance CCTime different, bandwidth and increasing
Benefit is different.
The present invention is different from general active inductance structure and consumes substantial amounts of voltage margin, but by circuit
The adjustment of structure, i.e. the external structure biasing to load, thus reduces the consumption of voltage margin.Load electricity
The foundation of the overall structure quiescent point on road only needs three overdrive voltages, it is possible to be more easy to be applicable to
In the structure of low supply voltage work.Wherein, overdrive voltage makes metal-oxide-semiconductor be in saturation
Minimum Vds voltage, Vds=Vgs-Vth.Vds represents the drain-source voltage of metal-oxide-semiconductor, and Vgs represents MOS
The gate source voltage of pipe, Vth represents the threshold voltage of metal-oxide-semiconductor.As shown in Figure 4, with the first load circuit
As a example by, symmetrical structure as a example by the first load circuit, six metal-oxide-semiconductors need three overdrive voltages,
As M2, M3, M8 need to be respectively connected to an overdrive voltage.
Simultaneously can be by producing high frequency zero, it is possible to realize the gain compensation under high frequency, it is achieved equalizer
Effect, make full use of the positive feedback character of Miller negative capacitance, strengthen further gain compensation effect, and
And it is achieved in the expansion of bandwidth.
Shown in sum up, in the embodiment of the present invention, two symmetrical load circuits of first order amplifier use
The structure of NMOS and PMOS intersection biasing is for first order amplifier load, to promote bandwidth.Load
The minimum single metal-oxide-semiconductor overdrive voltage of voltage margin consumed, therefore, described data sink is permissible
More convenient it is applied to low-voltage driving.In load circuit, the equivalent output impedance of load switch pipe is 1/gm, can
To facilitate bandwidth and the gain size of compromise regulation amplifier.It is applied simultaneously to the load circuit of this structure
Inductive effect in high frequency, to produce high frequency zero compensating gain, it is achieved Equalizer (equalizer)
Effect.
Use first order amplifier for folding amplifier structure, with taking of the symmetric form OTA of second level amplifier
Arranging meter, the design distinguished of the Miller negative capacitance that second level amplifier is applied only offsets second in tradition
The input capacitance (i.e. reducing second level load capacitance) of level amplifier, is reducing the negative of second level amplifier
While carrying electric capacity, it is also possible to reduce the output capacitance of first order amplifier.Simultaneously by loading with first
Circuit and the second load circuit, make full use of its positive feedback character, the first order produce high frequency zero with
The decay of compensating gain, further enhances the effect of Equalizer.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses
The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art
See, generic principles defined herein can without departing from the spirit or scope of the present invention,
Realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein,
And it is to fit to the widest scope consistent with principles disclosed herein and features of novelty.
Claims (10)
1. a data sink, it is characterised in that including:
First order amplifier；
Second level amplifier；
For connecting negative outfan and the positive of described second level amplifier of described first order amplifier
First load circuit of input；
The negative input of positive output end and second level amplifier for connecting described first order amplifier
Second load circuit of end；
Wherein, described first load circuit is identical with the equivalent resistance of described second load circuit；Described
One load circuit and described second load circuit are for increasing the communication zero point of described data sink.
Data sink the most according to claim 1, it is characterised in that described first load circuit
Including: the first switching tube, second switch pipe, the 3rd switching tube, the first current source and the second current source；
The control end of described 3rd switching tube inputs the first biasing voltage signal, and its first pole is put with the second level
The normal phase input end of big device connects, and its second pole is connected with the negative outfan of described first order amplifier,
And its second pole is by the second current source ground connection；
The control end of described second switch pipe passes through the first current source ground connection, and its first pole connects power supply, its
Second pole is connected with the first pole of described 3rd switching tube；
The end that controls of described first switching tube is connected with the second pole of described second switch pipe, and its first pole is even
Connecing described power supply, described first current source ground connection is passed through in its second pole.
Data sink the most according to claim 2, it is characterised in that described first switching tube is
NMOS, described second switch pipe is PMOS.
Data sink the most according to claim 2, it is characterised in that described second load circuit
Including: the 4th switching tube, the 5th switching tube, the 6th switching tube, the 3rd current source and the 4th current source；
The control end of described 6th switching tube inputs described first biasing voltage signal, its first pole and second
The negative-phase input of level amplifier connects, and its second pole connects with the positive output end of described first order amplifier
Connect, and its second pole is by the 4th current source ground connection；
The control end of described 5th switching tube passes through the 3rd current source ground connection, and its first pole connects described power supply,
Its second pole is connected with the first pole of described 6th switching tube；
The end that controls of described 4th switching tube is connected with the second pole of described 5th switching tube, and its first pole is even
Connecing described power supply, described 3rd current source ground connection is passed through in its second pole.
Data sink the most according to claim 4, it is characterised in that described first current source is
7th switching tube；First pole of described 7th switching tube connects the second pole of described first switching tube, and it is the years old
Two pole ground connection, it controls end and inputs the second biasing voltage signal；
Described second current source is the 8th switching tube；First pole of described 8th switching tube is opened with the described 3rd
The second pole closing pipe connects, its second pole ground connection, and it controls end and inputs described second biasing voltage signal.
Data sink the most according to claim 4, it is characterised in that described 3rd current source is
9th switching tube；First pole of described 9th switching tube connects the second pole of described 4th switching tube, and it is the years old
Two pole ground connection, it controls the second biasing voltage signal described in single input；
Described 4th current source is the tenth switching tube；First pole of described tenth switching tube connects the described 6th
Second pole of switching tube, its second pole ground connection, it controls end and inputs described second biasing voltage signal.
Data sink the most according to claim 4, it is characterised in that described first order amplifier
Including: the 11st switching tube, twelvemo close pipe and the 13rd switching tube；
The normal phase input end that control end is described first order amplifier of described 11st switching tube, for defeated
Entering the first input signal, its first pole connects the second pole of described 13rd switching tube, and its second pole connects
Second pole of described 3rd switching tube；
Described twelvemo closes the negative-phase input that control end is described first order amplifier of pipe, for defeated
Entering the second input signal, its first pole connects the second pole of described 13rd switching tube, and its second pole connects
Second pole of described 6th switching tube；The control end of described 13rd switching tube is for input the 3rd biased electrical
Pressure signal, its first pole is used for connecting described power supply.
Data sink the most according to claim 4, it is characterised in that described 4th switching tube is
NMOS, described 5th switching tube is PMOS.
Data sink the most according to claim 1, it is characterised in that described second level amplifier
Including: the operation transconductance amplifier of symmetric form；
Described second level amplifier has the Miller negative electricity for reducing described first order amplifier output capacitance
Hold.
Data sink the most according to claim 1, it is characterised in that described first load electricity
Road includes load switch pipe, and the equivalent output impedance of described load switch pipe is equal to described load switch pipe
The inverse of mutual conductance.
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| CN107947748A (en) * | 2016-10-13 | 2018-04-20 | 智原科技股份有限公司 | Variable gain amplifier |
| CN113551770A (en) * | 2021-07-23 | 2021-10-26 | 中国科学院半导体研究所 | Terahertz wave amplitude and phase reading device |
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| CN101677230A (en) * | 2008-09-15 | 2010-03-24 | 联发科技（新加坡）私人有限公司 | three-stage frequency-compensated operational amplifier |
| CN102386859A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Wide band amplifier with frequency compensation |
| US20120268086A1 (en) * | 2011-04-19 | 2012-10-25 | Hon Hai Precision Industry Co., Ltd. | Power supply device |
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| CN107947748B (en) * | 2016-10-13 | 2020-06-09 | 智原科技股份有限公司 | Variable gain amplifier |
| CN113551770A (en) * | 2021-07-23 | 2021-10-26 | 中国科学院半导体研究所 | Terahertz wave amplitude and phase reading device |
| CN113551770B (en) * | 2021-07-23 | 2023-12-29 | 中国科学院半导体研究所 | Terahertz wave amplitude and phase reading device |
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|---|---|
| CN105958953B (en) | 2019-05-31 |
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