CN104283546A - Low-voltage differential signal driver - Google Patents
Low-voltage differential signal driver Download PDFInfo
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- CN104283546A CN104283546A CN201310275469.1A CN201310275469A CN104283546A CN 104283546 A CN104283546 A CN 104283546A CN 201310275469 A CN201310275469 A CN 201310275469A CN 104283546 A CN104283546 A CN 104283546A
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- nmos pass
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Abstract
The invention provides a low-voltage differential signal driver. The low-voltage differential signal driver comprises a main driving circuit and a common-mode feedback network. The main driving circuit is used for generating high-speed differential transmission data with low voltage swing. The common-mode feedback network is connected with the main driving circuit and used for comparing common-mode voltage at the output end of the main driving circuit with target common-mode voltage so as to adjust the common-mode voltage to the level of the target common-mode voltage. The low-voltage differential signal driver greatly improves the stability of the driving circuit and increases the working speed of the driving circuit.
Description
Technical field
The present invention relates to circuit engineering field, refer to a kind of low-voltage differential signal driver especially.
Background technology
LVDS(Low Voltage Differential Signaling, Low Voltage Differential Signal) be a kind of transfer of data and interfacing that just occur the nineties in 20th century.The core of this technology adopts extremely low voltage swing high speed differential transmission data, can realize connection that is point-to-point or point to multi--point, have the features such as low-power consumption, low error rate, low crosstalk and Low emissivity.
Typical lvds driver is the current source in an energy high speed switch current direction, and output current sets up the correct differential output voltage amplitude of oscillation at load resistance two ends.Conventional LVDS driver as shown in Figure 1, comprising: four transistor M11, M21, M31, M41 and a load resistance R
l, wherein, the grid of transistor M11, M41 is connected with input signal IN1; The grid of transistor M21, M31 is connected with input signal IN2, current source I
sSoutput current is provided, along with the switching of incoming level, load resistance R
lon the sense of current also change thereupon, so just set up correct differential output voltage V at resistance two ends
rL=± I
sS× R
l.
Because in the noise inside and outside chip and work, the change of PVT is easy to the skew and the fluctuation that cause common mode electrical level in signals transmission, this is just difficult to the requirement ensureing to reach LVDS international standard, and output common mode level to the characteristic of device and mismatch quite responsive, and do not reach stable by differential feedback.Therefore, for this traditional structure, in lvds driver, the common mode electrical level of the LVDS signal exported cannot be realized accurately, just need to add common mode feedback circuit and carry out stable output common mode level.And the existence due to output node parasitic capacitance seriously constrains the operating rate of circuit, greatly limit the application of this circuit in high speed situation.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of low-voltage differential signal driver, can guarantee the stable of output signal, improve operating rate, increase driving force.
For solving the problems of the technologies described above, embodiments of the invention provide a kind of low-voltage differential signal driver, comprising:
Main body drive circuit, for generation of the high speed differential transmission data of the low-voltage amplitude of oscillation;
Common-mode feedback network, is connected with described main body drive circuit, for the common-mode voltage of the output by described main body drive circuit compared with target common-mode voltage, described common-mode voltage to be adjusted to the level of described target common-mode voltage.
Wherein, described main body drive circuit comprises:
First nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor and the 6th nmos pass transistor, pre-charge and discharge capacitance, the first filter capacitor, the second filter capacitor and load;
The grid of described first nmos pass transistor is connected with first input end signal respectively with the grid of described 4th nmos pass transistor;
The grid of described second nmos pass transistor is connected with the second input end signal respectively with the grid of described 3rd nmos pass transistor;
The source electrode of described first nmos pass transistor connects the described drain electrode of the 3rd nmos pass transistor and one end of load respectively, and the source electrode of described second nmos pass transistor connects the described drain electrode of the 4th nmos pass transistor and the other end of load respectively;
Described 5th nmos pass transistor is used as current source, and its grid connects described common-mode feedback network, and drain electrode is connected with power supply, and source electrode connects one end of the drain electrode of described first nmos pass transistor, the drain electrode of described second nmos pass transistor and described pre-charge and discharge capacitance respectively;
Described 6th nmos pass transistor is used as current source, and its grid connects described common-mode feedback network, source ground, and drain the source electrode, the source electrode of described 4th nmos pass transistor and the other end of described pre-charge and discharge capacitance that connect described 3rd nmos pass transistor respectively;
One end of described first filter capacitor connects the grid of described 5th nmos pass transistor, and the other end connects the drain electrode of described first nmos pass transistor;
One end of described second filter capacitor connects the source electrode of described 3rd nmos pass transistor, and the other end connects the grid of described 6th nmos pass transistor.
Wherein, described first input end signal and described second input end signal are complementary fully differential signals.
Wherein, described common-mode feedback network comprises:
7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the first resistance and the second resistance;
One end of described first resistance connects the source electrode of described first nmos pass transistor, and the other end connects the grid of described 11 nmos pass transistor;
One end of described second resistance connects the source electrode of described second nmos pass transistor, and the other end connects the grid of described 11 nmos pass transistor;
The source electrode of described 7th PMOS transistor, the source electrode of described 8th PMOS transistor are connected with power supply respectively with the source electrode of described 9th PMOS transistor;
Described 7th PMOS transistor and described 8th PMOS transistor form current mirror pattern, as the load of described common-mode feedback network;
The grid of described 7th PMOS transistor connects the grid of described 8th PMOS transistor and the drain electrode of described 8th PMOS transistor respectively, and its drain electrode connects the drain electrode of described tenth nmos pass transistor;
The drain electrode of described 8th PMOS transistor connects the drain electrode of described 11 nmos pass transistor;
Described 9th PMOS transistor and described 5th nmos pass transistor form current mirror pattern, and the grid of described 9th PMOS transistor connects the drain electrode of described 9th PMOS transistor and the grid of described 5th nmos pass transistor respectively;
Described tenth nmos pass transistor and described 6th nmos pass transistor form current mirror pattern, and the grid of described tenth nmos pass transistor connects the drain electrode of described tenth nmos pass transistor and the grid of described 6th nmos pass transistor respectively;
The source electrode of described 11 nmos pass transistor is connected with the drain electrode of described 13 nmos pass transistor respectively with the source electrode of described tenth bi-NMOS transistor;
The grid of described tenth bi-NMOS transistor connects described target common-mode voltage, and its drain electrode connects the drain electrode of described 9th PMOS transistor;
The source electrode of described tenth nmos pass transistor and the source electrode of described 13 nmos pass transistor ground connection respectively;
The grid of described 13 nmos pass transistor connects a bias voltage.
The beneficial effect of technique scheme of the present invention is as follows:
Such scheme, compared with traditional lvds driver, the pre-charge and discharge capacitance of increase improves the charge/discharge rates of load, reduces load parasitic capacitance to the impact of circuit working speed.The improvement of above two aspects substantially increases stability and the operating rate of drive circuit.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of conventional LVDS driver;
Fig. 2 is the principle assumption diagram of common-mode feedback;
Fig. 3 is the circuit diagram of low-voltage differential signal driver of the present invention.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
As shown in Figure 3, embodiments of the invention provide a kind of low-voltage differential signal driver, comprising:
Main body drive circuit, for generation of the high speed differential transmission data of the low-voltage amplitude of oscillation;
Common-mode feedback network, is connected with described main body drive circuit, for the common-mode voltage of the output by described main body drive circuit compared with target common-mode voltage, described common-mode voltage to be adjusted to the level of described target common-mode voltage.
Wherein, described main body drive circuit comprises:
First nmos pass transistor M1, the second nmos pass transistor M2, the 3rd nmos pass transistor M3, the 4th nmos pass transistor M4, the 5th nmos pass transistor M5 and the 6th nmos pass transistor (M6), pre-charge and discharge capacitance C
p, the first filter capacitor C1, the second filter capacitor C2 and load (R
l);
The grid of described first nmos pass transistor M1 is connected with first input end signal IN1 respectively with the grid of described 4th nmos pass transistor M4;
The grid of described second nmos pass transistor M2 is connected with the second input end signal IN2 respectively with the grid of described 3rd nmos pass transistor M3;
The source electrode of described first nmos pass transistor M1 connects drain electrode and the load R of described 3rd nmos pass transistor M3 respectively
lone end, the source electrode of described second nmos pass transistor M2 connects drain electrode and the load R of described 4th nmos pass transistor M4 respectively
lthe other end;
Described 5th nmos pass transistor M5 is used as current source, and its grid connects described common-mode feedback network, and drain electrode is connected with power supply, and source electrode connects the drain electrode of described first nmos pass transistor M1, the drain electrode of described second nmos pass transistor M2 and described pre-charge and discharge capacitance C respectively
pone end;
Described 6th nmos pass transistor M6 is used as current source, and its grid connects described common-mode feedback network, source ground, and drain electrode connects the source electrode of described 3rd nmos pass transistor M3, the source electrode of described 4th nmos pass transistor M4 and described pre-charge and discharge capacitance C respectively
pthe other end;
One end of described first filter capacitor C1 connects the grid of described 5th nmos pass transistor M5, and the other end connects the drain electrode of described first nmos pass transistor;
One end of described second filter capacitor C2 connects the source electrode of described 3rd nmos pass transistor M3, and the other end connects the grid of described 6th nmos pass transistor M6.
Wherein, described first input end signal IN1 and described second input end signal IN2 is complementary fully differential signal.
Wherein, described common-mode feedback network comprises:
7th PMOS transistor M7, the 8th PMOS transistor M8, the 9th PMOS transistor M9, the tenth nmos pass transistor M10, the 11 nmos pass transistor M11, the tenth bi-NMOS transistor M12, the 13 nmos pass transistor M13, the first resistance R1 and the second resistance R2;
One end of described first resistance R1 connects the source electrode of described first nmos pass transistor M1, and the other end connects the grid of described 11 nmos pass transistor M11;
One end of described second resistance R2 connects the source electrode of described second nmos pass transistor M2, and the other end connects the grid of described 11 nmos pass transistor M11;
The source electrode of described 7th PMOS transistor M7, the source electrode of described 8th PMOS transistor M8 are connected with power supply respectively with the source electrode of described 9th PMOS transistor M9;
Described 7th PMOS transistor M7 and described 8th PMOS crystal M8 pipe form current mirror pattern, as the load of described common-mode feedback network;
The grid of described 7th PMOS transistor M7 connects the grid of described 8th PMOS transistor M8 and the drain electrode of described 8th PMOS transistor M8 respectively, and its drain electrode connects the drain electrode of described tenth nmos pass transistor M10;
The drain electrode of described 8th PMOS transistor M8 connects the drain electrode of described 11 nmos pass transistor M11;
Described 9th PMOS transistor M9 and described 5th nmos pass transistor M5 forms current mirror pattern, and the grid of described 9th PMOS transistor M9 connects the drain electrode of described 9th PMOS transistor M9 and the grid of described 5th nmos pass transistor M5 respectively;
Described tenth nmos pass transistor M10 and described 6th nmos pass transistor M6 forms current mirror pattern, and the grid of described tenth nmos pass transistor M10 connects the drain electrode of described tenth nmos pass transistor M10 and the grid of described 6th nmos pass transistor M6 respectively;
The source electrode of described 11 nmos pass transistor M11 is connected with the drain electrode of described 13 nmos pass transistor M13 respectively with the source electrode of described tenth bi-NMOS transistor M12;
The grid of described tenth bi-NMOS transistor M12 connects described target common-mode voltage, and its drain electrode connects the drain electrode of described 9th PMOS transistor M9;
The source electrode of described tenth nmos pass transistor M10 and the source electrode of described 13 nmos pass transistor M13 ground connection respectively;
The grid of described 13 nmos pass transistor M13 connects a bias voltage.
Wherein, pre-charge and discharge capacitance C
poperation principle as follows:
For ease of analyzing, if flow through described load resistance R
lon electric current be I
ss, the parasitic capacitance of existence is CL.When described first nmos pass transistor and the described 4th nmos transistor switch unlatching of described first input end signal controlling, C
pboth positive and negative polarity between stored charge, set up I
sSr
lvoltage difference; When described second nmos pass transistor that described second input end signal controls and described 3rd nmos transistor switch are opened, now C
pand C
lthe polarity of electric charge does not also change, C
pthe electric charge stored and C
lcharge bonded, make R instantaneously
lon voltage by I
sSr
lbecome
Visible, during switching over, R
lboth end voltage can rapidly from I
sSr
lbecome
greatly improve the charge/discharge rates of load.
The working method of common-mode feedback network is:
If described first input end signal and described second input end signal reduce, the common-mode voltage of the output of described main body drive circuit is caused to be less than target common-mode voltage, then the gate voltage of described 6th nmos pass transistor can reduce, thus the electric current flowing through described load can reduce, the common-mode voltage of the output of described main body drive circuit will raise.In like manner, if described first input end signal and described second input end signal raise, the common-mode voltage of the output of described main body drive circuit is caused to be greater than target common-mode voltage, then the gate voltage of described 6th nmos pass transistor can raise, thus the electric current flowing through described load can increase, the common-mode voltage of the output of described main body drive circuit will reduce.Visible, common-mode feedback network stabilizes the common-mode voltage of lvds driver output signal.In addition, in order to improve drive performance, in circuit, also add some filter capacitors, thus when making switch state, electric current is more steady, and signal is more stable.
According to the viewpoint of reponse system, the common mode feedback circuit needed for driver mainly contains three tasks: detect output common mode level; Common mode electrical level and a fixed reference level are compared; Send error back to biasing networks.Fig. 2 conceptually illustrates this thought.In Fig. 2, detect the common mode electrical level of two outputs by increasing common-mode feedback network, and with good grounds ground resonance-amplifier offset current.Namely adopt common mode electrical level testing circuit to detect the common mode electrical level of output end vo ut1 and Vout2, after itself and a fixed reference level Vref are compared, send error back to amplifier thus change its bias current and reach stable.
The above embodiment of the present invention is guarantee stablizing of output signal, improve operating rate, increase driving force, introduce common-mode feedback CMFB (Common Mode Feedback) and stablize the common mode electrical level exporting LVDS signal, there is skew and the fluctuation of common mode electrical level in anti-stop signal, and increase a pre-charge and discharge capacitance to reduce the impact of load parasitic capacitance on circuit working speed in transmitting procedure.By the improvement to above two aspects, substantially increase stability and the operating rate of drive circuit.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. a low-voltage differential signal driver, is characterized in that, comprising:
Main body drive circuit, for generation of the high speed differential transmission data of the low-voltage amplitude of oscillation;
Common-mode feedback network, is connected with described main body drive circuit, for the common-mode voltage of the output by described main body drive circuit compared with target common-mode voltage, described common-mode voltage to be adjusted to the level of described target common-mode voltage.
2. low-voltage differential signal driver according to claim 1, is characterized in that, described main body drive circuit comprises:
First nmos pass transistor (M1), the second nmos pass transistor (M2), the 3rd nmos pass transistor (M3), the 4th nmos pass transistor (M4), the 5th nmos pass transistor (M5) and the 6th nmos pass transistor (M6), pre-charge and discharge capacitance (C
p), the first filter capacitor (C1), the second filter capacitor (C2) and load (R
l);
The grid of described first nmos pass transistor (M1) is connected with first input end signal (IN1) respectively with the grid of described 4th nmos pass transistor (M4);
The grid of described second nmos pass transistor (M2) is connected with the second input end signal (IN2) respectively with the grid of described 3rd nmos pass transistor (M3);
The source electrode of described first nmos pass transistor (M1) connects drain electrode and the load (R of described 3rd nmos pass transistor (M3) respectively
l) one end, the source electrode of described second nmos pass transistor (M2) connects drain electrode and the load (R of described 4th nmos pass transistor (M4) respectively
l) the other end;
Described 5th nmos pass transistor (M5) is as current source, its grid connects described common-mode feedback network, drain electrode is connected with power supply, and source electrode connects the drain electrode of described first nmos pass transistor (M1), the drain electrode of described second nmos pass transistor (M2) and described pre-charge and discharge capacitance (C respectively
p) one end;
Described 6th nmos pass transistor (M6) is as current source, its grid connects described common-mode feedback network, source ground, drain electrode connects the source electrode of described 3rd nmos pass transistor (M3), the source electrode of described 4th nmos pass transistor (M4) and described pre-charge and discharge capacitance (C respectively
p) the other end;
One end of described first filter capacitor (C1) connects the grid of described 5th nmos pass transistor (M5), and the other end connects the drain electrode of described first nmos pass transistor;
One end of described second filter capacitor (C2) connects the source electrode of described 3rd nmos pass transistor (M3), and the other end connects the grid of described 6th nmos pass transistor (M6).
3. low-voltage differential signal driver according to claim 2, is characterized in that, described first input end signal (IN1) and described second input end signal (IN2) are complementary fully differential signals.
4. low-voltage differential signal driver according to claim 1, is characterized in that, described common-mode feedback network comprises:
7th PMOS transistor (M7), the 8th PMOS transistor (M8), the 9th PMOS transistor (M9), the tenth nmos pass transistor (M10), the 11 nmos pass transistor (M11), the tenth bi-NMOS transistor (M12), the 13 nmos pass transistor (M13), the first resistance (R1) and the second resistance (R2);
One end of described first resistance (R1) connects the source electrode of described first nmos pass transistor (M1), and the other end connects the grid of described 11 nmos pass transistor (M11);
One end of described second resistance (R2) connects the source electrode of described second nmos pass transistor (M2), and the other end connects the grid of described 11 nmos pass transistor (M11);
The source electrode of described 7th PMOS transistor (M7), the source electrode of described 8th PMOS transistor (M8) are connected with power supply respectively with the source electrode of described 9th PMOS transistor (M9);
Described 7th PMOS transistor (M7) and described 8th PMOS crystal (M8) pipe form current mirror pattern, as the load of described common-mode feedback network;
The grid of described 7th PMOS transistor (M7) connects the grid of described 8th PMOS transistor (M8) and the drain electrode of described 8th PMOS transistor (M8) respectively, and its drain electrode connects the drain electrode of described tenth nmos pass transistor (M10);
The drain electrode of described 8th PMOS transistor (M8) connects the drain electrode of described 11 nmos pass transistor (M11);
Described 9th PMOS transistor (M9) and described 5th nmos pass transistor (M5) form current mirror pattern, and the grid of described 9th PMOS transistor (M9) connects the drain electrode of described 9th PMOS transistor (M9) and the grid of described 5th nmos pass transistor (M5) respectively;
Described tenth nmos pass transistor (M10) and described 6th nmos pass transistor (M6) form current mirror pattern, and the grid of described tenth nmos pass transistor (M10) connects the drain electrode of described tenth nmos pass transistor (M10) and the grid of described 6th nmos pass transistor (M6) respectively;
The source electrode of described 11 nmos pass transistor (M11) is connected with the drain electrode of described 13 nmos pass transistor (M13) respectively with the source electrode of described tenth bi-NMOS transistor (M12);
The grid of described tenth bi-NMOS transistor (M12) connects described target common-mode voltage, and its drain electrode connects the drain electrode of described 9th PMOS transistor (M9);
The source electrode of described tenth nmos pass transistor (M10) and the source electrode of described 13 nmos pass transistor (M13) ground connection respectively;
The grid of described 13 nmos pass transistor (M13) connects a bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310275469.1A CN104283546A (en) | 2013-07-02 | 2013-07-02 | Low-voltage differential signal driver |
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|---|---|---|---|
| CN201310275469.1A CN104283546A (en) | 2013-07-02 | 2013-07-02 | Low-voltage differential signal driver |
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| CN104283546A true CN104283546A (en) | 2015-01-14 |
Family
ID=52258095
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| CN201310275469.1A Pending CN104283546A (en) | 2013-07-02 | 2013-07-02 | Low-voltage differential signal driver |
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| CN105577164A (en) * | 2016-01-20 | 2016-05-11 | 北京时代民芯科技有限公司 | Single event transient resistant differential driver applicable to FPGA for space flight |
| CN106656150A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | Drive circuit used for LVDS sending end |
| CN107979367A (en) * | 2017-12-14 | 2018-05-01 | 上海玮舟微电子科技有限公司 | A kind of high speed long arc differential driver and differential data interface system |
| CN109327217A (en) * | 2018-11-21 | 2019-02-12 | 灿芯半导体(上海)有限公司 | A kind of LVDS transmitting line |
| CN109923784A (en) * | 2016-11-08 | 2019-06-21 | 高通股份有限公司 | For the device and method based on different electrical power voltage transmission data-signal |
| CN110121685A (en) * | 2016-12-22 | 2019-08-13 | 新日本无线株式会社 | Power circuit |
| CN115580288A (en) * | 2022-12-08 | 2023-01-06 | 中科亿海微电子科技（苏州）有限公司 | Driver capable of expanding low-voltage signaling standard and driving method thereof |
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| CN106656150A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | Drive circuit used for LVDS sending end |
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| CN109923784A (en) * | 2016-11-08 | 2019-06-21 | 高通股份有限公司 | For the device and method based on different electrical power voltage transmission data-signal |
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| CN110121685A (en) * | 2016-12-22 | 2019-08-13 | 新日本无线株式会社 | Power circuit |
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| CN107979367A (en) * | 2017-12-14 | 2018-05-01 | 上海玮舟微电子科技有限公司 | A kind of high speed long arc differential driver and differential data interface system |
| CN109327217A (en) * | 2018-11-21 | 2019-02-12 | 灿芯半导体(上海)有限公司 | A kind of LVDS transmitting line |
| CN115580288A (en) * | 2022-12-08 | 2023-01-06 | 中科亿海微电子科技（苏州）有限公司 | Driver capable of expanding low-voltage signaling standard and driving method thereof |
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