CN104283546A - Low-voltage differential signal driver - Google Patents

Abstract

The invention provides a low-voltage differential signal driver. The low-voltage differential signal driver comprises a main driving circuit and a common-mode feedback network. The main driving circuit is used for generating high-speed differential transmission data with low voltage swing. The common-mode feedback network is connected with the main driving circuit and used for comparing common-mode voltage at the output end of the main driving circuit with target common-mode voltage so as to adjust the common-mode voltage to the level of the target common-mode voltage. The low-voltage differential signal driver greatly improves the stability of the driving circuit and increases the working speed of the driving circuit.

Description

A Low Voltage Differential Signal Driver

technical field

The invention relates to the field of circuit technology, in particular to a low-voltage differential signal driver.

Background technique

LVDS (Low Voltage Differential Signaling) is a data transmission and interface technology that only appeared in the 1990s. The core of this technology is high-speed differential data transmission with extremely low voltage swing, which can realize point-to-point or point-to-multipoint connection, and has the characteristics of low power consumption, low bit error rate, low crosstalk and low radiation.

A typical LVDS driver is a current source that switches current direction at high speed, and the output current establishes the correct differential output voltage swing across the load resistor. The traditional LVDS driver as shown in Fig. 1, comprises: four transistors M11, M21, M31, M41 and a load resistance _RL , wherein, the gate of transistor M11, M41 is connected with input signal IN1; Transistor M21, M31 The gate is connected to the input signal IN2, and the current source I _SS provides the output current. As the input level is switched, the current direction on the load resistor _RL also changes, so that the correct differential output voltage V is established across the resistor. _RL =±I _SS × _RL .

Due to the noise inside and outside the chip and the change of PVT during work, it is easy to cause the shift and fluctuation of the common mode level in the signal transmission process, which is difficult to ensure that the requirements of the LVDS international standard are met, and the output common mode level has a great influence on the characteristics of the device. and mismatch are quite sensitive and cannot be stabilized by differential feedback. Therefore, for this traditional structure, it is impossible to accurately realize the common-mode level of the output LVDS signal in the LVDS driver, and it is necessary to add a common-mode feedback circuit to stabilize the output common-mode level. And because the existence of the parasitic capacitance of the output node seriously restricts the working speed of the circuit, it greatly limits the application of this circuit in high-speed occasions.

Contents of the invention

The technical problem to be solved by the present invention is to provide a low-voltage differential signal driver, which can ensure the stability of the output signal, improve the working speed and increase the driving capacity.

In order to solve the above technical problems, an embodiment of the present invention provides a low-voltage differential signal driver, including:

The main drive circuit is used to generate high-speed differential transmission data with low voltage swing;

a common-mode feedback network, connected to the main body driving circuit, for comparing the common-mode voltage at the output terminal of the main body driving circuit with a target common-mode voltage, so as to adjust the common-mode voltage to the target common-mode voltage Level.

Wherein, the main body drive circuit includes:

A first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor, a pre-charge and discharge capacitor, a first filter capacitor, a second filter capacitor, and a load;

The gate of the first NMOS transistor and the gate of the fourth NMOS transistor are respectively signal-connected to the first input terminal;

The gate of the second NMOS transistor and the gate of the third NMOS transistor are respectively signal-connected to the second input terminal;

The source of the first NMOS transistor is respectively connected to the drain of the third NMOS transistor and one end of the load, and the source of the second NMOS transistor is respectively connected to the drain of the fourth NMOS transistor and the other end of the load ;

The fifth NMOS transistor is used as a current source, its gate is connected to the common-mode feedback network, its drain is connected to a power supply, and its source is respectively connected to the drain of the first NMOS transistor and the drain of the second NMOS transistor. pole and one end of the pre-charge and discharge capacitor;

The sixth NMOS transistor is used as a current source, its gate is connected to the common-mode feedback network, its source is grounded, and its drain is respectively connected to the source of the third NMOS transistor, the source of the fourth NMOS transistor, and the The other end of the pre-charge and discharge capacitor;

One end of the first filter capacitor is connected to the gate of the fifth NMOS transistor, and the other end is connected to the drain of the first NMOS transistor;

One end of the second filter capacitor is connected to the source of the third NMOS transistor, and the other end is connected to the gate of the sixth NMOS transistor.

Wherein, the first input signal and the second input signal are complementary fully differential signals.

Wherein, the common mode feedback network includes:

a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a first resistor, and a second resistor;

One end of the first resistor is connected to the source of the first NMOS transistor, and the other end is connected to the gate of the eleventh NMOS transistor;

One end of the second resistor is connected to the source of the second NMOS transistor, and the other end is connected to the gate of the eleventh NMOS transistor;

The source of the seventh PMOS transistor, the source of the eighth PMOS transistor, and the source of the ninth PMOS transistor are respectively connected to a power supply;

The seventh PMOS transistor and the eighth PMOS transistor form a current mirror mode as a load of the common-mode feedback network;

The gate of the seventh PMOS transistor is respectively connected to the gate of the eighth PMOS transistor and the drain of the eighth PMOS transistor, and the drain is connected to the drain of the tenth NMOS transistor;

The drain of the eighth PMOS transistor is connected to the drain of the eleventh NMOS transistor;

The ninth PMOS transistor and the fifth NMOS transistor form a current mirror mode, and the gate of the ninth PMOS transistor is respectively connected to the drain of the ninth PMOS transistor and the gate of the fifth NMOS transistor;

The tenth NMOS transistor and the sixth NMOS transistor form a current mirror mode, and the gate of the tenth NMOS transistor is respectively connected to the drain of the tenth NMOS transistor and the gate of the sixth NMOS transistor;

The source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are respectively connected to the drain of the thirteenth NMOS transistor;

The gate of the twelfth NMOS transistor is connected to the target common-mode voltage, and the drain thereof is connected to the drain of the ninth PMOS transistor;

The source of the tenth NMOS transistor and the source of the thirteenth NMOS transistor are respectively grounded;

The gate of the thirteenth NMOS transistor is connected to a bias voltage.

The beneficial effects of above-mentioned technical scheme of the present invention are as follows:

Compared with the traditional LVDS driver, the above solution increases the charging and discharging speed of the load by increasing the pre-charging and discharging capacitance, and reduces the influence of the parasitic capacitance of the load on the working speed of the circuit. The improvements in the above two aspects have greatly improved the stability and working speed of the drive circuit.

Description of drawings

Figure 1 is a circuit diagram of a traditional LVDS driver;

Fig. 2 is a schematic structural diagram of common mode feedback;

FIG. 3 is a circuit diagram of a low voltage differential signal driver according to the present invention.

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

As shown in Figure 3, an embodiment of the present invention provides a low-voltage differential signal driver, including:

The main drive circuit is used to generate high-speed differential transmission data with low voltage swing;

a common-mode feedback network, connected to the main body driving circuit, for comparing the common-mode voltage at the output terminal of the main body driving circuit with a target common-mode voltage, so as to adjust the common-mode voltage to the target common-mode voltage Level.

Wherein, the main body drive circuit includes:

The first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5 and the sixth NMOS transistor (M6), the pre-charge and discharge capacitor C _P , and the first filter capacitor C1 , the second filter capacitor C2 and the load (R _L );

The gate of the first NMOS transistor M1 and the gate of the fourth NMOS transistor M4 are respectively connected to the first input terminal signal IN1;

The gate of the second NMOS transistor M2 and the gate of the third NMOS transistor M3 are respectively connected to the second input terminal signal IN2;

The source of the first NMOS transistor M1 is respectively connected to the drain of the third NMOS transistor M3 and one end of the load _RL , and the source of the second NMOS transistor M2 is respectively connected to the drain of the fourth NMOS transistor M4 Pole and the other end of the load _RL ;

The fifth NMOS transistor M5 is used as a current source, its gate is connected to the common-mode feedback network, its drain is connected to a power supply, and its source is respectively connected to the drain of the first NMOS transistor M1 and the second NMOS transistor The drain of M2 and one end of the pre-charge and discharge capacitor C _P ;

The sixth NMOS transistor M6 is used as a current source, its gate is connected to the common-mode feedback network, its source is grounded, and its drain is respectively connected to the source of the third NMOS transistor M3 and the source of the fourth NMOS transistor M4. source and the other end of the pre-charge and discharge capacitor C _P ;

One end of the first filter capacitor C1 is connected to the gate of the fifth NMOS transistor M5, and the other end is connected to the drain of the first NMOS transistor;

One end of the second filter capacitor C2 is connected to the source of the third NMOS transistor M3, and the other end is connected to the gate of the sixth NMOS transistor M6.

Wherein, the first input signal IN1 and the second input signal IN2 are complementary fully differential signals.

Wherein, the common mode feedback network includes:

The seventh PMOS transistor M7, the eighth PMOS transistor M8, the ninth PMOS transistor M9, the tenth NMOS transistor M10, the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the first resistor R1, and a second resistor R2;

One end of the first resistor R1 is connected to the source of the first NMOS transistor M1, and the other end is connected to the gate of the eleventh NMOS transistor M11;

One end of the second resistor R2 is connected to the source of the second NMOS transistor M2, and the other end is connected to the gate of the eleventh NMOS transistor M11;

The source of the seventh PMOS transistor M7, the source of the eighth PMOS transistor M8, and the source of the ninth PMOS transistor M9 are respectively connected to a power supply;

The seventh PMOS transistor M7 and the eighth PMOS transistor M8 form a current mirror mode as a load of the common-mode feedback network;

The gate of the seventh PMOS transistor M7 is respectively connected to the gate of the eighth PMOS transistor M8 and the drain of the eighth PMOS transistor M8, and the drain is connected to the drain of the tenth NMOS transistor M10;

The drain of the eighth PMOS transistor M8 is connected to the drain of the eleventh NMOS transistor M11;

The ninth PMOS transistor M9 and the fifth NMOS transistor M5 form a current mirror mode, and the gate of the ninth PMOS transistor M9 is respectively connected to the drain of the ninth PMOS transistor M9 and the fifth NMOS transistor M5 grid;

The tenth NMOS transistor M10 and the sixth NMOS transistor M6 form a current mirror mode, and the gate of the tenth NMOS transistor M10 is respectively connected to the drain of the tenth NMOS transistor M10 and the sixth NMOS transistor M6 grid;

The source of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12 are respectively connected to the drain of the thirteenth NMOS transistor M13;

The gate of the twelfth NMOS transistor M12 is connected to the target common-mode voltage, and the drain thereof is connected to the drain of the ninth PMOS transistor M9;

The source of the tenth NMOS transistor M10 and the source of the thirteenth NMOS transistor M13 are respectively grounded;

The gate of the thirteenth NMOS transistor M13 is connected to a bias voltage.

Among them, the working principle of the pre-charge and discharge capacitor C _P is as follows:

For the convenience of analysis, it is assumed that the current flowing through the load resistor _RL is I _ss , and the existing parasitic capacitance is CL. When the first NMOS transistor and the fourth NMOS transistor switch controlled by the first input terminal signal are turned on, _charges are stored between the positive and negative electrodes of CP, and a voltage difference of I _SS · _RL is established; When the switch of the second NMOS transistor and the third NMOS transistor controlled by the signal at the second input terminal is turned on, the _polarities of the charges of CP and _CL have not changed at this time, and the _charge stored in CP is the same as that of _CL . The charge combination instantly makes the voltage on _RL change from I _SS · _RL to

$<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; SS</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; .</span>$

It can be seen that when the switch is switched, the voltage across R _L can quickly change from I _SS · R _L to

Greatly improve the charge and discharge speed of the load.

The common-mode feedback network works as follows:

If the signal at the first input terminal and the signal at the second input terminal decrease, causing the common-mode voltage at the output terminal of the main driving circuit to be lower than the target common-mode voltage, the gate voltage of the sixth NMOS transistor will decrease, thereby The current flowing through the load will decrease and the common mode voltage at the output of the main body drive circuit will increase. Similarly, if the signal at the first input terminal and the signal at the second input terminal rise, causing the common-mode voltage at the output terminal of the main driving circuit to be greater than the target common-mode voltage, the gate voltage of the sixth NMOS transistor will increase, so that the current flowing through the load will increase, and the common-mode voltage at the output terminal of the main body driving circuit will decrease. It can be seen that the common-mode feedback network stabilizes the common-mode voltage of the output signal of the LVDS driver. In addition, in order to improve the performance of the driver, some filter capacitors are added to the circuit, so that the current is more stable and the signal is more stable when the switch state is changed.

From the feedback system point of view, the common-mode feedback circuit required by the driver has three main tasks: detecting the output common-mode level; comparing the common-mode level to a fixed reference level; and feeding the error back to the bias network. Figure 2 conceptually represents this idea. In Figure 2, the common-mode level of the two output terminals is detected by adding a common-mode feedback network, and a bias current of the amplifier is adjusted accordingly. That is, the common-mode level detection circuit is used to detect the common-mode level of the output terminals Vout1 and Vout2, and after comparing it with a fixed reference level Vref, the error is sent back to the amplifier to change its bias current to achieve stability.

In order to ensure the stability of the output signal, improve the working speed, and increase the drive capability, the above-mentioned embodiment of the present invention introduces common mode feedback CMFB (Common Mode Feedback) to stabilize the common mode level of the output LVDS signal, preventing the signal from appearing in the transmission process. The offset and fluctuation of the mode level, and a pre-charge and discharge capacitor is added to reduce the influence of the load parasitic capacitance on the circuit operating speed. By improving the above two aspects, the stability and working speed of the drive circuit are greatly improved.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (4)

1. a low-voltage differential signal driver, is characterized in that, comprising:

Main body drive circuit, for generation of the high speed differential transmission data of the low-voltage amplitude of oscillation;

Common-mode feedback network, is connected with described main body drive circuit, for the common-mode voltage of the output by described main body drive circuit compared with target common-mode voltage, described common-mode voltage to be adjusted to the level of described target common-mode voltage.

2. low-voltage differential signal driver according to claim 1, is characterized in that, described main body drive circuit comprises:

First nmos pass transistor (M1), the second nmos pass transistor (M2), the 3rd nmos pass transistor (M3), the 4th nmos pass transistor (M4), the 5th nmos pass transistor (M5) and the 6th nmos pass transistor (M6), pre-charge and discharge capacitance (C _p), the first filter capacitor (C1), the second filter capacitor (C2) and load (R _l);

The grid of described first nmos pass transistor (M1) is connected with first input end signal (IN1) respectively with the grid of described 4th nmos pass transistor (M4);

The grid of described second nmos pass transistor (M2) is connected with the second input end signal (IN2) respectively with the grid of described 3rd nmos pass transistor (M3);

The source electrode of described first nmos pass transistor (M1) connects drain electrode and the load (R of described 3rd nmos pass transistor (M3) respectively _l) one end, the source electrode of described second nmos pass transistor (M2) connects drain electrode and the load (R of described 4th nmos pass transistor (M4) respectively _l) the other end;

Described 5th nmos pass transistor (M5) is as current source, its grid connects described common-mode feedback network, drain electrode is connected with power supply, and source electrode connects the drain electrode of described first nmos pass transistor (M1), the drain electrode of described second nmos pass transistor (M2) and described pre-charge and discharge capacitance (C respectively _p) one end;

Described 6th nmos pass transistor (M6) is as current source, its grid connects described common-mode feedback network, source ground, drain electrode connects the source electrode of described 3rd nmos pass transistor (M3), the source electrode of described 4th nmos pass transistor (M4) and described pre-charge and discharge capacitance (C respectively _p) the other end;

One end of described first filter capacitor (C1) connects the grid of described 5th nmos pass transistor (M5), and the other end connects the drain electrode of described first nmos pass transistor;

One end of described second filter capacitor (C2) connects the source electrode of described 3rd nmos pass transistor (M3), and the other end connects the grid of described 6th nmos pass transistor (M6).

3. low-voltage differential signal driver according to claim 2, is characterized in that, described first input end signal (IN1) and described second input end signal (IN2) are complementary fully differential signals.

4. low-voltage differential signal driver according to claim 1, is characterized in that, described common-mode feedback network comprises:

7th PMOS transistor (M7), the 8th PMOS transistor (M8), the 9th PMOS transistor (M9), the tenth nmos pass transistor (M10), the 11 nmos pass transistor (M11), the tenth bi-NMOS transistor (M12), the 13 nmos pass transistor (M13), the first resistance (R1) and the second resistance (R2);

One end of described first resistance (R1) connects the source electrode of described first nmos pass transistor (M1), and the other end connects the grid of described 11 nmos pass transistor (M11);

One end of described second resistance (R2) connects the source electrode of described second nmos pass transistor (M2), and the other end connects the grid of described 11 nmos pass transistor (M11);

The source electrode of described 7th PMOS transistor (M7), the source electrode of described 8th PMOS transistor (M8) are connected with power supply respectively with the source electrode of described 9th PMOS transistor (M9);

Described 7th PMOS transistor (M7) and described 8th PMOS crystal (M8) pipe form current mirror pattern, as the load of described common-mode feedback network;

The grid of described 7th PMOS transistor (M7) connects the grid of described 8th PMOS transistor (M8) and the drain electrode of described 8th PMOS transistor (M8) respectively, and its drain electrode connects the drain electrode of described tenth nmos pass transistor (M10);

The drain electrode of described 8th PMOS transistor (M8) connects the drain electrode of described 11 nmos pass transistor (M11);

Described 9th PMOS transistor (M9) and described 5th nmos pass transistor (M5) form current mirror pattern, and the grid of described 9th PMOS transistor (M9) connects the drain electrode of described 9th PMOS transistor (M9) and the grid of described 5th nmos pass transistor (M5) respectively;

Described tenth nmos pass transistor (M10) and described 6th nmos pass transistor (M6) form current mirror pattern, and the grid of described tenth nmos pass transistor (M10) connects the drain electrode of described tenth nmos pass transistor (M10) and the grid of described 6th nmos pass transistor (M6) respectively;

The source electrode of described 11 nmos pass transistor (M11) is connected with the drain electrode of described 13 nmos pass transistor (M13) respectively with the source electrode of described tenth bi-NMOS transistor (M12);

The grid of described tenth bi-NMOS transistor (M12) connects described target common-mode voltage, and its drain electrode connects the drain electrode of described 9th PMOS transistor (M9);

The source electrode of described tenth nmos pass transistor (M10) and the source electrode of described 13 nmos pass transistor (M13) ground connection respectively;

The grid of described 13 nmos pass transistor (M13) connects a bias voltage.