CN101471634B - Output stage circuit and operational amplifier applying the same - Google Patents
Output stage circuit and operational amplifier applying the same Download PDFInfo
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- CN101471634B CN101471634B CN2007103052154A CN200710305215A CN101471634B CN 101471634 B CN101471634 B CN 101471634B CN 2007103052154 A CN2007103052154 A CN 2007103052154A CN 200710305215 A CN200710305215 A CN 200710305215A CN 101471634 B CN101471634 B CN 101471634B
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Abstract
The invention relates to an output stage circuit and an operational amplifier using thereof. The design of a bias circuit of the output stage circuit simply adopts four transistors to be spliced between a first common voltage and a second common voltage. The design of the bias circuit uses the principle of a differential amplifier, one control voltage is input by a differential input terminal thereof, and the control voltage is generated through the comparison between the voltage difference of the gird voltages of two transistors at the output stage and the fixed difference value. The control voltage can't change with the common voltage of the gird voltage of two transistors at the output stage, therefore, the voltage difference value can be accurately controlled in a preset range and the distortion of the output signal is reduced.
Description
Technical field
The invention relates to the technology that a kind of amplifier is relevant, and particularly relevant for a kind of output-stage circuit and the operational amplifier that uses it.
Background technology
In analog circuit, output-stage circuit is being played the part of the role who output signal is promoted load under the situation that does not cause gain to descend.
Fig. 1 is the circuit diagram of complementary metal oxide semiconductors (CMOS) (CMOS) operational amplifier 10 with AB class output stage 100 disclosed in the list of references [1].Please refer to Fig. 1, this operational amplifier 10 comprises AB class output stage 100, two resistance R 10, R11, two capacitor C 10, C11, amplifying circuit A10 and bias circuit B10, and wherein bias circuit B10 comprises and is positioned at Fig. 1 left side two bias voltage electronic circuit B10-1, B10-2.For the running of the operational amplifier 10 of key diagram 1, node A, B, X and Y have been found in bias circuit B10 acceptance of the bid.Bias voltage electronic circuit B10-1, B10-2 mainly are the voltage that sees through its inner current source IB1, IB2 control A, B node, to reach the bias voltage of control X, Y node, make the Dc bias electric current I out of AB class output stage 100 can become predetermined ratio relation with IB1, IB2.
The bias voltage mode of the AB class output stage 100 of this operational amplifier 10 has the rapid-action advantage in frequency response, but this framework must use folding repeatedly to meet the bias circuit B10 of configuration (folded-cascode) so that AB class output stage 100 is made bias voltage.By top narration, can find out obviously that this circuit has following 2 shortcomings at least:
For the control of output stage quiescent current not precisely (channel length modulation).
Because A, B node all need 2V at least
GSThe bias voltage of grade.So circuit is difficult to operate in the situation of low-voltage.With UMC 0.35um technology is example, V
TP～0.8V, if consider the overdrive voltage of slow corner and 0.1V, then this circuit is difficult to operate in the situation of VDD-VSS＜2V.
Fig. 2 is the circuit diagram of operational amplifier in order to the circuit of improvement Fig. 1 that is disclosed in list of references [1].Please also refer to Fig. 1 and Fig. 2, the bias circuit B20 of Fig. 2 has only repeatedly connect 4 transistors, and the bias circuit B10 of Fig. 1 has repeatedly connect 5 transistors.Obviously, the operational amplifier of Fig. 2 is more suitable for being applied to operate in the situation of low-voltage than the operational amplifier of Fig. 1.Because it is differential right that transistor M201 among the bias circuit B20 and M202 have constituted, therefore,, just can control the voltage difference of X node and Y node as long as the E node is given suitable direct voltage.When small-signal operation, the voltage of X node and Y node can the same-phase change along with signal that amplifying circuit A20 exported.At this moment, the voltage of A node can be subjected to the variation in voltage of X node and Y node, and and then change.Can cause the difference of the voltage of the voltage of X node and Y node and then to change like this.Therefore, the signal Vout that exported of AB class output stage O20 will distortion.
[1]K.J.de?Langen，J.H.Huijsing，“Compact?Low-Voltage?Power-efficientOperational?Amplifier?Cells?for?VLSI”，IEEE?Journal?of?Solid-State?Circuits，vol.SC-33，pp.1482-1496，Oct.1997.
Summary of the invention
In view of this, a purpose of the present invention provides a kind of output-stage circuit, in order to the interference of minimizing output signal when handling, and the distortion of minimizing output signal.
Another object of the present invention is exactly in that a kind of operational amplifier is provided, and can be applicable to low voltage operating.
The present invention proposes a kind of operational amplifier.It comprises an amplifying circuit, a bias circuit, an output-stage circuit and a difference amplifying circuit.Amplifying circuit is in order to export one first output signal.Bias circuit is according to a control voltage and above-mentioned first output signal, export first input voltage and second input voltage, wherein control the Dc bias of voltage control first input voltage and second input voltage, first output signal is controlled the voltage difference of first input voltage and second input voltage.Output-stage circuit according to first input voltage and second input voltage to export an output signal.The difference amplifying circuit is coupled to output-stage circuit, in order to the difference and of first input voltage that output-stage circuit received and second input voltage fixedly difference make comparisons, producing control voltage, with the difference of the Dc bias part of controlling first input voltage and second input voltage in a preset range.
The design of the bias circuit of output-stage circuit of the present invention need only be adopted and repeatedly connect 4 transistors between first common voltage and second common voltage.The principle of differential amplifier is used in the design of above-mentioned bias circuit, utilizes one of them differential input terminal input one control voltage, this control voltage be utilize output stage two transistorized grid voltages voltage difference and fixedly difference make comparisons produce.This control voltage can be along with the and then change of common-mode voltage (Common ModeVoltage) of two transistorized grid voltages of output stage, therefore not only above-mentioned voltage difference can be controlled in the preset range accurately, and can reach the distortion effect that lowers output signal.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the circuit diagram of complementary metal oxide semiconductors (CMOS) (CMOS) operational amplifier 10 with AB class output stage 100 of disclosure in the above-mentioned list of references [1].
Fig. 2 is the circuit diagram of operational amplifier in order to the circuit of improvement Fig. 1 that is disclosed in above-mentioned list of references [1].
Fig. 3 is the circuit block diagram of the operational amplifier 31 that illustrates according to the embodiment of the invention.
Fig. 4 be the above-mentioned operational amplifier 31 that illustrates according to the embodiment of the invention than detail circuits figure.
Fig. 5 be the above-mentioned difference amplifying circuit DA30 that illustrates according to the embodiment of the invention than detail circuits figure.
Fig. 6 be the above-mentioned operational amplifier 31 that illustrates according to the embodiment of the invention than detail circuits figure.
Fig. 7 be the above-mentioned difference amplifying circuit DA30 that illustrates according to the embodiment of the invention than detail circuits figure.
The reference numeral explanation
A10, A20,301: amplifying circuit
B10, B20, BA302: bias circuit
B10-1, B10-2: bias voltage electronic circuit
C40, C41, C10, C11: electric capacity
DA30: difference amplifying circuit
M01～M25: transistor
R40, R41, R10, R11: resistance
I01, I02, IB1, IB2, I03, I04: current source
10,31: operational amplifier
100:AB class output stage
302: output-stage circuit
Embodiment
Fig. 3 is the circuit block diagram of the operational amplifier 31 that illustrates according to the embodiment of the invention.Please refer to Fig. 3, this operational amplifier 31 comprises amplifying circuit 301 and output-stage circuit 302, wherein this output-stage circuit 302 comprises a M01, transistor seconds M02 and bias circuit BA302, and wherein bias circuit comprises the 3rd transistor M03, the 4th transistor M04, the 5th transistor M05, the 6th transistor M06, the first current source I01, the second current source I02 and difference amplifying circuit DA30.It couples as shown above.For convenience of description, first and second meets voltage VDD and VSS altogether also to have marked several node NDA, NDB, NDO on Fig. 3.The above-mentioned voltage VDD that connects altogether generally is a supply voltage, and meeting voltage VSS altogether generally is earthed voltage, yet, meet voltage VDD altogether and can change according to different application with VSS, on for example some was used, VSS can equal-VDD.Therefore, should be with VDD and VSS voltage as restrictive condition of the present invention.
The one M01 of output-stage circuit 302 and transistor seconds M02 are used for driving load.In the present embodiment, in order will to keep in the output-stage circuit 302, the aligned phase signal that signal that a M01 and transistor seconds M02 are exported at node NDO and amplifying circuit 301 are exported, first and second transistor M01 and M02 can meet following condition:
Transistor M01 and M02 operate in the saturation region.
Dc bias electric current between the source electrode of transistor M01 and M02 and drain electrode can be predicted.
Yet the grid bias of the grid bias of transistor M01 and transistor M02 is also inequality.Therefore, the Dc bias of the Dc bias of node NDA and node NDB must have a difference.In addition, when the common-mode voltage (small-signal) on node NDA and the node NDB changed, the change amount of above-mentioned difference was the smaller the better.
In this embodiment, the 3rd transistor M03 and the 4th transistor M04 are configured to the structure of similar difference amplifier.The grid of the 5th transistor M05 and the 6th transistor M06 couples fixed-bias transistor circuit Vbn2, so both are equivalent to current source.But the 4th transistorized grid couples a fixed-bias transistor circuit Vbp2, therefore as long as the grid voltage of control the 3rd transistor M03, just can Control Node NDA and the Dc bias of node NDB, and control the Dc bias difference of above-mentioned two node NDA and NDB.In addition, the first output signal S1 that amplifying circuit 301 is exported transistorizedly couples input from the second current source I02 and the 5th, the 6th, therefore, and can the same-phase change in the small signal of node NDA and node NDB.
In order to reduce the distortion of output signal Vout, the voltage difference of node NDA and node NDB will be fixed.So in this embodiment, difference amplifying circuit DA30 couples node NDA and node NDB, and the voltage of receiving node NDA and NDB, and with the difference and of above-mentioned two nodes fixedly difference make comparisons, to control the grid voltage of the 3rd transistor M03.Because the node voltage of NDA and NDB is the first output signal S1 homophase change of being exported according to amplifying circuit 301, in theory, the node voltage of NDA and NDB is can not change along with the first output signal S1.Therefore, difference amplifying circuit DA30 is the difference and the said fixing difference of the node voltage of comparison NDA and NDB, when the difference of the node voltage of NDA and NDB drops to when being lower than the said fixing difference, just promote the control voltage Vc of the grid that inputs to the 3rd transistor M03, the difference of the node voltage of NDA and NDB is amplified.When the difference of node voltage rises to when being higher than the said fixing difference, the control voltage Vc that just reduces the grid that inputs to the 3rd transistor M03 reduces the difference of the node voltage of NDA and NDB.
Please refer again to Fig. 3, in the above-described embodiments, the first current source I01 and the second current source I02 can use simple current mirroring circuit to implement respectively, therefore, connecing altogether between voltage VDD and the VSS, it is 4 that the transistorized maximum of this operational amplifier 31 repeatedly connects number.Therefore, this circuit is fit to be applied in low-voltage.In addition, control voltage Vc is controlled by the difference of the node voltage of NDA and NDB only, so no matter how the common-mode voltage of the node voltage of NDA and NDB changes, also can not have influence on and control voltage Vc.Therefore, the distortion of the output signal Vout that exports of this circuit compared with the circuit of Fig. 2 of prior art to come little.
Though operational amplifier 31 of the present invention and output-stage circuit 302 have been described out a possible kenel in the foregoing description, but those skilled in the art should know, the design of bias circuit BA302 and amplifying circuit 301 all is not quite similar, and therefore application of the present invention is not restricted to this kind kenel.In other words, so long as the principle of differential amplifier is used in the design of bias circuit, utilize one of them differential input terminal input one control voltage, this control voltage be utilize output stage two transistorized grid voltages voltage difference and fixedly difference make comparisons produce, even circuit or signal processing mode have a little difference, technology with operational amplifier and output-stage circuit of those differences has been to have met spiritual place of the present invention just.
Next, lift the enforcement circuit of an operational amplifier 31 again so that those skilled in the art can understand spirit of the present invention.
Fig. 4 be the above-mentioned operational amplifier 31 that illustrates according to the embodiment of the invention than detail circuits figure.Please refer to Fig. 4, in this embodiment, the second current source I02 is the 7th transistor M07 enforcement that receives fixed-bias transistor circuit Vbn1 with grid.The first current source I01 among Fig. 3 implements with the current mirror that the tenth transistor M10, the 11 transistor M11 and the tenth two-transistor M12 are constituted, and wherein the grid of the tenth two-transistor M12 and the 4th transistor M04 receives fixed-bias transistor circuit Vbp2 simultaneously.In addition, in bias circuit BA302, the 8th transistor M08 and the 9th transistor M09 have also been comprised.The grid of the 8th transistor M08 receives fixed-bias transistor circuit Vbn1.The grid of the 9th transistor M09 receives fixed-bias transistor circuit Vbn2.Amplifying circuit 301 is to implement with the 13 transistor M13, the 14 transistor M14 and the 15 transistor M15, wherein, it is differential right that the 14 transistor M14 and the 15 transistor M15 have constituted, the grid of the 13 transistor M13 receives fixed-bias transistor circuit Vbp1, and supplies the 14 transistor M14 and the 15 transistor DC bias voltage by the 13 transistor M13.In addition,, coupled resistance R 40, R41 and capacitor C 40, C41 respectively between the grid of the first transistor M01 and the drain electrode and between the grid of transistor seconds and the drain electrode, in order to the working frequency compensation, the stability of increase operational amplifier 31.
Can see that by Fig. 4 transistor M03～M15 has constituted folding and repeatedly connect configuration (Folded-Cascode Configuration).The grid of the 14 M14 and the 15 transistor M15 receives positive input signal Vip and negative input signal Vin respectively.Positive output signal S2 and negative output signal S1 are exported in the drain electrode of the 14 M14 and the 15 transistor M15 respectively.The small-signal of output signal S1 and S2 then is repeatedly to connect configuration through this folding to be transferred to node NDA and NDB.
Fig. 5 be the above-mentioned difference amplifying circuit DA30 that illustrates according to the embodiment of the invention than detail circuits figure.Please refer to Fig. 5, this circuit comprises the 16 M16, the 17 M17, the 18 M18, the 19 M19, the 20 M20, the 21 M21, the 22 M22, the 23 M23, the 24 M24, the 25 transistor M25.It couples as Fig. 5 and illustrates.In this embodiment, it is one differential right that transistor M18 and M19 constitute, and it is one differential right in addition that transistor M20 and M21 constitute.It is above-mentioned two differential to bias voltage that transistor M16, M17, M22, M23 are used to provide.The grid of the 18 transistor M18 couples node NDB.The grid of the 19 transistor M19 couples the grid of the 24 transistor M24.The grid of the 21 transistor M21 couples node NDA.The grid of the 20 transistor M20 couples the grid of the 25 transistor M25.
Because the grid of the 24 M24 and the 25 transistor M25 couples its drain electrode, just so-called diode connects.Therefore, so long as the size that suitable Control current source I03 and I04 flow through the electric current of the 24 M24 and the 25 transistor M25, just can control grid and the drain voltage of the 24 M24 and the 25 transistor M25.At this, the drain voltage of hypothesis the 24 transistor M24 is first error voltage earlier, and is expressed as A, and the drain voltage of the 25 transistor M25 is second error voltage, and is expressed as B, and the voltmeter of NDA node is shown Y, and the voltmeter of NDB node is shown X.Control voltage Vc just can be expressed as follows:
Vc＝G[(X+A)-(Y+B)]＝G[(X-Y)-(A-B)]
Wherein, G represents Amplifier Gain.Therefore, as long as suitable designing gain G and error voltage A and B just can control the size of voltage Vc.And the node voltage X of node NDA and NDB, the voltage difference of Y are just controlled.In addition, because the design of difference amplifying circuit DA30, the size of control voltage the Vc only difference with node voltage X, the Y of node NDA and NDB are relevant, have nothing to do with the common-mode voltage of both X, Y, therefore, output voltage V out is not easy distortion compared with the circuit of Fig. 2 of prior art.
Though above lifted a specific embodiment, the embodiment that it will be appreciated by those skilled in the art that above-mentioned Fig. 4 is a kind of application of spirit according to the invention equally if be revised as Fig. 6.Same, the embodiment of above-mentioned Fig. 5 is a kind of application of spirit according to the invention if be revised as Fig. 7 equally.So the present invention is not exceeded with the enforcement aspect of above-mentioned Fig. 4～Fig. 7.
In sum, the design of the bias circuit of output-stage circuit of the present invention need only be adopted between the first common voltage VDD and the second common voltage VSS and repeatedly connect 4 transistors.The principle of differential amplifier is used in the design of above-mentioned bias circuit, utilize one of them differential input terminal input one control voltage Vc, this control voltage Vc be utilize two transistor M01 of output stage and M02 grid voltage voltage difference and fixedly difference make comparisons produce.This control voltage Vc can be along with the and then change of common-mode voltage (Common Mode Voltage) of the grid voltage of two transistor M01 of output stage and M02, therefore not only above-mentioned voltage difference can be controlled in the preset range accurately, and can reach the distortion effect that lowers output signal.
The specific embodiment that is proposed in the detailed description of the foregoing description is only in order to convenient explanation technology contents of the present invention, but not with narrow sense of the present invention be limited to the foregoing description, the many variations of being done under the prerequisite that does not exceed spirit of the present invention and claim scope is implemented, and all belongs to scope of the present invention.Therefore protection scope of the present invention is as the criterion with claim of the present invention.
Claims (13)
1. operational amplifier comprises:
One amplifying circuit is exported one first output signal;
One bias circuit, according to control voltage and this first output signal, export one first input voltage and one second input voltage, wherein should control the Dc bias part of this first input voltage of voltage control and this second input voltage, this first output signal is controlled the voltage difference of this first input voltage and this second input voltage;
One output-stage circuit, according to this first input voltage and this second input voltage to export an output signal; And
One difference amplifying circuit, be coupled to this output-stage circuit, in order to the difference and of this first input voltage of this output-stage circuit and this second input voltage fixedly difference make comparisons, producing this control voltage, with the difference of the Dc bias part of controlling this first input voltage and this second input voltage in a preset range.
2. operational amplifier as claimed in claim 1, this output-stage circuit wherein comprises:
One first node receives this first input voltage;
One Section Point receives this second input voltage;
One the first transistor, its first source-drain electrode couples one first and connects voltage altogether, and its grid couples this first node; And
One transistor seconds, its first source-drain electrode couples second source-drain electrode of this first transistor, and its second source-drain electrode couples one second and connects voltage altogether, and its grid couples this Section Point.
3. operational amplifier as claimed in claim 2 also comprises:
One first frequency compensating circuit, its first end couples second source-drain electrode of this first transistor, and its second end couples this first node, compensates in order to working frequency; And
One second frequency compensating circuit, its first end couples first source-drain electrode of this transistor seconds, and its second end couples this Section Point, compensates in order to working frequency.
4. operational amplifier as claimed in claim 3, wherein this first frequency compensating circuit comprises:
One resistance, its first end couples this first node;
One electric capacity, its first end couples second end of this resistance, and its second end couples second source-drain electrode of this first transistor.
5. operational amplifier as claimed in claim 3, wherein this second frequency compensating circuit comprises:
One resistance, its first end couples this Section Point;
One electric capacity, its first end couples second end of this resistance, and its second end couples first source-drain electrode of this transistor seconds.
6. operational amplifier as claimed in claim 2, wherein this first to connect voltage altogether be a supply voltage, second to connect voltage altogether be an earthed voltage for this.
7. operational amplifier as claimed in claim 1, bias circuit wherein includes:
One first current source, its first end couples first and connects voltage altogether;
One the 3rd transistor, its first source-drain electrode couples second end of this first current source, and its second source-drain electrode is exported this first input voltage, and its grid receives this control voltage;
One the 4th transistor, its first source-drain electrode couples second end of this first current source, and its second source-drain electrode is exported this second input voltage, and its grid receives one first fixed-bias transistor circuit;
One the 5th transistor, its first source-drain electrode couple the 3rd transistorized second source-drain electrode, and its grid receives one second fixed-bias transistor circuit;
One the 6th transistor, its first source-drain electrode couple the 4th transistorized second source-drain electrode, and its grid receives this second fixed-bias transistor circuit; And
One second current source, its first end couple the 5th with the 6th transistorized second source-drain electrode, and receive this first output signal that this amplifying circuit is exported, its second end couples second and connects voltage altogether.
8. operational amplifier as claimed in claim 7, wherein this second current source comprises:
One the 7th transistor, its grid receive one the 3rd fixed-bias transistor circuit, and its first source-drain electrode is first end of this second current source, and its second source-drain electrode is second end of this second current source.
9. operational amplifier as claimed in claim 8 also comprises:
One the 8th transistor, its first source-drain electrode receive one second output signal that this amplifying circuit is exported, and its second source-drain electrode couples this and second connects voltage altogether, and its grid couples the 7th transistorized grid; And
One the 9th transistor, its grid couple the 5th with the 6th transistorized grid, its second source-drain electrode couples the 8th transistorized first source-drain electrode.
10. operational amplifier as claimed in claim 7, wherein this first current source comprises:
The tenth transistor, its first source-drain electrode are first end of this first current source, and its second source-drain electrode is second end of this first current source;
The 11 transistor, its grid couple the tenth transistorized grid, and its first source-drain electrode couples this and first connects voltage altogether; And
The tenth two-transistor, its grid couple the 4th transistorized grid, and its first source-drain electrode couples the 11 transistorized second source-drain electrode, and its second source-drain electrode couples the 11 transistorized grid.
11. operational amplifier as claimed in claim 1, wherein this amplifying circuit comprises:
The 13 transistor, its first source-drain electrode couples first and connects voltage altogether, and its grid receives one the 4th fixed-bias transistor circuit;
The 14 transistor, its first source-drain electrode couples the 13 transistorized second source-drain electrode, and its grid receives one first input signal, and its second source-drain electrode is exported this first output signal; And
The 15 transistor, its first source-drain electrode couples the 13 transistorized second source-drain electrode, and its grid receives one second input signal, and its second source-drain electrode is exported one second output signal.
12. operational amplifier as claimed in claim 1, wherein this difference amplifying circuit comprises:
The 16 transistor, its first source-drain electrode couples first and connects voltage altogether, and its grid couples its second source-drain electrode;
The 17 transistor, its first source-drain electrode couple this and first connect voltage altogether, and its grid couples the 16 transistorized grid;
The 18 transistor, its first source-drain electrode couples the 16 transistorized second source-drain electrode, and its grid couples Section Point;
The 19 transistor, its first source-drain electrode couple the 17 transistorized second source-drain electrode and export this control voltage, and its grid receives one first error voltage;
One the 20 transistor, its first source-drain electrode couples the 16 transistorized second source-drain electrode, and its grid receives one second error voltage;
One the 21 transistor, its first source-drain electrode couple the 17 transistorized second source-drain electrode and export this control voltage, and its grid couples first node;
One the 20 two-transistor, its grid receives first fixed-bias transistor circuit, its first source-drain electrode couple the 18 with the 19 transistorized second source-drain electrode, its second source-drain electrode couples second and connects voltage altogether; And
One the 23 transistor, its grid receive this first fixed-bias transistor circuit, its first source-drain electrode couple the 20 with the 21 transistorized second source-drain electrode, its second source-drain electrode couples this and second connects voltage altogether.
13. operational amplifier as claimed in claim 12, wherein this difference amplifying circuit also comprises:
One the 3rd current source, its first end couple this and first connect voltage altogether;
One the 24 transistor, its first source-drain electrode couples second end of its grid and the 3rd current source, and produces this first error voltage, and its second source-drain electrode couples this and second connects voltage altogether;
One the 25 transistor, its first source-drain electrode couple this and first connect voltage altogether, and its second source-drain electrode couples its grid and produces this second error voltage; And
One the 4th current source, its first end couples the 25 transistorized second source-drain electrode, and its second end couples this and second connects voltage altogether.
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| CN2007103052154A CN101471634B (en) | 2007-12-29 | 2007-12-29 | Output stage circuit and operational amplifier applying the same |
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| CN2007103052154A CN101471634B (en) | 2007-12-29 | 2007-12-29 | Output stage circuit and operational amplifier applying the same |
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| CN101471634B true CN101471634B (en) | 2011-05-11 |
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| TWI465035B (en) * | 2011-11-23 | 2014-12-11 | Sitronix Technology Corp | Power amplifier with low power consumption |
| CN104426490A (en) * | 2013-08-30 | 2015-03-18 | 核芯科技股份有限公司 | Amplifier circuit and signal amplifying method |
| CN105356883B (en) * | 2015-12-04 | 2019-02-12 | 上海兆芯集成电路有限公司 | Conduct current Digital to Analog Converter and output voltage swing control circuit |
| TWI635700B (en) * | 2015-12-10 | 2018-09-11 | 矽創電子股份有限公司 | Operational amplifier |
| CN111327278B (en) * | 2020-04-10 | 2023-10-13 | 上海兆芯集成电路股份有限公司 | Output stage circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0123275A2 (en) * | 1983-04-21 | 1984-10-31 | Kabushiki Kaisha Toshiba | Operational amplifier circuit |
| CN1165427A (en) * | 1996-02-23 | 1997-11-19 | 冲电气工业株式会社 | Operational amplification circuit |
| JP2000183668A (en) * | 1998-12-16 | 2000-06-30 | Nec Corp | Operation amplifier circuit |
| US20020000883A1 (en) * | 1999-05-24 | 2002-01-03 | David F. Cox | Apparatus for and method of controlling amplifier output offset using body biasing in mos transistors |
-
2007
- 2007-12-29 CN CN2007103052154A patent/CN101471634B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0123275A2 (en) * | 1983-04-21 | 1984-10-31 | Kabushiki Kaisha Toshiba | Operational amplifier circuit |
| CN1165427A (en) * | 1996-02-23 | 1997-11-19 | 冲电气工业株式会社 | Operational amplification circuit |
| JP2000183668A (en) * | 1998-12-16 | 2000-06-30 | Nec Corp | Operation amplifier circuit |
| US20020000883A1 (en) * | 1999-05-24 | 2002-01-03 | David F. Cox | Apparatus for and method of controlling amplifier output offset using body biasing in mos transistors |
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