CN210183300U - Universal comparator integrated circuit - Google Patents
Universal comparator integrated circuit Download PDFInfo
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- CN210183300U CN210183300U CN201921307468.XU CN201921307468U CN210183300U CN 210183300 U CN210183300 U CN 210183300U CN 201921307468 U CN201921307468 U CN 201921307468U CN 210183300 U CN210183300 U CN 210183300U
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Abstract
The utility model discloses a general comparator integrated circuit, which comprises a rail-to-rail preamplification circuit, an intermediate stage amplification circuit, a latch comparison circuit and an output circuit; the rail-to-rail preamplification circuit is formed by connecting two P-type and N-type differential pairs in parallel to form differential inputs vinp and vinn of the universal comparator integrated circuit; the intermediate-stage amplification circuit is connected with the rail-to-rail preamplification circuit and consists of a differential amplification circuit of two stages of resistance loads; the latch comparison circuit is connected with the intermediate-stage amplifying circuit and is a parallel latch amplifying circuit; the output circuit is connected with the latch comparison circuit and consists of a self-bias differential amplification circuit and an inverter. Support rail-to-rail input and output, support hysteretic comparison, support high frequency input signals with higher speed and sensitivity, synchronous output with forward and reverse directions, and lower power consumption.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, specifically speaking relates to a general comparator integrated circuit.
Background
The application of voltage comparator circuits in many analog integrated circuit projects is quite extensive, and especially in common analog-to-digital conversion circuits, the comparator plays a crucial role.
Comparators are classified in various ways, wherein the comparators can be classified into static comparators (i.e. conventional comparators) and dynamic comparators according to the difference between the time duration of the comparator operation and the clock sampling time. The former is mostly suitable for the situation that uninterrupted comparison is needed in continuous time and is characterized in that offset is small but power consumption is large; the latter is mostly used in analog-to-digital conversion circuits, and is characterized by fast speed, low power consumption, but large offset. The frame of the static comparator circuit is generally composed of various amplifiers and positive feedback comparison structure circuits, even only composed of an amplifying circuit. The amplifying circuit is generally used as an input to provide a difference amplifying service of an input signal for the comparator, and provides a better comparison signal for the following comparison, and the positive feedback comparison structure is a core of the comparison, so that the comparison is performed quickly, a difference result is output to a subsequent structure quickly, and finally, a voltage comparison function is realized.
The prior static comparator chip circuit has the following problems: 1. most of the circuits only support rail-to-rail output, and lack of support for rail-to-rail input function, so that input voltage is greatly limited, and the circuit versions of most of comparators are older and cannot meet the current requirements; 2. for the existing common comparator, the sensitivity of some circuits is too small, the speed is slightly low, and the hysteresis function is not supported; 3. the power consumption of part of the comparison circuit is overlarge, and only the forward output is realized, and a synchronous reverse output interface is not realized.
Disclosure of Invention
An object of the utility model is to provide a support rail to rail input/output, support hysteresis relatively, can support high frequency input signal and have high speed and sensitivity, have positive and negative two to synchronous output, the general comparator integrated circuit of lower consumption.
The utility model discloses a following technical scheme realizes:
a universal comparator integrated circuit is proposed, comprising: the rail-to-rail preamplification circuit is formed by connecting two P-type and N-type differential pairs in parallel to form differential inputs vinp and vinn of the universal comparator integrated circuit; the intermediate-stage amplifying circuit is connected with the rail-to-rail pre-amplifying circuit and consists of a differential amplifying circuit of two stages of resistive loads; the latch comparison circuit is connected with the intermediate-stage amplifying circuit and is a parallel latch amplifying circuit; and the output circuit is connected with the latch comparison circuit and consists of a self-bias differential amplification circuit and an inverter.
Further, the rail-to-rail preamplification circuit further includes: the output of the N-type differential pair load circuit is connected with the intermediate-stage amplifying circuit; a current mirror circuit that loads the output of the P-type differential pair onto the N-type differential pair load circuit; an enable switch for enabling turn-on and turn-off of the rail-to-rail pre-stage circuit; a bias circuit to provide a bias current and a bias voltage for the rail-to-rail preamplifier circuit.
Further, the intermediate stage amplifying circuit further includes: and the two stages of first mirror current sources consisting of NMOS tubes are connected with the differential amplification circuit of the resistance load.
Further, the latch comparison circuit includes: an N-type differential input pair circuit; a second mirror current source composed of NOMS tubes and loaded on the N-type differential input pair circuit; and the parallel latch circuit is connected with the output of the N-type differential input pair circuit.
Further, the inverter comprises a first inverter, a second inverter and a third inverter which are connected in series; wherein the output of the second inverter is a forward output Vout, and the output of the third inverter is a reverse output Vout-.
Further, the integrated circuit further comprises: a hysteresis circuit including a first resistor and a second resistor; the first resistor is connected in series with an input circuit of the differential input vinp, and the second resistor is connected in series between an output end of the output circuit and the differential input vinp.
Compared with the prior art, the utility model discloses an advantage is with positive effect: the utility model provides a general comparator integrated circuit supports rail to rail input/output, supports hysteresis comparison, can support high frequency input signal and have higher speed and sensitivity, have positive and negative two to synchronous output and have lower consumption.
Other features and advantages of the present invention will become more apparent from the following detailed description of embodiments of the invention, which is to be read in connection with the accompanying drawings.
Drawings
Fig. 1 is a circuit architecture diagram of a general comparator integrated circuit according to the present invention;
fig. 2 is a circuit diagram of an embodiment of a rail-to-rail front-end circuit according to the present invention;
fig. 3 is a circuit diagram of an embodiment of an intermediate stage amplifying circuit provided by the present invention;
fig. 4 is a circuit diagram of an embodiment of a latch comparison circuit according to the present invention;
fig. 5 is a circuit diagram of an embodiment of an output circuit according to the present invention;
fig. 6 is a block diagram of a general comparator integrated circuit according to the present invention;
fig. 7 is a simulation diagram of a general comparator integrated circuit according to the present invention;
fig. 8 is a simulation diagram of a general comparator integrated circuit according to the present invention;
fig. 9 is a simulation diagram of a general comparator integrated circuit according to the present invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
The utility model aims at providing a support rail to rail input/output, support hysteresis relatively, can support high frequency input signal and have higher speed and sensitivity, have positive and negative two to synchronous output, the voltage comparator circuit of lower consumption.
As shown in fig. 1, the general comparator integrated circuit provided by the present invention includes a rail-to-rail preamplifier circuit 11, an intermediate stage amplifier circuit, a latch comparator circuit 13, and an output circuit 14; the rail-to-rail preamplification circuit 11 is formed by connecting two differential pairs of a P type and an N type in parallel to form differential inputs vinp and vinn of a general comparator integrated circuit; the intermediate-stage amplifying circuit 12 is connected with the rail-to-rail preamplification circuit 11 and is composed of a differential amplifying circuit of two stages of resistive loads; the latch comparison circuit 13 is connected with the intermediate-stage amplifying circuit 12 and is a parallel latch amplifying circuit; the output circuit 14 is connected to the latch comparator circuit 13, and is composed of a self-biased differential amplifier circuit and an inverter.
Specifically, the rail-to-rail preamplification circuit 11 is formed by connecting two groups of P-type and N-type differential pairs in parallel; the two have no need of large amplification gain, and only need of ensuring P-type differential operation at low-voltage input and N-type differential pair operation at high-voltage input, and can retain relatively good bandwidth. Therefore, the comparator can work normally no matter high voltage or low voltage is input, and a good amplification effect can still be kept for high-frequency signals because the bandwidth is large.
As shown in fig. 2, PMOS transistors M2 and M3 form a P-type differential input pair, and are connected in parallel to an N-type differential input pair formed by NMOS transistors M0 and M1, gates of M3 and M1 are connected to form an input vinp, gates of M2 and M0 are connected to form an input vinn, and a current is applied to N-type differential pair load circuits M10 and M13 through a current mirror circuit formed by NMOS transistors M9 and M6 and M7 and M8, and then is output to a subsequent intermediate-stage amplification module through drains of PMOS transistors M10 and M13. The NMOS transistor M71 constitutes an enable switch, which functions as an on/off enable. The rest MOS transistors M24, M25, M37, M38, M39, M40, M36, M22, M5 and M23 form a bias circuit of the circuit, and provide static working current for the circuit; in the figure, vdd is 3.3V, and gnd is 0V.
The intermediate-stage amplifying circuit 12 is formed by a differential amplifying circuit with two stages of resistive loads; the two-stage amplifier does not need large amplification gain, and only needs to ensure relatively good bandwidth and proper output voltage range, so that the amplification effect on high-frequency signals can be ensured.
As shown in fig. 3, the first-stage amplifier is an N-type differential input pair formed by NMOS transistors M59 and M62, and the gate of M59 is connected to the drain of M10 in fig. 2, and the gate of M62 is connected to the drain of M13 in fig. 2; r0 and R1 are respectively used as loads of M59 and M62; the gates of M60 and M61 used as the first mirror current source are respectively connected with the gates of M5 and M23 in FIG. 2; in addition, the second-stage amplifier is composed of an N-type differential input pair formed by NMOS transistors M63 and M66, the grid electrode of M63 is connected with the drain electrode of M59, and the grid electrode of M66 is connected with the drain electrode of M62; r2 and R3 are respectively used as loads of M63 and M66; the gates of M65 and M64 used as the first mirror current source are respectively connected with the gates of M60 and M61; in the figure, one end of R0 which is not connected with the MOS tube is connected with vdd, and the source end of M61 is connected with gnd.
The latch comparator circuit 13 is a parallel latch amplifier circuit, and can quickly amplify the received differential signal output from the preceding stage and quickly pull up the differential signal to the vdd power supply voltage or pull down the differential signal to the gnd ground voltage.
As shown in fig. 4, the MOS transistors M67 and M68 form an N-type differential input pair circuit, the gate of M67 is connected to the drain of M63 in fig. 3, and the gate of M68 is connected to the drain of M62 in fig. 3. The gates of M65 and M64 used as the second mirror current source are connected to the gates of M65 and M64 in fig. 3, respectively. M14, M15, M12 and M11 respectively form a parallel latch circuit, drain terminals of M14 and M15 are respectively connected with drain terminals of M12 and M11, and R8 is bridged between the two points and is connected with drain terminals of M67 and M68; the source terminal of M14 is connected to vdd, and the source terminal of M12 is connected to gnd.
The output circuit 14 is an output circuit with rail-to-rail output and capability of providing large current output, has no large quiescent current, has a certain tail current self-adapting capability, and is provided with an inverter at the output, and can output forward and reverse output result signals at the same time.
As shown in fig. 5, MOS transistors M28, M29, M30, M31, M32, and M33 constitute an output portion having the capability of drawing and supplying a large current, which is called a self-biased differential amplifier circuit, and M28 and M29 limit the maximum current that can flow. The other MOS tubes M34, M35, M41, M42, M74 and M77 form three inverters, the source of the MOS tube M28 is connected with vdd power voltage, the source of the MOS tube M28 is connected with gnd ground voltage, the gates of the MOS tubes M30 and M31 are respectively connected with the drains of the MOS tubes M11 and M15 in the circuit of FIG. 4, the gates of the MOS tubes M32 and M33 are respectively connected with the drains of the MOS tubes M14 and M12 in the circuit of FIG. 4, and the drains of the MOS tubes M42 and M77 are two output ports vout and vout of the module.
As shown in fig. 6, for the interface definition and module characterization symbol of the whole circuit, there are six input pins, which are respectively a 3.3V power supply voltage interface vdd, a 3.3V enable and enable signal interface en, a power ground interface gnd, a 5uA reference current input interface iin, and differential input interfaces vinp and vinn, and two output pins, which are respectively an output interface vout that is not inverted by an inverter and an output interface vout that is inverted by the inverter-, and the first resistor Ra and the second resistor Rb provide a hysteretic function.
The following embodiment illustrates the design simulation and the result of the general comparator integrated circuit provided by the present invention.
Firstly, 3.3V voltage is added to the whole circuit, 1V alternating voltage signals are added on the basis of 1.2V direct voltage through differential input, and amplification gain of the signals is checked through running AC simulation so as to observe the bandwidth of the circuit, namely the reaction condition of the bandwidth to higher-frequency signals.
As shown in fig. 7, the simulation results show the practical results of the ac voltage gain output by the circuit in the range of 1HZ to 1GHZ, and it can be seen from the simulation results that the signal with the frequency of 50MHZ or more can be supported.
Then, the voltage of 3.3V is added to the whole circuit, the differential input is added with an alternating current voltage signal with the amplitude of 1mV and the frequency of 1MHZ on the basis of the direct current voltage of 1.2V, the transient simulation under the signal is carried out, and the signal is converted into a triangular wave attempt to observe whether the output signal under the signal voltage meets the requirement or not.
As shown in fig. 8 and 9, the simulation result shows that the input signal of the 1-bit input terminal vinp of the curve, the input signal of the 2-bit input terminal vinn of the curve, the output signal of the 3-bit forward output terminal vout of the curve, and the output signal of the reverse output terminal vout-of the curve 4.
Finally, the 1.2V direct-current voltage is changed into any value, the comparators work normally, and the rail-to-rail input and output function is proved to be realized.
It should be noted that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and the changes, modifications, additions or substitutions made by those skilled in the art within the spirit of the present invention should also belong to the protection scope of the present invention.
Claims (6)
1. A universal comparator integrated circuit, comprising:
the rail-to-rail preamplification circuit is formed by connecting two P-type and N-type differential pairs in parallel to form differential inputs vinp and vinn of the universal comparator integrated circuit;
the intermediate-stage amplifying circuit is connected with the rail-to-rail pre-amplifying circuit and consists of a differential amplifying circuit of two stages of resistive loads;
the latch comparison circuit is connected with the intermediate-stage amplifying circuit and is a parallel latch amplifying circuit;
and the output circuit is connected with the latch comparison circuit and consists of a self-bias differential amplification circuit and an inverter.
2. The universal comparator integrated circuit as claimed in claim 1, wherein the rail-to-rail preamplification circuit further comprises:
the output of the N-type differential pair load circuit is connected with the intermediate-stage amplifying circuit;
a current mirror circuit that loads the output of the P-type differential pair onto the N-type differential pair load circuit;
an enable switch for enabling turn-on and turn-off of the rail-to-rail pre-stage circuit;
a bias circuit to provide a bias current and a bias voltage for the rail-to-rail preamplifier circuit.
3. The universal comparator integrated circuit as claimed in claim 1, wherein said intermediate stage amplification circuit further comprises:
and the two stages of first mirror current sources consisting of NMOS tubes are connected with the differential amplification circuit of the resistance load.
4. The universal comparator integrated circuit as claimed in claim 1, wherein said latching comparison circuit comprises:
an N-type differential input pair circuit;
a second mirror current source composed of NOMS tubes and loaded on the N-type differential input pair circuit;
and the parallel latch circuit is connected with the output of the N-type differential input pair circuit.
5. The universal comparator integrated circuit as claimed in claim 1, wherein said inverter comprises a first inverter, a second inverter and a third inverter connected in series;
wherein the output of the second inverter is a forward output Vout, and the output of the third inverter is a reverse output Vout-.
6. The universal comparator integrated circuit as claimed in claim 1, wherein said integrated circuit further comprises:
a hysteresis circuit including a first resistor and a second resistor;
the first resistor is connected in series with an input circuit of the differential input vinp, and the second resistor is connected in series between an output end of the output circuit and the differential input vinp.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921307468.XU CN210183300U (en) | 2019-08-13 | 2019-08-13 | Universal comparator integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921307468.XU CN210183300U (en) | 2019-08-13 | 2019-08-13 | Universal comparator integrated circuit |
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| CN210183300U true CN210183300U (en) | 2020-03-24 |
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| CN201921307468.XU Active CN210183300U (en) | 2019-08-13 | 2019-08-13 | Universal comparator integrated circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910447A (en) * | 2021-01-18 | 2021-06-04 | 电子科技大学 | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude |
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2019
- 2019-08-13 CN CN201921307468.XU patent/CN210183300U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910447A (en) * | 2021-01-18 | 2021-06-04 | 电子科技大学 | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude |
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