CN107979367A - A kind of high speed long arc differential driver and differential data interface system - Google Patents
A kind of high speed long arc differential driver and differential data interface system Download PDFInfo
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- CN107979367A CN107979367A CN201711343373.9A CN201711343373A CN107979367A CN 107979367 A CN107979367 A CN 107979367A CN 201711343373 A CN201711343373 A CN 201711343373A CN 107979367 A CN107979367 A CN 107979367A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The embodiment of the invention discloses a kind of high speed long arc differential driver and differential data interface system.The first tail current source of high speed long arc differential driver, the second tail current source, state adjustment circuit, the first differential input signal and the second differential input signal；The state adjustment circuit includes the push-pull circuit that stacked switch pipe is formed, stacked switch pipe includes thin grid oxygen switching tube and thick grid oxygen switching tube, the input terminal of the stacked switch pipe is connected to the first tail current source, the output terminal of stacked switch pipe is connected to the second tail current source, and the control terminal of stacked switch pipe is connected to the first differential input signal and the second differential input signal.The technical solution of the embodiment of the present invention can realize the long arc differential voltage output of fast speed, and power consumption of driver is small.
Description
Technical field
The present embodiments relate to technical field of data transmission, more particularly to a kind of high speed long arc differential driver and difference
Divided data interface system.
Background technology
Society and development in science and technology so far, especially grow at top speed with the rise of big data, all trades and professions all in data volume
Stage.In addition to requirements at the higher level are proposed to memory capacity, calculating speed, the data transfer of high speed is also one for the growth of data volume
Key request.At the same time, as the function of chip and system is increasingly sophisticated, the distribution of chip pin is also more nervous, to each
Module reduces number of pins and proposes requirement.High speed serial differential data-interface is adopted extensively because being well adapted to the demand
Receive.
There is different interface forms according to the difference of application demand, wherein, CML (Current Mode Logic, electric current
Mode logic) circuit is common a kind of high speed differential data interface form when output voltage swing is larger.
Refer to shown in Fig. 1, it includes receiver and the high speed long arc differential driver being made of CML circuits, wherein,
The high speed long arc differential driver being made of CML circuits includes NMOS tube MN11, NMOS tube MN12,2 resistance RD, voltage source
VDD, differential input signal Vi+, differential input signal Vi- and tail current source, the drain electrode of NMOS tube MN11 pass through one of them
Resistance RDVoltage source VDD is connected to, the drain electrode of NMOS tube MN12 passes through another resistance RDIt is connected to voltage source VDD, NMOS tube
The source electrode of MN11 and NMOS tube MN12 are grounded by tail current source, and the grid of NMOS tube MN11 and NMOS tube MN12 connect respectively
To differential input signal Vi+, differential input signal Vi-, the drain electrode of NMOS tube MN12 and another resistance RDBetween formed at a high speed
First difference output end Vo+ of long arc differential driver, the drain electrode of NMOS tube MN11 and one of resistance RDBetween formed
Second difference output end Vo-, the first difference output end Vo+ and the second difference output end Vo- of high speed long arc differential transmitter
The first input end and the second input terminal of receiver are connected to by the first transmission line and the second transmission line respectively, it is assumed that first passes
Defeated line and the second transmission line concatenate a terminal resistance RL, to provide certain decay, the resistance R of internal driveDFor impedance
Matching ensures the signal integrity in transmission, its resistance value and terminal resistance R to reduce reflectionLResistance value it is equal, usually 50
Ω, first input end and the second input terminal are connected directly, and by NMOS tube MN11 conductings and exemplified by NMOS tube MN12 cut-offs, such as
It is I for the single-ended amplitude of oscillation of output voltage shown in Fig. 1U*RLSignal, high speed long arc differential driver then need consumption 4*IUWork
Make electric current, power consumption is larger.
The content of the invention
The embodiment of the present invention provides a kind of high speed long arc differential driver and differential data interface system, can be smaller
Long arc differential signal is exported under power consumption situation.
In a first aspect, an embodiment of the present invention provides a kind of high speed long arc differential driver, including the first tail current source,
Second tail current source, state adjustment circuit, the first differential input signal and the second differential input signal；Wherein：
The state adjustment circuit includes the push-pull circuit that stacked switch pipe is formed, wherein, the stacked switch pipe includes
Thin grid oxygen switching tube and the thick grid oxygen switching tube stacked with the thin grid oxygen switching tube, the input terminal of the stacked switch pipe connect
The first tail current source is connected to, the output terminal of stacked switch pipe is connected to the second tail current source, the control terminal connection of stacked switch pipe
To the first differential input signal and the second differential input signal.
In above-mentioned high speed long arc differential driver, it is preferred that the quantity of the stacked switch pipe is four, two
The input terminal of stacked switch pipe is connected to the first tail current source, and the output terminal of two other stacked switch pipe is connected to second
The input terminal one of tail current source, the output terminal of the two of which stacked switch pipe and two other stacked switch pipe is a pair of
It should connect, the tie point of the corresponding connection forms two difference output ends；First differential input signal and the second difference
Input signal corresponds to the control terminal for accessing to two other stacked switch pipe respectively；The control of the two of which stacked switch pipe
Bias voltage is accessed at end.
In above-mentioned high speed long arc differential driver, it is preferred that the two of which stacked switch pipe includes first
The the first stacked switch pipe and the second PMOS tube of PMOS tube and the 3rd PMOS tube composition and the second heap of the 4th PMOS tube composition
Folded switching tube；Two other described stacked switch pipe includes the 3rd stacked switch pipe that the first NMOS tube and the 3rd NMOS tube form
And second NMOS tube and the 4th NMOS tube composition the 4th stacked switch pipe；
The source electrode of first PMOS tube and the second PMOS tube is connected to the first tail current source, first PMOS tube and
The grid of second PMOS tube accesses the first bias voltage, and the drain electrode of first PMOS tube and the second PMOS tube is respectively connected to
The source electrode of 3rd PMOS tube and the 4th PMOS tube；
The grid of 3rd PMOS tube and the 4th PMOS tube accesses the second bias voltage, the 3rd PMOS tube and
The drain electrode of four PMOS tube is respectively connected to the drain electrode of the 3rd NMOS tube and the 4th NMOS tube；
The grid of 3rd NMOS tube and the 4th NMOS tube accesses the 3rd bias voltage, the 3rd NMOS tube and
The source electrode of four NMOS tubes is respectively connected to the drain electrode of the first NMOS tube and the second NMOS tube；
The grid of first NMOS tube and the second NMOS tube is respectively connected to the first differential input signal and the second difference is defeated
Enter signal；The source electrode of first NMOS tube and the second NMOS tube is connected to the second tail current source；
Form the second difference output end between the drain electrode of 3rd PMOS tube and the drain electrode of the 3rd NMOS tube, the described 4th
The first difference output end is formed between the drain electrode of PMOS tube and the drain electrode of the 4th NMOS tube；
First NMOS tube and the second NMOS tube are thin grid oxygen NMOS tube；3rd NMOS tube and the 4th NMOS tube
Be thick grid oxygen NMOS tube, first PMOS tube and the second PMOS tube are thin grid oxygen PMOS tube, the 3rd PMOS tube and
4th PMOS tube is thick grid oxygen PMOS tube.
In above-mentioned high speed long arc differential driver, it is preferred that the ruler of first NMOS tube and the second NMOS tube
It is very little identical；3rd NMOS tube is identical with the size of the 4th NMOS tube, the size of first PMOS tube and the second PMOS tube
Identical, the 3rd PMOS tube is identical with the size of the 4th PMOS tube.
In above-mentioned high speed long arc differential driver, it is preferred that first tail current source includes voltage source and the
Five PMOS tube, the source electrode of the 5th PMOS tube are connected to voltage source, and the source electrode of first PMOS tube and the second PMOS tube is equal
It is connected to the drain electrode of the 5th PMOS tube；The grid of 5th PMOS tube is connected to biasing networks.
In above-mentioned high speed long arc differential driver, it is preferred that further include Commom-mode feedback circuit；
The Commom-mode feedback circuit includes operational amplifier and detection resistance；The detection resistance include 3rd resistor and
Both ends after 4th resistance, the 3rd resistor and the series connection of the 4th resistance are respectively connected to the first difference output end and the second difference
Output terminal；The normal phase input end of the operational amplifier is connected between 3rd resistor and the 4th resistance；The operational amplifier
Negative-phase input access reference voltage, the output terminal of the operational amplifier is connected to the grid of the 5th PMOS tube.
In above-mentioned high speed long arc differential driver, it is preferred that the voltage between 3rd resistor and the 4th resistance is
Common-mode voltage, the magnitude of voltage of second bias voltage, the 3rd bias voltage and common-mode voltage is the magnitude of voltage of voltage source
1/2.
In above-mentioned high speed long arc differential driver, it is preferred that second tail current source includes current source body
And the current mirror being made of the 5th NMOS tube and the 6th NMOS tube, the drain electrode of the 5th NMOS tube, the grid of the 5th NMOS tube
The grid of pole and the 6th NMOS tube is connected to current source body, and the source electrode of first NMOS tube and the second NMOS tube connects
It is connected to the drain electrode of the 6th NMOS tube, the source grounding of the 5th NMOS tube and the 6th NMOS tube.
In above-mentioned high speed long arc differential driver, it is preferred that the grid of first NMOS tube also passes through first
For capacitance connection to the grid of the first PMOS tube, the grid of second NMOS tube also passes through the second capacitance connection to the second PMOS tube
Grid.
In above-mentioned high speed long arc differential driver, it is preferred that the grid of first PMOS tube passes through the first electricity
Resistance the first bias voltage of access；The grid of second PMOS tube accesses the first bias voltage by second resistance.
Second aspect, an embodiment of the present invention provides a kind of differential data interface system, including receiver；And first party
High speed long arc differential driver described in face；
Described two difference output ends are connected to two input terminals of receiver by corresponding transmission line respectively.
In above-mentioned differential data interface system, it is preferred that be connected with series connection between described two difference output ends
3rd resistor and the 4th resistance, a terminal resistance, the terminal resistance, 3rd resistor and the 4th resistance are concatenated per transmission lines
Resistance value be equal；Two input terminals of receiver are connected by connecting line, the magnitude of voltage on the connecting line is equal to the
Magnitude of voltage between three resistance and the 4th resistance.
A kind of high speed long arc differential driver and differential data interface system provided in the embodiment of the present invention, passes through heap
The push-pull circuit structure differential driver of folded switching tube composition, small power consumption, each stacked switch pipe by thin grid oxygen switching tube with
And the thick grid oxygen switching tube stacked with the thin grid oxygen switching tube forms, wherein, thin grid oxygen switching tube causes current switching speed
It hurry up, and thick grid oxygen switching tube can bear big voltage swing, the two complementation realizes the long arc differential voltage output of fast speed.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing CML high speed differential datas interface circuit；
Fig. 2 is a kind of schematic diagram for high speed long arc differential driver that the embodiment of the present invention one provides；
Fig. 3 is a kind of schematic diagram of differential data interface system provided by Embodiment 2 of the present invention.
Embodiment
Further illustrate technical scheme below with reference to the accompanying drawings and specific embodiments.It is appreciated that
It is that specific embodiment described herein is used only for explaining the present invention, rather than limitation of the invention.Further need exist for illustrating
, for the ease of description, part related to the present invention rather than entire infrastructure are illustrate only in attached drawing.
Embodiment one
It refer to shown in Fig. 2, the embodiment of the present invention one provides a kind of high speed long arc differential driver, including the first tail
Current source 21, the second tail current source 23, state adjustment circuit 22, the first differential input signal Vin+ and the second differential input signal
Vin-；Wherein：
State adjustment circuit 22 includes the push-pull circuit that stacked switch pipe is formed, and stacked switch pipe includes thin grid oxygen (Thin-
Gate-Oxide) switching tube and thick grid oxygen (Thick-Gate-Oxide) switching tube stacked with thin grid oxygen switching tube, it is described
The input terminal of stacked switch pipe is connected to the first tail current source 21, and the output terminal of stacked switch pipe is connected to the second tail current source
23, the control terminal of stacked switch pipe is connected to the first differential input signal Vin+ and the second differential input signal Vin-.
High speed long arc differential driver provided in this embodiment, it uses stacked switch pipe to construct push-pull circuit, is formed
Differential driver, each stacked switch pipe include thin grid oxygen switching tube and thick grid oxygen switching tube, and thin grid oxygen switching tube causes electric current
Switch speed is fast, and thick grid oxygen switching tube can bear big voltage swing, the two complementation realizes the long arc difference of fast speed
Voltage output.
In the present embodiment, specifically scheme introduction is carried out using the quantity of the stacked switch pipe as four.Art technology
Personnel are appreciated that the quantity of stacked switch pipe can also be six or eight etc., can form push-pull circuit.
It is specific as shown in Fig. 2, the input terminal of two of which stacked switch pipe is connected to the first tail current source 21, in addition two
The output terminal of a stacked switch pipe is connected to the second tail current source 23, the output terminal of two of which stacked switch pipe and other two
The input terminal of a stacked switch pipe connects one to one, and the tie point of corresponding connection forms two difference output ends；First difference
Input signal Vin+ and the second differential input signal Vin- corresponds to the control terminal for accessing to two other stacked switch pipe respectively；Its
In the control terminals of two stacked switch pipes access bias voltage.
Aforementioned four stacked switch pipe, two of which stacked switch pipe are respectively defined as the first stacked switch pipe and the second heap
Folded switching tube, two other stacked switch pipe are defined as the 3rd stacked switch pipe and the 4th stacked switch pipe.First stacked switch
The input terminal of pipe is connected to the first tail current source, and the output terminal of the first stacked switch pipe is connected to by the 3rd stacked switch pipe
Two tail current sources, the input terminal of the second stacked switch pipe are connected to the first tail current source, and the output terminal of the second stacked switch pipe leads to
Cross the 4th stacked switch pipe and be connected to the secondth tail current source.Wherein, the first stacked switch pipe and the 4th stacked switch pipe be at the same time
It is on or cut-off state, the second stacked switch pipe and the 3rd stacked switch pipe is at the same time or cut-off state, and
One stacking switching tube and the second stacked switch pipe are in opposite state, the first stacked switch pipe and the interaction of the second stacked switch pipe
Conducting, produces state change.
Driver is considered as a current source, and the electric current of generation wherein arrives receiver all the way by difference transmission lines.
Since receiver shows as high resistant for direct current, certain voltage is produced after the terminal resistance RL that electric current passes through receiving terminal, at the same time
Electric current flows back to driver by another of difference transmission lines.When driver carries out state change, it is by varying flowing through terminal
The sense of current of resistance produces effective ' 0' and ' 1' states.
Specifically, above-mentioned two of which stacked switch pipe includes what the first PMOS tube MP21 and the 3rd PMOS tube MP23 was formed
Second stacked switch pipe of the first stacked switch pipe and the second PMOS tube MP22 and the 4th PMOS tube MP24 composition；Other two
A stacked switch pipe includes the 3rd stacked switch pipe and second that the first NMOS tube MN21 and the 3rd NMOS tube MN23 is formed
4th stacked switch pipe of NMOS tube MN22 and the 4th NMOS tube MN24 compositions.
The source electrode of first PMOS tube MP21 and the second PMOS tube MP22 are connected to the first tail current source, the first PMOS tube
The grid of MP21 and the second PMOS tube MP22 access the first bias voltage Vb, the first PMOS tube MP21 and the second PMOS tube MP22
Drain electrode be respectively connected to the source electrode of the 3rd PMOS tube MP23 and the 4th PMOS tube MP24.
The grid of 3rd PMOS tube MP23 and the 4th PMOS tube MP24 accesses the second bias voltage VGP2, the 3rd PMOS tube
The drain electrode of MP23 and the 4th PMOS tube MP24 is respectively connected to the drain electrode of the 3rd NMOS tube MN23 and the 4th NMOS tube MN24.
The grid of 3rd NMOS tube MN23 and the 4th NMOS tube MN24 accesses the 3rd bias voltage VGN2, the 3rd NMOS tube
The source electrode of MN23 and the 4th NMOS tube MN24 are respectively connected to the drain electrode of the first NMOS tube MN21 and the second NMOS tube MN22.
The grid of first NMOS tube MN21 and the second NMOS tube MN22 are respectively connected to the first differential input signal Vin+ and
Two differential input signal Vin-；The source electrode of first NMOS tube MN21 and the second NMOS tube MN22 are connected to the second tail current source.
The second difference output end is formed between the drain electrode of 3rd PMOS tube MP23 and the drain electrode of the 3rd NMOS tube MN23
Vout-, the first difference output end Vout+ is formed between the drain electrode of the 4th PMOS tube MP24 and the drain electrode of the 4th NMOS tube MN24.
First NMOS tube MN21 and the second NMOS tube MN22 is thin grid oxygen NMOS tube；3rd NMOS tube MN23 and the 4th
NMOS tube MN24 is thick grid oxygen NMOS tube, and the first PMOS tube MP21 and the second PMOS tube MP22 are thin grid oxygen PMOS tube, the
Three PMOS tube MP23 and the 4th PMOS tube MP24 are thick grid oxygen PMOS tube.
It is understood that the quantity of each stacked switch Guan Zhonghou grid oxygens switching tube as needed and thin grid oxygen switching tube
It is adapted to adjust.Meanwhile in practical application, the NMOS tube used for deep N-well NMOS tube, the substrate of deep N-well nmos device
Current potential can be selected independently so as to reduce body bias effect to realize lower threshold voltage.Further need exist for rationally setting some nodes
Current potential is to ensure that output voltage amplitude and device operating voltages are met the requirements, for example, the second bias voltage VGP2, the 3rd biased electrical
Press VGN2It is each about the magnitude of voltage V of voltage source PWRPWR1/2.
Preferable push-pull type differential driver, when at both ends, input signal is equal, its difference output and input signal it is big
It is small unrelated, remain zero.Therefore, the size of each differential pair tube is kept identical as far as possible, in the present embodiment, first
NMOS tube MN21 and the second NMOS tube MN22 composition differential pair tubes, the size of the two are identical；Similarly, the 3rd NMOS tube MN23 and
The size of 4th NMOS tube MN24 is identical, and the size of the first PMOS tube MP21 and the second PMOS tube MP22 are identical, the 3rd PMOS tube
The size of MP23 and the 4th PMOS tube MP24 are identical.
Further, the first tail current source includes voltage source PWR and the 5th PMOS tube MP25, the source of the 5th PMOS tube MP25
The source electrode that pole is connected to voltage source PWR, the first PMOS tube MP21 and the second PMOS tube MP22 is connected to the 5th PMOS tube MP25
Drain electrode；The grid of 5th PMOS tube MP25 is connected to biasing networks.
Further, the second tail current source includes current source body and by the 5th NMOS tube MN25 and the 6th NMOS tube
The current mirror of MN26 compositions, the drain electrode of the 5th NMOS tube MN25, the grid and the 6th NMOS tube MN26 of the 5th NMOS tube MN25
Grid be connected to current source body, the source electrode of the first NMOS tube MN21 and the second NMOS tube MN22 are connected to the 6th NMOS
The source grounding of the drain electrode of pipe MN26, the 5th NMOS tube MN25 and the 6th NMOS tube MN26.
Further, a kind of implementation as the embodiment of the present invention, the grid of the first NMOS tube MN21 also pass through
One capacitance C1 is connected to the grid of the first PMOS tube MP21, and the grid of the second NMOS tube MN22 is also connected to by the second capacitance C2
The grid of second PMOS tube MP22.The grid of first PMOS tube MP21 accesses the first bias voltage Vb by first resistor R1；The
The grid of two PMOS tube MP22 accesses the first bias voltage Vb by second resistance R2.
First differential input signal Vin+ and the second differential input signal Vin- is respectively two input controls of driver
Signal, when the first differential input signal Vin+ is high level, the second differential input signal Vin- is low level, at this time, first
NMOS tube MN21 and the second PMOS tube MP22 conductings, the second NMOS tube MN22 and the first PMOS tube MP21 cut-offs, the second biased electrical
Press VGP2, the 3rd bias voltage VGN2It is each about the magnitude of voltage V of voltage source PWRPWR1/2 so that the 3rd NMOS tube MN23 and the 4th
PMOS tube MP24 is turned on, then electric current can be achieved and flowed from the first difference output end Vout+ to the second difference output end Vout-, instead
It, when the first differential input signal Vin+ is low level, electric current is from the second difference output end Vout- to the first difference output end
Vout+ flows.
A kind of high speed long arc differential driver provided in an embodiment of the present invention, it uses stacked switch pipe construction to recommend electricity
Road, forms differential driver, and each stacked switch pipe includes thin grid oxygen switching tube and thick grid oxygen switching tube, and thin grid oxygen switching tube makes
It is fast to obtain current switching speed, and thick grid oxygen switching tube can bear big voltage swing, the two complementation realizes putting on for fast speed
Width differential voltage exports.
Embodiment two
Embodiment two is connected to receiver on the basis of above-described embodiment, by the output of high speed long arc differential driver,
Realize differential data interface system.It refer to shown in Fig. 3, a kind of differential data interface system, including receiver TX；It is and above-mentioned
The high speed long arc differential driver of embodiment；Described two difference output ends are connected to reception by corresponding transmission line respectively
Two input terminals of device TX.
In the application of specific differential data interface system, naturally it is also possible to be the application of high speed long arc differential driver
In, state adjustment circuit 22 further includes Commom-mode feedback circuit；Commom-mode feedback circuit includes operational amplifier OP and detection electricity
Resistance；Detection resistance includes the both ends difference after 3rd resistor R3 and the 4th resistance R4,3rd resistor R3 and the 4th resistance R4 series connection
It is connected to the first difference output end Vout+ and the second difference output end Vout-；The normal phase input end of operational amplifier OP is connected to
Between 3rd resistor R3 and the 4th resistance R4；The negative-phase input access reference voltage V of operational amplifier OPREF, operational amplifier
The output terminal of OP is connected to the grid of the 5th PMOS tube MP25.
Further, a terminal resistance R is concatenated per transmission linesL, terminal resistance RLSet preferably adjacent to receiver-side,
To provide certain decay.3rd resistor R3 and the 4th resistance R4 is used for impedance matching to reduce reflection, ensures the letter in transmission
Number integrality, its resistance value and terminal resistance RLResistance value it is equal, be usually each about 50 Ω.Preferably, the bias voltage of receiver
VBIASIt is identical with common-mode voltage Vcom, the about magnitude of voltage V of voltage sourcePWR1/2, to ensure that electric current only flows through terminal resistance RL。
Two input terminals of receiver are connected by connecting line, the magnitude of voltage on the connecting line is the bias voltage of receiver
VBIAS.Magnitudes of voltage of the common-mode voltage Vcom between 3rd resistor R3 and the 4th resistance R4.
The operation principle of the embodiment of the present invention is：First tail current source produces one from the 5th PMOS tube MP25 to state tune
The current value that whole circuit 22 flows is 2IUElectric current, similarly, the second tail current source ensures to flow through the electricity of the 6th NMOS tube MN26
The current value of stream is also 2IU.When the first differential input signal Vin+ is high level, the second differential input signal Vin- is low electricity
It is flat, the second stacked switch pipe (MP22 and MP24) and the 3rd stacked switch pipe (MN21 and MN23) conducting, the first stacked switch pipe
(MP21 and MP23) and the 4th stacked switch pipe (MN22 and MN24) end.The electric current that then the first tail current source produces is via second
It is divided into two parts after stacked switch pipe, a portion is flowed by resistance R3 and R4 to the 3rd stacked switch pipe, another part
Pass through the first difference output end Vout+, two terminal resistance RL, the second difference output end Vout- also flow to the 3rd stacked switch
Pipe.The sum of resistance value due to resistance R3 and R4 and two terminal resistance RLThe sum of resistance value it is equal, then flow through receiver-side
And the electric current of detection resistance side is IU, it is I to the single-ended amplitude of oscillation of receiver-side output voltage in this caseU*RLSignal,
High speed long arc differential driver only needs that 2*I need to be consumedUOperating current, power consumption is smaller.Conversely, when driver carries out state
Change, when the first differential input signal Vin+ is low level, the second differential input signal Vin- is high level, then electric current is from second
Difference output end Vout- is flowed to the first difference output end Vout+, so as to change the sense of current generation for flowing through terminal resistance
Effectively ' 0' and ' 1' states.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (12)
1. a kind of high speed long arc differential driver, including the first tail current source, the second tail current source, state adjustment circuit,
One differential input signal and the second differential input signal；It is characterized in that：
The state adjustment circuit includes the push-pull circuit that stacked switch pipe is formed, wherein, the stacked switch pipe includes thin grid
Oxygen switching tube and the thick grid oxygen switching tube stacked with the thin grid oxygen switching tube, the input terminal of the stacked switch pipe are connected to
First tail current source, the output terminal of stacked switch pipe are connected to the second tail current source, and the control terminal of stacked switch pipe is connected to
One differential input signal and the second differential input signal.
2. high speed long arc differential driver according to claim 1, it is characterised in that：The quantity of the stacked switch pipe
For four, the input terminal of two of which stacked switch pipe is connected to the first tail current source, two other stacked switch pipe it is defeated
Outlet is connected to the second tail current source, the output terminal of the two of which stacked switch pipe and two other described stacked switch
The input terminal of pipe connects one to one, and the tie point of the corresponding connection forms two difference output ends；First difference is defeated
Enter signal and the second differential input signal corresponding control terminal for accessing to two other stacked switch pipe respectively；The two of which
The control terminal of stacked switch pipe accesses bias voltage.
3. high speed long arc differential driver according to claim 2, it is characterised in that the two of which stacked switch
Pipe includes the first stacked switch pipe and the second PMOS tube and the 4th PMOS tube group of the first PMOS tube and the 3rd PMOS tube composition
Into the second stacked switch pipe；Two other described stacked switch pipe includes the 3rd that the first NMOS tube and the 3rd NMOS tube form
4th stacked switch pipe of stacked switch pipe and the second NMOS tube and the 4th NMOS tube composition；
The source electrode of first PMOS tube and the second PMOS tube is connected to the first tail current source, first PMOS tube and second
The grid of PMOS tube accesses the first bias voltage, and the drain electrode of first PMOS tube and the second PMOS tube is respectively connected to the 3rd
The source electrode of PMOS tube and the 4th PMOS tube；
The grid of 3rd PMOS tube and the 4th PMOS tube accesses the second bias voltage, the 3rd PMOS tube and the 4th
The drain electrode of PMOS tube is respectively connected to the drain electrode of the 3rd NMOS tube and the 4th NMOS tube；
The grid of 3rd NMOS tube and the 4th NMOS tube accesses the 3rd bias voltage, the 3rd NMOS tube and the 4th
The source electrode of NMOS tube is respectively connected to the drain electrode of the first NMOS tube and the second NMOS tube；
The grid of first NMOS tube and the second NMOS tube is respectively connected to the first differential input signal and the second Differential Input letter
Number；The source electrode of first NMOS tube and the second NMOS tube is connected to the second tail current source；
The second difference output end, the 4th PMOS are formed between the drain electrode of 3rd PMOS tube and the drain electrode of the 3rd NMOS tube
The first difference output end is formed between the drain electrode of pipe and the drain electrode of the 4th NMOS tube；
First NMOS tube and the second NMOS tube are thin grid oxygen NMOS tube；3rd NMOS tube and the 4th NMOS tube are
Thick grid oxygen NMOS tube, first PMOS tube and the second PMOS tube are thin grid oxygen PMOS tube, the 3rd PMOS tube and the 4th
PMOS tube is thick grid oxygen PMOS tube.
4. high speed long arc differential driver according to claim 3, it is characterised in that first NMOS tube and second
The size of NMOS tube is identical；3rd NMOS tube is identical with the size of the 4th NMOS tube, first PMOS tube and second
The size of PMOS tube is identical, and the 3rd PMOS tube is identical with the size of the 4th PMOS tube.
5. high speed long arc differential driver according to claim 3, it is characterised in that first tail current source includes
Voltage source and the 5th PMOS tube, the source electrode of the 5th PMOS tube are connected to voltage source, first PMOS tube and the 2nd PMOS
The source electrode of pipe is connected to the drain electrode of the 5th PMOS tube；The grid of 5th PMOS tube is connected to biasing networks.
6. high speed long arc differential driver according to claim 5, it is characterised in that further include Commom-mode feedback electricity
Road；
The Commom-mode feedback circuit includes operational amplifier and detection resistance；The detection resistance includes 3rd resistor and the 4th
Both ends after resistance, the 3rd resistor and the series connection of the 4th resistance are respectively connected to the first difference output end and the second difference output
End；The normal phase input end of the operational amplifier is connected between 3rd resistor and the 4th resistance；The operational amplifier is born
Phase input terminal accesses reference voltage, and the output terminal of the operational amplifier is connected to the grid of the 5th PMOS tube.
7. high speed long arc differential driver according to claim 6, it is characterised in that 3rd resistor and the 4th resistance it
Between voltage be common-mode voltage, the magnitude of voltage of second bias voltage, the 3rd bias voltage and common-mode voltage is voltage
The 1/2 of the magnitude of voltage in source.
8. high speed long arc differential driver according to claim 3, it is characterised in that second tail current source includes
Current source body and the current mirror being made of the 5th NMOS tube and the 6th NMOS tube, the drain electrode of the 5th NMOS tube, the 5th
The grid of NMOS tube and the grid of the 6th NMOS tube are connected to current source body, first NMOS tube and the second NMOS tube
Source electrode be connected to the drain electrode of the 6th NMOS tube, the source grounding of the 5th NMOS tube and the 6th NMOS tube.
9. high speed long arc differential driver according to claim 3, it is characterised in that the grid of first NMOS tube
Grid also by the first capacitance connection to the first PMOS tube, the grid of second NMOS tube also by the second capacitance connection extremely
The grid of second PMOS tube.
10. high speed long arc differential driver according to claim 3, it is characterised in that the grid of first PMOS tube
The first bias voltage is accessed in pole by first resistor；The grid of second PMOS tube accesses the first biased electrical by second resistance
Pressure.
A kind of 11. differential data interface system, it is characterised in that including：
Receiver；And
Such as claim 1-10 any one of them high speed long arc differential drivers；
Described two difference output ends are connected to two input terminals of receiver by corresponding transmission line respectively.
12. differential data interface system according to claim 11, it is characterised in that between described two difference output ends
The 3rd resistor and the 4th resistance of series connection are connected with, a terminal resistance, the terminal resistance, the 3rd electricity are concatenated per transmission lines
The resistance value of resistance and the 4th resistance is equal；Two input terminals of receiver are connected by connecting line, on the connecting line
Magnitude of voltage is equal to the magnitude of voltage between 3rd resistor and the 4th resistance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711343373.9A CN107979367A (en) | 2017-12-14 | 2017-12-14 | A kind of high speed long arc differential driver and differential data interface system |
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| CN201711343373.9A CN107979367A (en) | 2017-12-14 | 2017-12-14 | A kind of high speed long arc differential driver and differential data interface system |
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