CN105680834B - A kind of dynamic comparer of high-speed low-power-consumption - Google Patents
A kind of dynamic comparer of high-speed low-power-consumption Download PDFInfo
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Abstract
Description
Technical field
The present invention relates to Analogous Integrated Electronic Circuits technical field more particularly to a kind of dynamic comparers of high-speed low-power-consumption.
Background technology
Comparator (Comparator) is the important composition module of all multiple ics (IC), such as analog-digital converter (ADC), trsanscondutance amplifier (OTA), voltage-reference (VR) and clock data recovery circuit (CDR), by detecting Differential Input Voltage generates corresponding output, the larger input voltage information of display amplitude.In Modern Communication System, along with portable equipment pair More light weight and smaller size of continuous demand, comparator needs realize high speed operation in a manner of low power consumption and low cost.However, With the diminution (having arrived 40nm and 28nm or even smaller) of Advanced CMOS Process size, the supply voltage of core circuit is also followed It reduces, but the threshold voltage of metal-oxide-semiconductor cannot reduce in the same scale, which has limited the common-mode input ranges of comparator；More Importantly, in order to realize high speed operation, the size of metal-oxide-semiconductor needs bigger in comparator, continuous to compensate supply voltage The influence brought is reduced, this can bring about, and more additional chip areas occupy and power consumption consumes.
The structure of traditional static comparator, as shown in Figure 1.The structure is negative including a pair of of Differential Input pipe, a current mirror Load and a current source, can constantly compare two input signals, carry out control sequential without any clock signal or enable, Therefore static comparison device can be generally used in the occasion that can not provide clock signal.However, static comparison device can face undershoot and mistake The problem of rushing；Moreover, because the tail current source of the structure works always, this can bring larger quiescent dissipation, especially in height Under speed application.
The structure of traditional static latched comparator, as shown in Figure 2.The structure is introduced on the basis of static comparison device Latch signal latch, in reseting stage (latch signals are in low level, and two are latched pipe M5a and M5b conducting), difference output Signal VOP and VON are pulled down to ground, and four metal-oxide-semiconductors M1a, M1b, M2a and M2b constitute prime amplifier, distinguished by M3a and M3b Current mirror to output end VOP and VON；On the other hand, when latch signals are got higher, M5a and M5b are disconnected, flow through M3a and The electric current of M3b will change output voltage, carry out regenerative process.Drain electrode due to Differential Input pipe (M1a and M1b) and output end There is isolation between (VOP and VON), static latch comparator shows low to kick back noise.However, pure quiescent dissipation remains unchanged The structure can not be used under high-speed applications again；In addition, the M3a/M4a and M3b/M4b that are operated in current limited area can be dragged slowly The regenerative process of the structure comparator.
The structure of conventional dynamic comparator, as shown in Figure 3.The structure is widely used in high-speed ADC, is comparing operation Before, CLK signal is in low level, and comparator carries out reset operation, and clock control pipe Mt is disconnected, differential output signal VOP and VON It is precharged pipe M7 and M8 respectively and draws high supply voltage VDD；When CLK signal becomes high level, M7 and M8 are disconnected, Mt conductings, In VIP>In the case of VIN, all latch pipe M3, M4, M5 and M6 start regenerative process, since input pipe M1 ratios M2 is led in advance Logical, output end VON ratios VOP is pulled down to voltage VDD- earlier | Vtp |, therefore M6 is connected before M5, and at this time VOP-VON is just It is the input difference voltage VIP-VIN being amplified；Finally, output end VOP is pulled down to ground, and VON is pulled high to supply voltage VDD；In VIP<In the case of VIN, vice versa for comparator working condition.Dynamic comparer combines strong positive feedback to complete fast speed ratio Compared with, while there is good reliability to noise and mismatch；In addition, once comparison procedure is completed, electric current is automatically stopped, that is, Say no quiescent dissipation.However, since dynamic comparer is stacked more metal-oxide-semiconductor, larger voltage remaining is needed to obtain Suitable delay time, this can cause problem under low pressure deep-submicron CMOS process；In addition, Mt operates mainly in triode Area causes tail current to depend on common mode input, this can be unfavorable for regenerative process.
The structure of traditional double tail dynamic comparers, as shown in Figure 4.Another kind selection of the structure as dynamic comparer, Include the input stage and latch stage that tail current pipe is controlled with a pair of of differential clocks.When CLK low levels, comparator starts multiple Position, M3 and M4 are respectively pre-charged node FN and FP；When CLK high level, comparator starts regeneration stage, two tail current pipes Mt1 and Mt2 are both turned on, and voltage VFN and VFP start to reduce with rate IMt1/CFN (P), therefore a difference dependent on input Voltage △ VFN (P) will be set up；Voltage △ VFN (P) are transmitted to cross-couplings reverse phase by the intergrade being made of M11 and M12 Device (including M7, M8, M9 and M10) also provides good isolation effect between input and output, therefore reduces and kick back noise. Double tail dynamic comparers have less stacking metal-oxide-semiconductor, therefore can be operated in compared under low supply voltage；Moreover, the structure can be with It completes quickly to latch using larger current in latch stage, ensures low imbalance using smaller current in input stage.However, the structure There is still a need for higher common-mode voltages for input stage, can cause trouble at low supply voltages；In addition, being needed in double tail dynamic comparers A pair of of differential clock signal is used, this can bring additional area and power consumption and possible sequence problem.
Invention content
Technical problems based on background technology, the present invention propose a kind of dynamic comparer of high-speed low-power-consumption.
A kind of dynamic comparer of high-speed low-power-consumption proposed by the present invention, including pre-amplification circuit and regenerative latch electricity Road；
Pre-amplification circuit includes input end of clock, the first differential signal input, the second differential signal input, output Node FN and output node FP；Input end of clock is used for input clock signal CLK, the first differential signal input and the second difference Signal input part is respectively used to the first differential input signal of access and the second differential input signal；
Pre-amplification circuit connects DC power supply, and the output voltage VDD and first of output node FN synthesis DC power supplies is poor To export the first differential output signal, the output voltage VDD and second of output node FP synthesis DC power supplies is poor for point input signal Point input signal is to export the second differential output signal；The output node FN and output of regenerative latch circuit and pre-amplification circuit Node FP connections, can be used for latching the first differential output signal and the second differential output signal, and it is defeated to export first Go out signal and the second output signal；
There are two types of shapes according to the clock signal clk tool that input end of clock exports for the dynamic comparer of the high-speed low-power-consumption State：Under first state, the first differential output signal, the second differential output signal, the first output signal and the second output signal are equal In reset state；Under second state, the first differential output signal of regenerative latch circuit pair and the second differential output signal carry out It latches, and exports the first output signal and the second output signal.
Preferably, pre-amplification circuit includes：Input module, clock-reset module, cross-couplings module and tail current mould Block；
Output node FN and output node FP is separately connected the first differential signal input and second poor by input module Sub-signal input terminal；Output node FN connects direct current by concatenated input module with output node FP with tail current module Source, tail current module connect with input end of clock and control its break-make by clock signal clk；First differential output signal can pass through Cross-couplings module control output node FP is turned on or off over the ground is pulled down to ground to control the second differential output signal, and second is poor Point output signal can be controlled output node FN by cross-couplings module and is turned on or off over the ground to be believed with control the first difference output Number it is pulled down to ground；
Output node FN and output node FP passes through clock-reset module ground, clock-reset module and input end of clock It connects and its break-make is controlled by clock signal clk；
Under first state, tail current module open circuit, clock-reset module is connected, the first differential output signal and the second difference Output signal resets；Under second state, the conducting of tail current module, the open circuit of clock-reset module, the first differential output signal according to The output voltage VDD of DC power supply and the lifting of the first differential input signal, the second differential output signal is according to the defeated of DC power supply Go out voltage VDD and the lifting of the second differential input signal.
Preferably, cross-couplings module includes the first on-off element and the second on-off element, and output node FN and output save Point FP is grounded by the first on-off element and the second on-off element respectively, and output node FN connect and passes through with the second on-off element First differential output signal controls the second on-off element working condition, and output node FP connect with the first on-off element and by the Two differential output signals control the first on-off element working condition.
Preferably, tail current module uses PMOS tube Mt, source electrode to connect DC power supply, and grid connects clock input End, drain electrode connection input module.
Preferably, input module includes metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, and cross-couplings module includes metal-oxide-semiconductor M3 and metal-oxide-semiconductor M4, First on-off element is metal-oxide-semiconductor M5, and the second on-off element is metal-oxide-semiconductor M6；
The grid of metal-oxide-semiconductor M1 and the grid of metal-oxide-semiconductor M2 are respectively as the first differential signal input and the second differential signal Input terminal；Output node FN connects the drain electrode of PMOS tube Mt with output node FP by metal-oxide-semiconductor M1 with metal-oxide-semiconductor M2 respectively, and Respectively by metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 ground connection, the grid of metal-oxide-semiconductor M5 and the grid of metal-oxide-semiconductor M6 are connect with input end of clock； Output node FN and output node FP is distinguished by metal-oxide-semiconductor M3 and metal-oxide-semiconductor M4 ground connection, output node FN and output node FP respectively Connect the grid of the grid and metal-oxide-semiconductor M3 of metal-oxide-semiconductor M4.
Preferably, metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 is PMOS tube, and metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 are NMOS tube.
Preferably, under first state, clock signal clk is high level, and under the second state, clock signal clk is low level.
Preferably, regenerative latch circuit includes：First control module, the second control module and cross coupling inverter；The One control module, the second control module and cross coupling inverter are connect with DC power supply；Output node FN and output node FP connects cross coupling inverter, the first control module and cross-couplings with the second control module by the first control module respectively It is equipped with output end OP between phase inverter for exporting the first output signal, is set between the second control module and cross coupling inverter Have output end ON for export the second output signal；Regenerative latch circuit is full symmetric structure.
Preferably, the first control module includes metal-oxide-semiconductor M7, metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15, and the second control module includes MOS Pipe M8, metal-oxide-semiconductor M14 and metal-oxide-semiconductor M16, cross coupling inverter include metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 and metal-oxide-semiconductor M12；Wherein, metal-oxide-semiconductor M7, metal-oxide-semiconductor M8, metal-oxide-semiconductor M9 and metal-oxide-semiconductor M10 are NMOS tube；Metal-oxide-semiconductor M11 and metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, metal-oxide-semiconductor M16 are PMOS tube, and source electrode is all connected with DC power supply；
In cross coupling inverter be equipped with node COP and node CON, node COP be separately connected metal-oxide-semiconductor M11 drain electrode, The drain electrode of metal-oxide-semiconductor M9, the grid and metal-oxide-semiconductor M12 of metal-oxide-semiconductor M10 grid；Node CON be separately connected metal-oxide-semiconductor M12 drain electrode, The drain electrode of metal-oxide-semiconductor M10, the grid and metal-oxide-semiconductor M9 of metal-oxide-semiconductor M11 grid；
Output node FN is separately connected the grid of the grid of metal-oxide-semiconductor M7, the grid of metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15, output end OP is separately connected the source electrode of the drain electrode of metal-oxide-semiconductor M7, the drain electrode of metal-oxide-semiconductor M15 and metal-oxide-semiconductor M9；The source electrode of metal-oxide-semiconductor M7 is grounded, metal-oxide-semiconductor The drain electrode connecting node COP of M13；
Output node FP is separately connected the grid of the grid of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M14 and metal-oxide-semiconductor M16, output end ON is separately connected the source electrode of the drain electrode of metal-oxide-semiconductor M8, the drain electrode of metal-oxide-semiconductor M16 and metal-oxide-semiconductor M10；The source electrode of metal-oxide-semiconductor M8 is grounded, MOS The drain electrode connecting node CON of pipe M14.
In the present invention, in a dynamic mode, quiescent dissipation is not present in pre-amplification circuit A work；And when regenerative latch electricity When road B works, there is no current path between DC power supply and ground, so, the quiescent dissipation of regenerative latch circuit B is negligible not Meter.
In addition, compared to conventional dynamic comparator, the present invention be respectively adopted PMOS tube input pre-amplification circuit and The regenerative latch circuit of NMOS tube input, and two parts circuit only has the metal-oxide-semiconductor of three level stack, is conducive in low supply voltage Under high speed operation；Different from traditional double tail dynamic comparers, the present invention only needs single input clock signal complete At reset and comparison procedure, the sequential of comparator is not only simplified, and effectively save area and power consumption, realize a tool There is the high speed dynamic comparer of high energy efficiency.
Description of the drawings
Fig. 1 is the structural schematic diagram of static comparison device；
Fig. 2 is the structural schematic diagram of static latch comparator；
Fig. 3 is the structural schematic diagram of dynamic comparer；
Fig. 4 is the structural schematic diagram of double tail dynamic comparers；
Fig. 5 is a kind of structural schematic diagram of the dynamic comparer of high-speed low-power-consumption provided by the invention；
Fig. 6 is a kind of circuit diagram of the dynamic comparer of the high-speed low-power-consumption provided in the embodiment of the present invention；
Fig. 7 is a kind of Transient figure of the dynamic comparer of the high-speed low-power-consumption provided in the embodiment of the present invention.
Specific implementation mode
With reference to Fig. 5, a kind of dynamic comparer of high-speed low-power-consumption proposed by the present invention, including pre-amplification circuit A and again Raw latch cicuit B.
Include with reference to Fig. 6, pre-amplification circuit A：Input end of clock, the first differential signal input, the second differential signal Input terminal, output node FN, output node FP, input module, clock-reset module, cross-couplings module and tail current module. Input end of clock is used for input clock signal CLK, and the first differential signal input and the second differential signal input are respectively used to Access the first differential input signal VIPWith the second differential input signal VIN.Input module includes metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, is intersected Coupling module includes the metal-oxide-semiconductor M3 as the first on-off element and metal-oxide-semiconductor M4 as the second on-off element, clock-reset module Including metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6.Metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 is PMOS tube, metal-oxide-semiconductor M3, metal-oxide-semiconductor M4, metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 is NMOS tube.
Tail current module uses PMOS tube Mt, source electrode to connect DC power supply, and grid connects input end of clock to access Clock signal clk, drain electrode are separately connected the source electrode of the source electrode and metal-oxide-semiconductor M2 of metal-oxide-semiconductor M1.The grid of metal-oxide-semiconductor M1 is as first Differential signal input is to access the first differential input signal VIP, the grid of metal-oxide-semiconductor M2 as the second differential signal input with Access the second differential input signal VIN。
Output node FN is separately connected the drain electrode of metal-oxide-semiconductor M1, the drain electrode of metal-oxide-semiconductor M3, the drain electrode of metal-oxide-semiconductor M5 and metal-oxide-semiconductor M4 Grid, the source grounding of the source electrode and metal-oxide-semiconductor M5 of metal-oxide-semiconductor M3, when the grid of metal-oxide-semiconductor M5 connects input end of clock to access Clock signal CLK.Output node FP is separately connected the drain electrode of metal-oxide-semiconductor M2, the drain electrode of metal-oxide-semiconductor M4, the drain electrode of metal-oxide-semiconductor M6 and metal-oxide-semiconductor The grid of the grid of M3, the source grounding of the source electrode and metal-oxide-semiconductor M6 of metal-oxide-semiconductor M4, metal-oxide-semiconductor M6 connects input end of clock to access Clock signal clk.
Clock signal can control PMOS tube Mt, metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 break-makes.When PMOS tube Mt be connected, DC power supply to Input module is powered, the output voltage VDD and the first differential input signal V of output node FN synthesis DC power suppliesIPTo export One differential output signal VFN, the output voltage VDD and the second differential input signal V of output node FP synthesis DC power suppliesINWith defeated Go out the second differential output signal VFP.Meanwhile the first differential output signal VFNOutput node FP can be controlled by cross-couplings module It is turned on or off over the ground to control the second differential output signal VFPIt is pulled down to ground, the second differential output signal VFPIntersection can be passed through Coupling module control output node FN is turned on or off over the ground to control the first differential output signal VFNIt is pulled down to ground.
Specifically, when clock signal clk is high level, PMOS tube Mt cut-off, clock-reset mould metal-oxide-semiconductor M5 in the block and Metal-oxide-semiconductor M6 is both turned on, and output node FN and output node FP pass through metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 ground connection, the first difference output respectively Signal VFNWith the second differential output signal VFPRealize reset with being pulled down to；When clock signal clk is low level, metal-oxide-semiconductor M5 It is turned off with metal-oxide-semiconductor M6, PMOS tube Mt conductings, in input module, the source electrode and grid of metal-oxide-semiconductor M1 obtain DC power supply respectively Output voltage VDD and the first differential input signal VIP, the drain electrode connection output node FN of metal-oxide-semiconductor M1 is to export the first difference output Signal VFN, the source electrode and grid of metal-oxide-semiconductor M2 obtain the output voltage VDD and the second differential input signal V of DC power supply respectivelyIN, The drain electrode of metal-oxide-semiconductor M2 connects output node FP to export the second differential output signal VFP.As the first differential input signal VIPFirst It is increased to certain value, metal-oxide-semiconductor M4 conductings are thus by the second differential output signal VFPIt is pulled down to ground, conversely, when the second difference output Signal VFPIt is first increased to certain value, metal-oxide-semiconductor M3 conductings are thus by the first differential input signal VIPIt is pulled down to ground.
With reference to Fig. 6, in present embodiment, regenerative latch circuit B is full symmetric structure, with pre-amplification circuit A's Output node FN is connected with output node FP, can be used for the first differential output signal VFNWith the second differential output signal VFP It is latched, and exports the first output signal VOPWith the second output signal VON.Regenerative latch circuit B includes：First control mould Block, the second control module and cross coupling inverter.
First control module includes metal-oxide-semiconductor M7, metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15, the second control module include metal-oxide-semiconductor M8, Metal-oxide-semiconductor M14 and metal-oxide-semiconductor M16, cross coupling inverter include metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 and metal-oxide-semiconductor M12.Its In, metal-oxide-semiconductor M7, metal-oxide-semiconductor M8, metal-oxide-semiconductor M9 and metal-oxide-semiconductor M10 are NMOS tube；Metal-oxide-semiconductor M11 and metal-oxide-semiconductor M12, metal-oxide-semiconductor M13, Metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, metal-oxide-semiconductor M16 are PMOS tube, and source electrode is all connected with DC power supply.
In cross coupling inverter be equipped with node COP and node CON, node COP be separately connected metal-oxide-semiconductor M11 drain electrode, The drain electrode of metal-oxide-semiconductor M9, the grid and metal-oxide-semiconductor M12 of metal-oxide-semiconductor M10 grid.Node CON be separately connected metal-oxide-semiconductor M12 drain electrode, The drain electrode of metal-oxide-semiconductor M10, the grid and metal-oxide-semiconductor M9 of metal-oxide-semiconductor M11 grid.
Output node FN is separately connected the grid of the grid of metal-oxide-semiconductor M7, the grid of metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15, output end OP is separately connected the source electrode of the drain electrode of metal-oxide-semiconductor M7, the drain electrode of metal-oxide-semiconductor M15 and metal-oxide-semiconductor M9.The source electrode of metal-oxide-semiconductor M7 is grounded, metal-oxide-semiconductor The drain electrode connecting node COP of M13.
Output node FP is separately connected the grid of the grid of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M14 and metal-oxide-semiconductor M16, output end ON is separately connected the source electrode of the drain electrode of metal-oxide-semiconductor M8, the drain electrode of metal-oxide-semiconductor M16 and metal-oxide-semiconductor M10.The source electrode of metal-oxide-semiconductor M8 is grounded, MOS The drain electrode connecting node CON of pipe M14.
As the first differential output signal V of output node FN outputsFNFor high level, the second difference of output node FP outputs Output signal VFPFor low level：Metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15 cut-offs, metal-oxide-semiconductor M7 conductings, metal-oxide-semiconductor M8 cut-offs, metal-oxide-semiconductor M14 and Metal-oxide-semiconductor M16 conductings, the first output signal V of output end OPOPIt is pulled down to ground, output end ON obtains direct current by metal-oxide-semiconductor M16 The output voltage VDD of power supply is to export the second output signal V of high levelON；Node CON is by metal-oxide-semiconductor M14 from DC power supply High level is obtained, to metal-oxide-semiconductor M11 cut-offs, for metal-oxide-semiconductor M9 source electrodes by metal-oxide-semiconductor M7 ground connection to be connected, node COP passes through MOS Low level is presented in pipe M9 and metal-oxide-semiconductor M7 ground connection, to which the high level of node CON is latched in metal-oxide-semiconductor M12 conductings, metal-oxide-semiconductor M10 ends the second output signal V to output end ONONIt is latched.At this point, the metal-oxide-semiconductor M8 of branch where output node ON is disconnected It opens, metal-oxide-semiconductor M11, M13 and M15 of branch where output node OP are disconnected so that there is no electric current logical between DC power supply and ground Road advantageously reduces the quiescent dissipation of regenerative latch circuit B.
As the first differential output signal V of output node FN outputsFNFor low level, the second difference of output node FP outputs Output signal VFPFor high level；Metal-oxide-semiconductor M13 and metal-oxide-semiconductor M15 conductings, metal-oxide-semiconductor M7 cut-offs, metal-oxide-semiconductor M8 conductings, metal-oxide-semiconductor M14 and Metal-oxide-semiconductor M16 cut-offs, to the second output signal VONGround, the first output signal V are pulled down to by metal-oxide-semiconductor M8OPPass through metal-oxide-semiconductor M15 High level is obtained from DC power supply；Node COP obtains high level by metal-oxide-semiconductor M13 from DC power supply, to which metal-oxide-semiconductor M12 is cut Only, metal-oxide-semiconductor M10 is connected, and low level is presented by metal-oxide-semiconductor M10 and metal-oxide-semiconductor M8 ground connection in node CON, to metal-oxide-semiconductor M11 conductings It is latched with the high level to node COP, metal-oxide-semiconductor M9 cut-offs are with to the first output signal VOPIt is latched.At this point, output section Branch metal-oxide-semiconductor M7 is disconnected where point OP, and branch M12, M14 and M16 are disconnected where output node ON so that in DC power supply and ground Between there is no current path, advantageously reduce the quiescent dissipation of regenerative latch circuit B.
The clock signal clk that the dynamic comparer for the high-speed low-power-consumption that present embodiment provides is exported according to input end of clock With two states.
Under first state, clock signal clk is high level, and the PMOS tube Mt of tail current module ends to avoid static work( Consumption, clock-reset mould metal-oxide-semiconductor M5 in the block and metal-oxide-semiconductor M6 conductings, the first differential output signal VFNWith the second differential output signal VFPIt is resetted with being pulled down to；Metal-oxide-semiconductor M7 and metal-oxide-semiconductor M8 cut-offs, metal-oxide-semiconductor M13, metal-oxide-semiconductor M15, metal-oxide-semiconductor M14 and metal-oxide-semiconductor M16 is both turned on, the first output signal VOPWith the second output signal VONRespectively by metal-oxide-semiconductor M15 and metal-oxide-semiconductor M16 from DC power supply High level is obtained to be resetted.
Under second state, clock signal clk is low level, the PMOS tube Mt conductings of tail current module, clock-reset module In metal-oxide-semiconductor M5 and metal-oxide-semiconductor M6 cut-off.At this point, the output voltage VDD of output node FN synthesis DC power supplies and the first difference are defeated Enter signal VIPTo export the first differential output signal VFN, the output voltage VDD and second of output node FP synthesis DC power supply is poor Divide input signal VINTo export the second differential output signal VFP.With VIP>VINFor, the first differential output signal V at this timeFNRise Speed is slower than the second differential output signal VFP, with the second differential output signal VFPContinuous raising, when it reaches preset value, Metal-oxide-semiconductor M3 conductings are thus by the first differential output signal VFNIt is pulled down to ground, and metal-oxide-semiconductor M4 maintains cut-off state so that output section Point FP is completely charged, to the second differential output signal VFPHigh level is presented, under cross coupling inverter effect, second is defeated Go out signal VONExport low level, the first output signal VOPExport high level.
Conversely, working as VIN>VIP, the second differential output signal V at this timeFPThe rate of climb is slower than the first differential output signal VFN, with The first differential output signal VFNContinuous raising, when it reaches preset value, metal-oxide-semiconductor M4 conductings are to believe the second difference output Number VFPIt is pulled down to ground, and metal-oxide-semiconductor M3 maintains cut-off state so that output node FN is completely charged, to the first difference output Signal VFNHigh level is presented, under cross coupling inverter effect, the first output signal VOPExport low level, the second output letter Number VONExport high level.
In present embodiment, in a dynamic mode, quiescent dissipation is not present in pre-amplification circuit A work；And when regeneration lock When depositing circuit B work, there is no current path between DC power supply and ground, so, the quiescent dissipation of regenerative latch circuit B is negligible Disregard.
Specific the present invention is verified below in conjunction with one.The present embodiment is using the realization of 40nm CMOS technologies, directly The output voltage VDD=1.1V in galvanic electricity source, entire dynamic latch power consumption under 5GHz high-frequency clocks are only 270 μ W, and are occupied Area is only 60.75 μm 2, is tested based on foregoing circuit.
Referring to Fig. 7, the wink of the dynamic comparer as shown in the figure for a kind of high-speed low-power-consumption provided in the embodiment of the present invention State analogous diagram, comparator can work to 5GHz, and each conversion consumption energy is only 54fJ, while delay time narrows down to 55ps, As it can be seen that dynamic comparer provided by the invention can fast implement low-power consumption dynamic latch function under high-speed applications.
The pre-amplification circuit of PMOS tube input and the regenerative latch electricity of NMOS tube input are respectively adopted in present embodiment Road, and two parts circuit only has the metal-oxide-semiconductor of three level stack, is conducive to high speed operation at low supply voltages；Different from passing The double tail dynamic comparers of system, the present invention only need single input clock signal that can complete reset and comparison procedure, not only The sequential of comparator is simplified, and effectively saves area and power consumption, realizes a high speed dynamic ratio with high energy efficiency Compared with device.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, Any one skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610021289.4A CN105680834B (en) | 2016-01-11 | 2016-01-11 | A kind of dynamic comparer of high-speed low-power-consumption |
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| CN106209035A (en) * | 2016-07-13 | 2016-12-07 | 电子科技大学 | A kind of two stage comparator |
| CN107453737A (en) * | 2017-08-09 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | A kind of low power consumption comparator circuit |
| CN109327209A (en) * | 2018-09-17 | 2019-02-12 | 中国电子科技集团公司第二十四研究所 | A kind of renewable comparator circuit of high speed |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4401901A (en) * | 1981-06-01 | 1983-08-30 | Advanced Micro Devices, Inc. | Comparator |
| CN101355351A (en) * | 2007-07-23 | 2009-01-28 | 杭州中科微电子有限公司 | CMOS low-power consumption, low offset voltage, low return-stroke noise comparator |
| CN201341126Y (en) * | 2008-12-30 | 2009-11-04 | 上海贝岭股份有限公司 | Current switch type BiCMOS latch comparator circuit |
| CN201854264U (en) * | 2010-12-01 | 2011-06-01 | 四川和芯微电子股份有限公司 | High-speed dynamic comparison latch |
| CN102957405A (en) * | 2011-08-30 | 2013-03-06 | 安凯(广州)微电子技术有限公司 | Dynamic latch comparator |
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2016
- 2016-01-11 CN CN201610021289.4A patent/CN105680834B/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4401901A (en) * | 1981-06-01 | 1983-08-30 | Advanced Micro Devices, Inc. | Comparator |
| CN101355351A (en) * | 2007-07-23 | 2009-01-28 | 杭州中科微电子有限公司 | CMOS low-power consumption, low offset voltage, low return-stroke noise comparator |
| CN201341126Y (en) * | 2008-12-30 | 2009-11-04 | 上海贝岭股份有限公司 | Current switch type BiCMOS latch comparator circuit |
| CN201854264U (en) * | 2010-12-01 | 2011-06-01 | 四川和芯微电子股份有限公司 | High-speed dynamic comparison latch |
| CN102957405A (en) * | 2011-08-30 | 2013-03-06 | 安凯(广州)微电子技术有限公司 | Dynamic latch comparator |
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| CN105680834A (en) | 2016-06-15 |
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