CN105680834B - A kind of dynamic comparer of high-speed low-power-consumption - Google Patents

A kind of dynamic comparer of high-speed low-power-consumption Download PDF

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CN105680834B
CN105680834B CN201610021289.4A CN201610021289A CN105680834B CN 105680834 B CN105680834 B CN 105680834B CN 201610021289 A CN201610021289 A CN 201610021289A CN 105680834 B CN105680834 B CN 105680834B
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CN105680834A (en
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黄森
林福江
周煜凯
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University of Science and Technology of China USTC
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    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral

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Abstract

本发明公开了一种高速低功耗的动态比较器,包括前置放大电路和再生锁存电路;前置放大电路包括时钟输出端、第一差分信号输入端、第二差分信号输入端、输出节点FN和输出节点FP;前置放大电路连接直流电源,输出节点FN合成直流电源的输出电压VDD和第一差分输入信号以输出第一差分输出信号,输出节点FP合成直流电源的输出电压VDD和第二差分输入信号以输出第二差分输出信号;再生锁存电路与前置放大电路的输出节点FN和输出节点FP连接,其可用于对第一差分输出信号和第二差分输出信号进行锁存,并输出第一输出信号和第二输出信号。本发明提供的动态比较器可在高速应用下快速实现低功耗动态锁存功能。

The invention discloses a dynamic comparator with high speed and low power consumption, which includes a preamplifier circuit and a regenerative latch circuit; the preamplifier circuit includes a clock output terminal, a first differential signal input terminal, a second differential signal input terminal, an output Node FN and output node FP; the preamplifier circuit is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal to output the first differential output signal, and the output node FP synthesizes the output voltage VDD of the DC power supply and The second differential input signal to output the second differential output signal; the regenerative latch circuit is connected to the output node FN and the output node FP of the preamplifier circuit, which can be used to latch the first differential output signal and the second differential output signal , and output the first output signal and the second output signal. The dynamic comparator provided by the invention can quickly realize the low power consumption dynamic latch function under high-speed application.

Description

一种高速低功耗的动态比较器A high-speed and low-power dynamic comparator

技术领域technical field

本发明涉及模拟集成电路技术领域,尤其涉及一种高速低功耗的动态比较器。The invention relates to the technical field of analog integrated circuits, in particular to a dynamic comparator with high speed and low power consumption.

背景技术Background technique

比较器(Comparator)是诸多集成电路(IC)的重要组成模块,比如模数转换器(ADC)、跨导放大器(OTA)、电压基准源(VR)和时钟数据恢复电路(CDR),通过检测差分输入电压产生对应输出,显示幅度较大的输入电压信息。在现代通信系统中,伴随着便携设备对更轻重量和更小尺寸的不断需求,比较器需要以低功耗低成本的方式实现高速工作。然而,随着先进CMOS工艺尺寸的缩小(已到40nm和28nm,甚至更小),核心电路的电源电压也跟着降低,但MOS管的阈值电压却不能以相同的比例降低,这限制了比较器的共模输入范围;更重要的是,为了能够实现高速操作,比较器中MOS管的尺寸需要更大,来补偿电源电压不断降低带来的影响,这就会带来更多额外的芯片面积占用和功耗消耗。Comparator (Comparator) is an important component module of many integrated circuits (IC), such as analog-to-digital converter (ADC), transconductance amplifier (OTA), voltage reference source (VR) and clock data recovery circuit (CDR), through detection The differential input voltage produces a corresponding output that displays input voltage information with a larger magnitude. In modern communication systems, with the ever-increasing demand for lighter weight and smaller size in portable devices, comparators need to achieve high-speed operation with low power consumption and low cost. However, with the reduction of advanced CMOS process size (to 40nm and 28nm, even smaller), the power supply voltage of the core circuit is also reduced, but the threshold voltage of the MOS tube cannot be reduced in the same proportion, which limits the comparator The common-mode input range; more importantly, in order to achieve high-speed operation, the size of the MOS tube in the comparator needs to be larger to compensate for the impact of the continuous reduction of the power supply voltage, which will bring more additional chip area occupancy and power consumption.

传统静态比较器的结构,如图1所示。该结构包括一对差分输入管、一个电流镜负载和一个电流源,会不断的比较两个输入信号,而不需要任何时钟信号来控制时序或使能,因此静态比较器一般可用在无法提供时钟信号的场合。然而,静态比较器会面临下冲和过冲的问题;而且,由于该结构的尾电流源一直工作,这会带来较大的静态功耗,尤其是在高速应用下。The structure of a traditional static comparator is shown in Figure 1. The structure includes a pair of differential input transistors, a current mirror load and a current source, which will continuously compare the two input signals without any clock signal to control the timing or enable, so the static comparator can generally be used when the clock cannot be provided signal occasions. However, the static comparator will face the problem of undershoot and overshoot; moreover, since the tail current source of this structure is always on, this will bring a large static power consumption, especially in high-speed applications.

传统静态锁存比较器的结构,如图2所示。该结构是在静态比较器的基础上引入了锁存信号latch,在复位阶段(latch信号处于低电平,两个锁存管M5a和M5b导通),差分输出信号VOP和VON被拉低到地,四个MOS管M1a、M1b、M2a和M2b构成预放大器,通过M3a和M3b分别把电流镜像到输出端VOP和VON;另一方面,当latch信号变高,M5a和M5b均断开,流过M3a和M3b的电流将改变输出电压,进行再生过程。由于差分输入管(M1a和M1b)的漏极和输出端(VOP和VON)之间存在隔离,静态锁存比较器表现出低踢回噪声。然而,纯粹的静态功耗依旧让该结构无法再高速应用下被采用;另外,工作在电流受限区的M3a/M4a和M3b/M4b会拖慢该结构比较器的再生过程。The structure of a traditional static latch comparator is shown in Figure 2. This structure introduces the latch signal latch on the basis of the static comparator. In the reset phase (the latch signal is at low level, and the two latch transistors M5a and M5b are turned on), the differential output signals VOP and VON are pulled down to Ground, four MOS transistors M1a, M1b, M2a and M2b form a pre-amplifier, and mirror the current to the output terminals VOP and VON through M3a and M3b respectively; on the other hand, when the latch signal becomes high, both M5a and M5b are disconnected, and the current The current passing through M3a and M3b will change the output voltage and carry out the regeneration process. Static latching comparators exhibit low kickback noise due to isolation between the drains of the differential input transistors (M1a and M1b) and the output terminals (VOP and VON). However, the pure static power consumption still makes this structure unsuitable for high-speed applications; in addition, M3a/M4a and M3b/M4b operating in the current-limited region will slow down the regeneration process of the comparator of this structure.

传统动态比较器的结构,如图3所示。该结构被广泛应用在高速ADC里,在比较操作前,CLK信号处于低电平,比较器进行复位操作,时钟控制管Mt断开,差分输出信号VOP和VON分别被预充电管M7和M8拉高到电源电压VDD;当CLK信号变成高电平,M7和M8断开,Mt导通,在VIP>VIN的情况下,所有的锁存管M3、M4、M5和M6开始再生过程,由于输入管M1比M2提前导通,输出端VON比VOP更早被拉低到电压VDD-|Vtp|,因此M6在M5之前导通,这时候VOP-VON就是被放大的输入差分电压VIP-VIN;最终,输出端VOP被拉低到地,VON被拉高到电源电压VDD;在VIP<VIN的情况下,比较器工作情况反之亦然。动态比较器结合强正反馈完成快速比较,同时对噪声和失配具有良好的可靠性;另外,一旦比较过程完成,电流自动停止,也就是说没有静态功耗。然而,由于动态比较器堆叠了较多的MOS管,需要较大的电压余度来获得合适的延迟时间,这会在低压深亚微米CMOS工艺下引起问题;还有,Mt主要工作在三极管区,导致尾电流依赖于输入共模电压,这会不利于再生过程。The structure of a traditional dynamic comparator is shown in Figure 3. This structure is widely used in high-speed ADCs. Before the comparison operation, the CLK signal is at low level, the comparator performs a reset operation, the clock control tube Mt is disconnected, and the differential output signals VOP and VON are respectively pulled by the pre-charge tubes M7 and M8. High to the power supply voltage VDD; when the CLK signal becomes high level, M7 and M8 are disconnected, and Mt is turned on. In the case of VIP>VIN, all latch tubes M3, M4, M5 and M6 start the regeneration process, because The input tube M1 is turned on earlier than M2, and the output terminal VON is pulled down to the voltage VDD-|Vtp| earlier than VOP, so M6 is turned on before M5. At this time, VOP-VON is the amplified input differential voltage VIP-VIN ; Finally, the output terminal VOP is pulled down to the ground, and VON is pulled up to the power supply voltage VDD; in the case of VIP<VIN, the comparator works vice versa. The dynamic comparator combines strong positive feedback to perform fast comparisons while having good reliability against noise and mismatch; in addition, once the comparison process is completed, the current flow is automatically stopped, that is, there is no static power consumption. However, since the dynamic comparator stacks more MOS transistors, a large voltage margin is required to obtain a suitable delay time, which will cause problems in the low-voltage deep submicron CMOS process; in addition, Mt mainly works in the triode region , causing the tail current to depend on the input common-mode voltage, which can be detrimental to the regeneration process.

传统双尾动态比较器的结构,如图4所示。该结构作为动态比较器的另一种选择,包括了具有一对差分时钟控制尾电流管的输入级和锁存级。当CLK低电平时,比较器开始复位,M3和M4分别对节点FN和FP预充电;当CLK高电平时,比较器开始再生阶段,两个尾电流管Mt1和Mt2均导通,电压VFN和VFP开始以速率IMt1/CFN(P)降低,因此一个依赖于输入的差分电压△VFN(P)将建立起来;由M11和M12构成的中间级把电压△VFN(P)传递到交叉耦合反相器(包括M7、M8、M9和M10),也提供了输入输出之间良好的隔离效果,因此降低了踢回噪声。双尾动态比较器具有较少的堆叠MOS管,因此可工作在较低电源电压下;而且,该结构可以在锁存级使用较大电流完成快速锁存,在输入级使用较小电流保证低失调。然而,该结构的输入级仍需要较高的共模电压,在低电源电压下会造成麻烦;另外,在双尾动态比较器里需要使用一对差分时钟信号,这会带来额外的面积和功耗以及可能的时序问题。The structure of a traditional double-tailed dynamic comparator is shown in Figure 4. As an alternative to the dynamic comparator, this structure includes an input stage and a latch stage with a pair of differentially clocked tail current transistors. When CLK is at a low level, the comparator starts to reset, and M3 and M4 precharge the nodes FN and FP respectively; when CLK is at a high level, the comparator starts to regenerate, and the two tail current transistors Mt1 and Mt2 are both turned on, and the voltages VFN and VFP begins to decrease at the rate IMt1/CFN(P), so an input-dependent differential voltage △VFN(P) will build up; the intermediate stage consisting of M11 and M12 delivers the voltage △VFN(P) to the cross-coupled inverting devices (including M7, M8, M9, and M10), also provide good isolation between input and output, thus reducing kickback noise. The double-tailed dynamic comparator has fewer stacked MOS transistors, so it can work at a lower power supply voltage; moreover, this structure can use a large current in the latch stage to complete fast latching, and use a small current in the input stage to ensure low out of tune. However, the input stage of this structure still requires a high common-mode voltage, which can cause trouble at low supply voltages; in addition, a pair of differential clock signals is required in the dual-tailed dynamic comparator, which brings additional area and Power consumption and possible timing issues.

发明内容Contents of the invention

基于背景技术存在的技术问题,本发明提出了一种高速低功耗的动态比较器。Based on the technical problems existing in the background technology, the present invention proposes a dynamic comparator with high speed and low power consumption.

本发明提出的一种高速低功耗的动态比较器,包括前置放大电路和再生锁存电路;A high-speed and low-power dynamic comparator proposed by the present invention includes a preamplifier circuit and a regenerative latch circuit;

前置放大电路包括时钟输入端、第一差分信号输入端、第二差分信号输入端、输出节点FN和输出节点FP;时钟输入端用于输入时钟信号CLK,第一差分信号输入端和第二差分信号输入端分别用于接入第一差分输入信号和第二差分输入信号;The preamplifier circuit includes a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN and an output node FP; the clock input terminal is used to input a clock signal CLK, and the first differential signal input terminal and the second differential signal input terminal The differential signal input terminals are respectively used to access the first differential input signal and the second differential input signal;

前置放大电路连接直流电源,输出节点FN合成直流电源的输出电压VDD和第一差分输入信号以输出第一差分输出信号,输出节点FP合成直流电源的输出电压VDD和第二差分输入信号以输出第二差分输出信号;再生锁存电路与前置放大电路的输出节点FN和输出节点FP连接,其可用于对第一差分输出信号和第二差分输出信号进行锁存,并输出第一输出信号和第二输出信号;The preamplifier circuit is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal to output the first differential output signal, and the output node FP synthesizes the output voltage VDD of the DC power supply and the second differential input signal to output The second differential output signal; the regenerative latch circuit is connected to the output node FN and the output node FP of the preamplifier circuit, which can be used to latch the first differential output signal and the second differential output signal, and output the first output signal and a second output signal;

所述高速低功耗的动态比较器根据时钟输入端输出的时钟信号CLK具有两种状态:第一状态下,第一差分输出信号、第二差分输出信号、第一输出信号和第二输出信号均处于复位状态;第二状态下,再生锁存电路对第一差分输出信号和第二差分输出信号进行锁存,并输出第一输出信号和第二输出信号。The high-speed and low-power dynamic comparator has two states according to the clock signal CLK output by the clock input terminal: in the first state, the first differential output signal, the second differential output signal, the first output signal and the second output signal Both are in the reset state; in the second state, the regenerative latch circuit latches the first differential output signal and the second differential output signal, and outputs the first output signal and the second output signal.

优选地,前置放大电路包括:输入模块、时钟复位模块、交叉耦合模块和尾电流模块;Preferably, the preamplification circuit includes: an input module, a clock reset module, a cross-coupling module and a tail current module;

输出节点FN和输出节点FP通过输入模块分别连接第一差分信号输入端和第二差分信号输入端;输出节点FN和输出节点FP通过串联的输入模块和尾电流模块连接直流电源,尾电流模块与时钟输入端连接并由时钟信号CLK控制其通断;第一差分输出信号可通过交叉耦合模块控制输出节点FP对地导通或断开以控制第二差分输出信号拉低到地,第二差分输出信号可通过交叉耦合模块控制输出节点FN对地导通或断开以控制第一差分输出信号拉低到地;The output node FN and the output node FP are respectively connected to the first differential signal input terminal and the second differential signal input terminal through the input module; the output node FN and the output node FP are connected to the DC power supply through the serial input module and the tail current module, and the tail current module and The clock input terminal is connected and controlled by the clock signal CLK; the first differential output signal can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal to be pulled down to the ground, and the second differential output signal The output signal can control the output node FN to be turned on or off to the ground through the cross-coupling module to control the first differential output signal to be pulled down to the ground;

输出节点FN和输出节点FP均通过时钟复位模块接地,时钟复位模块与时钟输入端连接并由时钟信号CLK控制其通断;Both the output node FN and the output node FP are grounded through the clock reset module, and the clock reset module is connected to the clock input terminal and controlled by the clock signal CLK to turn it on and off;

第一状态下,尾电流模块断路,时钟复位模块导通,第一差分输出信号和第二差分输出信号复位;第二状态下,尾电流模块导通,时钟复位模块断路,第一差分输出信号根据直流电源的输出电压VDD和第一差分输入信号升降,第二差分输出信号根据直流电源的输出电压VDD和第二差分输入信号升降。In the first state, the tail current module is turned off, the clock reset module is turned on, and the first differential output signal and the second differential output signal are reset; in the second state, the tail current module is turned on, the clock reset module is turned off, and the first differential output signal The second differential output signal rises and falls according to the output voltage VDD of the DC power supply and the first differential input signal, and the second differential output signal rises and falls according to the output voltage VDD of the DC power supply and the second differential input signal.

优选地,交叉耦合模块包括第一通断元件和第二通断元件,输出节点FN和输出节点FP分别通过第一通断元件和第二通断元件接地,输出节点FN与第二通断元件连接并通过第一差分输出信号控制第二通断元件工作状态,输出节点FP与第一通断元件连接并通过第二差分输出信号控制第一通断元件工作状态。Preferably, the cross-coupling module includes a first on-off element and a second on-off element, the output node FN and the output node FP are respectively grounded through the first on-off element and the second on-off element, and the output node FN and the second on-off element connected to and control the working state of the second on-off element through the first differential output signal, the output node FP is connected to the first on-off element and controls the working state of the first on-off element through the second differential output signal.

优选地,尾电流模块采用PMOS管Mt,其源极连接直流电源,其栅极连接时钟输入端,其漏极连接输入模块。Preferably, the tail current module adopts a PMOS transistor Mt, its source is connected to a DC power supply, its gate is connected to a clock input terminal, and its drain is connected to an input module.

优选地,输入模块包括MOS管M1和MOS管M2,交叉耦合模块包括MOS管M3和MOS管M4,第一通断元件为MOS管M5,第二通断元件为MOS管M6;Preferably, the input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 and a MOS transistor M4, the first on-off element is a MOS transistor M5, and the second on-off element is a MOS transistor M6;

MOS管M1的栅极和MOS管M2的栅极分别作为第一差分信号输入端和第二差分信号输入端;输出节点FN和输出节点FP分别通过MOS管M1和和MOS管M2连接PMOS管Mt的漏极,并分别通过MOS管M5和MOS管M6接地,MOS管M5的栅极和MOS管M6的栅极均与时钟输入端连接;输出节点FN和输出节点FP分别通过MOS管M3和MOS管M4接地,输出节点FN和输出节点FP分别连接MOS管M4的栅极和MOS管M3的栅极。The gate of the MOS transistor M1 and the gate of the MOS transistor M2 are respectively used as the first differential signal input terminal and the second differential signal input terminal; the output node FN and the output node FP are respectively connected to the PMOS transistor Mt through the MOS transistor M1 and the MOS transistor M2 The drain of the MOS transistor M5 and the MOS transistor M6 are connected to the ground respectively, and the gate of the MOS transistor M5 and the gate of the MOS transistor M6 are connected to the clock input terminal; the output node FN and the output node FP are respectively connected to the MOS transistor M3 and the MOS The transistor M4 is grounded, and the output node FN and the output node FP are connected to the gate of the MOS transistor M4 and the gate of the MOS transistor M3 respectively.

优选地,MOS管M1和MOS管M2为PMOS管,MOS管M3、MOS管M4、MOS管M5和MOS管M6为NMOS管。Preferably, the MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3, the MOS transistor M4, the MOS transistor M5 and the MOS transistor M6 are NMOS transistors.

优选地,第一状态下,时钟信号CLK为高电平,第二状态下,时钟信号CLK为低电平。Preferably, in the first state, the clock signal CLK is at high level, and in the second state, the clock signal CLK is at low level.

优选地,再生锁存电路包括:第一控制模块、第二控制模块和交叉耦合反相器;第一控制模块、第二控制模块和交叉耦合反相器均与直流电源连接;输出节点FN和输出节点FP分别通过第一控制模块和第二控制模块连接交叉耦合反相器,第一控制模块和交叉耦合反相器之间设有输出端OP用于输出第一输出信号,第二控制模块和交叉耦合反相器之间设有输出端ON用于输出第二输出信号;再生锁存电路为完全对称结构。Preferably, the regenerative latch circuit includes: a first control module, a second control module and a cross-coupled inverter; the first control module, the second control module and the cross-coupled inverter are all connected to a DC power supply; the output nodes FN and The output node FP is respectively connected to the cross-coupled inverter through the first control module and the second control module, an output terminal OP is provided between the first control module and the cross-coupled inverter for outputting the first output signal, and the second control module An output terminal ON is provided between the cross-coupled inverter and the second output signal; the regenerative latch circuit has a completely symmetrical structure.

优选地,第一控制模块包括MOS管M7、MOS管M13和MOS管M15,第二控制模块包括MOS管M8、MOS管M14和MOS管M16,交叉耦合反相器包括MOS管M9、MOS管M10、MOS管M11和MOS管M12;其中,MOS管M7、MOS管M8、MOS管M9和MOS管M10均为NMOS管;MOS管M11和MOS管M12、MOS管M13、MOS管M14、MOS管M15、MOS管M16为PMOS管,且源极均连接直流电源;Preferably, the first control module includes a MOS transistor M7, a MOS transistor M13, and a MOS transistor M15, the second control module includes a MOS transistor M8, a MOS transistor M14, and a MOS transistor M16, and the cross-coupled inverter includes a MOS transistor M9, a MOS transistor M10 , MOS tube M11 and MOS tube M12; among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11 and MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15 , MOS tube M16 is a PMOS tube, and the source is connected to a DC power supply;

交叉耦合反相器中设有节点COP和节点CON,节点COP分别连接MOS管M11的漏极、MOS管M9的漏极、MOS管M10的栅极和MOS管M12的栅极;节点CON分别连接MOS管M12的漏极、MOS管M10的漏极、MOS管M11的栅极和MOS管M9的栅极;The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12; the node CON is respectively connected to The drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9;

输出节点FN分别连接MOS管M7的栅极、MOS管M13的栅极和MOS管M15的栅极,输出端OP分别连接MOS管M7的漏极、MOS管M15的漏极和MOS管M9的源极;MOS管M7的源极接地,MOS管M13的漏极连接节点COP;The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole; the source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP;

输出节点FP分别连接MOS管M8的栅极、MOS管M14的栅极和MOS管M16的栅极,输出端ON分别连接MOS管M8的漏极、MOS管M16的漏极和MOS管M10的源极;MOS管M8的源极接地,MOS管M14的漏极连接节点CON。The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole; the source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON.

本发明中,前置放大电路A工作在动态模式下,不存在静态功耗;而当再生锁存电路B工作时,直流电源和地之间没有电流通路,故而,再生锁存电路B的静态功耗可忽略不计。In the present invention, the preamplifier circuit A works in a dynamic mode, and there is no static power consumption; and when the regenerative latch circuit B is working, there is no current path between the DC power supply and the ground, so the static power of the regenerative latch circuit B Power consumption is negligible.

此外,相比于传统动态比较器,本发明分别采用PMOS管输入的前置放大电路和NMOS管输入的再生锁存电路,且两部分电路均只有三层堆叠的MOS管,有利于在低电源电压下的高速工作;不同于传统双尾动态比较器的是,本发明只需要单个输入时钟信号就可完成复位和比较过程,不仅简化了比较器的时序,而且有效节省了面积和功耗,实现了一个具有高能效的高速动态比较器。In addition, compared with the traditional dynamic comparator, the present invention respectively adopts the preamplifier circuit with PMOS tube input and the regenerative latch circuit with NMOS tube input, and both parts of the circuit have only three-layer stacked MOS tubes, which is beneficial to low power supply High-speed operation under voltage; different from the traditional double-tailed dynamic comparator, the present invention only needs a single input clock signal to complete the reset and comparison process, which not only simplifies the timing of the comparator, but also effectively saves area and power consumption. A high-speed dynamic comparator with high energy efficiency is implemented.

附图说明Description of drawings

图1为静态比较器的结构示意图;Fig. 1 is the structural representation of static comparator;

图2为静态锁存比较器的结构示意图;Fig. 2 is a structural schematic diagram of a static latch comparator;

图3为动态比较器的结构示意图;Fig. 3 is a structural schematic diagram of a dynamic comparator;

图4为双尾动态比较器的结构示意图;Fig. 4 is the structural representation of double tail dynamic comparator;

图5为本发明提供的一种高速低功耗的动态比较器的结构示意图;FIG. 5 is a schematic structural diagram of a high-speed and low-power dynamic comparator provided by the present invention;

图6为本发明实施例中提供的一种高速低功耗的动态比较器的电路图;FIG. 6 is a circuit diagram of a high-speed and low-power dynamic comparator provided in an embodiment of the present invention;

图7为本发明实施例中提供的一种高速低功耗的动态比较器的瞬态仿真图。FIG. 7 is a transient simulation diagram of a high-speed and low-power dynamic comparator provided in an embodiment of the present invention.

具体实施方式Detailed ways

参照图5,本发明提出的一种高速低功耗的动态比较器,包括前置放大电路A和再生锁存电路B。Referring to FIG. 5 , a high-speed and low-power dynamic comparator proposed by the present invention includes a preamplifier circuit A and a regenerative latch circuit B.

参照图6,前置放大电路A包括:时钟输入端、第一差分信号输入端、第二差分信号输入端、输出节点FN、输出节点FP、输入模块、时钟复位模块、交叉耦合模块和尾电流模块。时钟输入端用于输入时钟信号CLK,第一差分信号输入端和第二差分信号输入端分别用于接入第一差分输入信号VIP和第二差分输入信号VIN。输入模块包括MOS管M1和MOS管M2,交叉耦合模块包括作为第一通断元件的MOS管M3和作为第二通断元件的MOS管M4,时钟复位模块包括MOS管M5和MOS管M6。MOS管M1和MOS管M2为PMOS管,MOS管M3、MOS管M4、MOS管M5和MOS管M6为NMOS管。Referring to FIG. 6, the preamplifier circuit A includes: a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN, an output node FP, an input module, a clock reset module, a cross-coupling module and a tail current module. The clock input terminal is used to input the clock signal CLK, and the first differential signal input terminal and the second differential signal input terminal are respectively used to receive the first differential input signal V IP and the second differential input signal V IN . The input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 as a first on-off element and a MOS transistor M4 as a second on-off element, and the clock reset module includes a MOS transistor M5 and a MOS transistor M6. The MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3 , the MOS transistor M4 , the MOS transistor M5 and the MOS transistor M6 are NMOS transistors.

尾电流模块采用PMOS管Mt,其源极连接直流电源,其栅极连接时钟输入端以接入时钟信号CLK,其漏极分别连接MOS管M1的源极和MOS管M2的源极。MOS管M1的栅极作为第一差分信号输入端以接入第一差分输入信号VIP,MOS管M2的栅极作为第二差分信号输入端以接入第二差分输入信号VINThe tail current module adopts a PMOS transistor Mt, its source is connected to the DC power supply, its gate is connected to the clock input terminal to receive the clock signal CLK, and its drain is respectively connected to the source of the MOS transistor M1 and the source of the MOS transistor M2. The gate of the MOS transistor M1 is used as the first differential signal input terminal for receiving the first differential input signal V IP , and the gate of the MOS transistor M2 is used as the second differential signal input terminal for receiving the second differential input signal V IN .

输出节点FN分别连接MOS管M1的漏极、MOS管M3的漏极、MOS管M5的漏极和MOS管M4的栅极,MOS管M3的源极和MOS管M5的源极均接地,MOS管M5的栅极连接时钟输入端以接入时钟信号CLK。输出节点FP分别连接MOS管M2的漏极、MOS管M4的漏极、MOS管M6的漏极和MOS管M3的栅极,MOS管M4的源极和MOS管M6的源极均接地,MOS管M6的栅极连接时钟输入端以接入时钟信号CLK。The output node FN is respectively connected to the drain of the MOS transistor M1, the drain of the MOS transistor M3, the drain of the MOS transistor M5 and the gate of the MOS transistor M4, the source of the MOS transistor M3 and the source of the MOS transistor M5 are grounded, and the MOS The gate of the transistor M5 is connected to the clock input terminal to receive the clock signal CLK. The output node FP is respectively connected to the drain of the MOS transistor M2, the drain of the MOS transistor M4, the drain of the MOS transistor M6 and the gate of the MOS transistor M3, the source of the MOS transistor M4 and the source of the MOS transistor M6 are both grounded, and the MOS The gate of the transistor M6 is connected to the clock input terminal to receive the clock signal CLK.

时钟信号可控制PMOS管Mt、MOS管M5和MOS管M6通断。当PMOS管Mt导通,直流电源向输入模块供电,输出节点FN合成直流电源的输出电压VDD和第一差分输入信号VIP以输出第一差分输出信号VFN,输出节点FP合成直流电源的输出电压VDD和第二差分输入信号VIN以输出第二差分输出信号VFP。同时,第一差分输出信号VFN可通过交叉耦合模块控制输出节点FP对地导通或断开以控制第二差分输出信号VFP拉低到地,第二差分输出信号VFP可通过交叉耦合模块控制输出节点FN对地导通或断开以控制第一差分输出信号VFN拉低到地。The clock signal can control the on-off of the PMOS transistor Mt, the MOS transistor M5 and the MOS transistor M6. When the PMOS transistor Mt is turned on, the DC power supply supplies power to the input module, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V IP to output the first differential output signal V FN , and the output node FP synthesizes the output of the DC power supply voltage VDD and the second differential input signal V IN to output a second differential output signal V FP . At the same time, the first differential output signal V FN can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal V FP to be pulled down to the ground, and the second differential output signal V FP can be passed through the cross-coupling The module controls the output node FN to be turned on or off to the ground to control the first differential output signal V FN to be pulled down to the ground.

具体地,当时钟信号CLK为高电平,PMOS管Mt截止,时钟复位模块中的MOS管M5和MOS管M6均导通,输出节点FN和输出节点FP分别通过MOS管M5和MOS管M6接地,第一差分输出信号VFN和第二差分输出信号VFP均被拉低到地实现复位;当时钟信号CLK为低电平,MOS管M5和MOS管M6均截止,PMOS管Mt导通,输入模块中,MOS管M1的源极和栅极分别获得直流电源的输出电压VDD和第一差分输入信号VIP,MOS管M1的漏极连接输出节点FN以输出第一差分输出信号VFN,MOS管M2的源极和栅极分别获得直流电源的输出电压VDD和第二差分输入信号VIN,MOS管M2的的漏极连接输出节点FP以输出第二差分输出信号VFP。当第一差分输入信号VIP先升高到一定值,MOS管M4导通从而将第二差分输出信号VFP拉低到地,反之,当第二差分输出信号VFP先升高到一定值,MOS管M3导通从而将第一差分输入信号VIP拉低到地。Specifically, when the clock signal CLK is at a high level, the PMOS transistor Mt is turned off, the MOS transistor M5 and the MOS transistor M6 in the clock reset module are both turned on, and the output node FN and the output node FP are grounded through the MOS transistor M5 and the MOS transistor M6 respectively. , the first differential output signal V FN and the second differential output signal V FP are both pulled down to the ground to realize reset; when the clock signal CLK is low level, both the MOS transistor M5 and the MOS transistor M6 are cut off, and the PMOS transistor Mt is turned on. In the input module, the source and gate of the MOS transistor M1 obtain the output voltage VDD of the DC power supply and the first differential input signal V IP respectively, and the drain of the MOS transistor M1 is connected to the output node FN to output the first differential output signal V FN , The source and gate of the MOS transistor M2 respectively obtain the output voltage VDD of the DC power supply and the second differential input signal V IN , and the drain of the MOS transistor M2 is connected to the output node FP to output the second differential output signal V FP . When the first differential input signal V IP first rises to a certain value, the MOS transistor M4 is turned on to pull the second differential output signal V FP down to the ground; otherwise, when the second differential output signal V FP first rises to a certain value , the MOS transistor M3 is turned on so as to pull down the first differential input signal V IP to ground.

参照图6,本实施方式中,再生锁存电路B为完全对称结构,其与前置放大电路A的输出节点FN和输出节点FP连接,其可用于对第一差分输出信号VFN和第二差分输出信号VFP进行锁存,并输出第一输出信号VOP和第二输出信号VON。再生锁存电路B包括:第一控制模块、第二控制模块和交叉耦合反相器。Referring to Fig. 6, in this embodiment, the regenerative latch circuit B is a completely symmetrical structure, which is connected to the output node FN and the output node FP of the preamplifier circuit A, and it can be used for the first differential output signal V FN and the second The differential output signal V FP is latched, and outputs a first output signal V OP and a second output signal V ON . The regenerative latch circuit B includes: a first control module, a second control module and a cross-coupled inverter.

第一控制模块包括MOS管M7、MOS管M13和MOS管M15,第二控制模块包括MOS管M8、MOS管M14和MOS管M16,交叉耦合反相器包括MOS管M9、MOS管M10、MOS管M11和MOS管M12。其中,MOS管M7、MOS管M8、MOS管M9和MOS管M10均为NMOS管;MOS管M11和MOS管M12、MOS管M13、MOS管M14、MOS管M15、MOS管M16为PMOS管,且源极均连接直流电源。The first control module includes MOS transistor M7, MOS transistor M13 and MOS transistor M15, the second control module includes MOS transistor M8, MOS transistor M14 and MOS transistor M16, and the cross-coupled inverter includes MOS transistor M9, MOS transistor M10, MOS transistor M11 and MOS tube M12. Among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, and MOS tube M16 are PMOS tubes, and The sources are all connected to a DC power supply.

交叉耦合反相器中设有节点COP和节点CON,节点COP分别连接MOS管M11的漏极、MOS管M9的漏极、MOS管M10的栅极和MOS管M12的栅极。节点CON分别连接MOS管M12的漏极、MOS管M10的漏极、MOS管M11的栅极和MOS管M9的栅极。The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12. The node CON is respectively connected to the drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9.

输出节点FN分别连接MOS管M7的栅极、MOS管M13的栅极和MOS管M15的栅极,输出端OP分别连接MOS管M7的漏极、MOS管M15的漏极和MOS管M9的源极。MOS管M7的源极接地,MOS管M13的漏极连接节点COP。The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole. The source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP.

输出节点FP分别连接MOS管M8的栅极、MOS管M14的栅极和MOS管M16的栅极,输出端ON分别连接MOS管M8的漏极、MOS管M16的漏极和MOS管M10的源极。MOS管M8的源极接地,MOS管M14的漏极连接节点CON。The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole. The source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON.

当输出节点FN输出的第一差分输出信号VFN为高电平,输出节点FP输出的第二差分输出信号VFP为低电平:MOS管M13和MOS管M15截止,MOS管M7导通,MOS管M8截止,MOS管M14和MOS管M16导通,输出端OP的第一输出信号VOP被拉低到地,输出端ON通过MOS管M16获得直流电源的输出电压VDD从而输出高电平的第二输出信号VON;节点CON通过MOS管M14从直流电源获得高电平,从而MOS管M11截止,MOS管M9源极通过MOS管M7接地从而导通,节点COP通过MOS管M9和MOS管M7接地呈现低电平,从而,MOS管M12导通对节点CON的高电平进行锁存,MOS管M10截止对输出端ON的第二输出信号VON进行锁存。此时,输出节点ON所在支路的MOS管M8断开,输出节点OP所在支路的MOS管M11、M13和M15断开,使得在直流电源和地之间没有电流通路,有利于降低再生锁存电路B的静态功耗。When the first differential output signal V FN output from the output node FN is at a high level, the second differential output signal V FP output from the output node FP is at a low level: the MOS transistor M13 and the MOS transistor M15 are turned off, and the MOS transistor M7 is turned on. The MOS transistor M8 is turned off, the MOS transistor M14 and the MOS transistor M16 are turned on, the first output signal V OP of the output terminal OP is pulled down to the ground, and the output terminal ON obtains the output voltage VDD of the DC power supply through the MOS transistor M16 to output a high level The second output signal V ON ; the node CON obtains a high level from the DC power supply through the MOS transistor M14, so that the MOS transistor M11 is cut off, the source of the MOS transistor M9 is grounded through the MOS transistor M7 to conduct, and the node COP is turned on through the MOS transistor M9 and the MOS transistor M14. The transistor M7 is grounded and presents a low level, thus, the MOS transistor M12 is turned on to latch the high level of the node CON, and the MOS transistor M10 is turned off to latch the second output signal V ON of the output terminal ON. At this time, the MOS transistor M8 of the branch where the output node ON is located is disconnected, and the MOS transistors M11, M13, and M15 of the branch where the output node OP is located are disconnected, so that there is no current path between the DC power supply and the ground, which is beneficial to reduce the regenerative lock Static power consumption of storage circuit B.

当输出节点FN输出的第一差分输出信号VFN为低电平,输出节点FP输出的第二差分输出信号VFP为高电平;MOS管M13和MOS管M15导通,MOS管M7截止,MOS管M8导通,MOS管M14和MOS管M16截止,从而,第二输出信号VON被MOS管M8拉低到地,第一输出信号VOP通过MOS管M15从直流电源获得高电平;节点COP通过MOS管M13从直流电源获得高电平,从而,MOS管M12截止,MOS管M10导通,节点CON通过MOS管M10和MOS管M8接地呈现低电平,从而,MOS管M11导通以对节点COP的高电平进行锁存,MOS管M9截止以对第一输出信号VOP进行锁存。此时,输出节点OP所在支路MOS管M7断开,输出节点ON所在支路M12、M14和M16断开,使得在直流电源和地之间没有电流通路,有利于降低再生锁存电路B的静态功耗。When the first differential output signal V FN output from the output node FN is at a low level, the second differential output signal V FP output from the output node FP is at a high level; the MOS transistor M13 and the MOS transistor M15 are turned on, and the MOS transistor M7 is turned off. The MOS transistor M8 is turned on, and the MOS transistor M14 and the MOS transistor M16 are turned off, so that the second output signal V ON is pulled down to the ground by the MOS transistor M8, and the first output signal V OP obtains a high level from the DC power supply through the MOS transistor M15; The node COP obtains a high level from the DC power supply through the MOS transistor M13, so that the MOS transistor M12 is turned off, the MOS transistor M10 is turned on, and the node CON is grounded to a low level through the MOS transistor M10 and the MOS transistor M8, so that the MOS transistor M11 is turned on To latch the high level of the node COP, the MOS transistor M9 is turned off to latch the first output signal V OP . At this time, the MOS transistor M7 of the branch where the output node OP is located is disconnected, and the branches M12, M14, and M16 of the output node ON are disconnected, so that there is no current path between the DC power supply and the ground, which is beneficial to reduce the regenerative latch circuit B. Static power.

本实施方式提供的高速低功耗的动态比较器根据时钟输入端输出的时钟信号CLK具有两种状态。The high-speed and low-power dynamic comparator provided in this embodiment has two states according to the clock signal CLK output from the clock input terminal.

第一状态下,时钟信号CLK为高电平,尾电流模块的PMOS管Mt截止以避免静态功耗,时钟复位模块中的MOS管M5和MOS管M6导通,第一差分输出信号VFN和第二差分输出信号VFP均被拉低到地进行复位;MOS管M7和MOS管M8截止,MOS管M13、MOS管M15、MOS管M14和MOS管M16均导通,第一输出信号VOP和第二输出信号VON分别通过MOS管M15和MOS管M16从直流电源获得高电平进行复位。In the first state, the clock signal CLK is at a high level, the PMOS transistor Mt of the tail current module is turned off to avoid static power consumption, the MOS transistors M5 and MOS transistors M6 in the clock reset module are turned on, and the first differential output signal V FN and The second differential output signal V FP is pulled down to ground for reset; MOS transistor M7 and MOS transistor M8 are cut off, MOS transistor M13, MOS transistor M15, MOS transistor M14 and MOS transistor M16 are all turned on, and the first output signal V OP and the second output signal V ON obtain a high level from the DC power supply through the MOS transistor M15 and the MOS transistor M16 respectively to reset.

第二状态下,时钟信号CLK为低电平,尾电流模块的PMOS管Mt导通,时钟复位模块中的MOS管M5和MOS管M6截止。此时,输出节点FN合成直流电源的输出电压VDD和第一差分输入信号VIP以输出第一差分输出信号VFN,输出节点FP合成直流电源的输出电压VDD和第二差分输入信号VIN以输出第二差分输出信号VFP。以VIP>VIN为例,此时第一差分输出信号VFN上升速度慢于第二差分输出信号VFP,随着第二差分输出信号VFP的不断升高,当其达到预设值,MOS管M3导通从而将第一差分输出信号VFN拉低到地,而MOS管M4维持截止状态,使得输出节点FP被完全充电,从而第二差分输出信号VFP呈现高电平,在交叉耦合反相器作用下,第二输出信号VON输出低电平,第一输出信号VOP输出高电平。In the second state, the clock signal CLK is at low level, the PMOS transistor Mt of the tail current module is turned on, and the MOS transistors M5 and MOS transistors M6 in the clock reset module are turned off. At this time, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V IP to output the first differential output signal V FN , and the output node FP synthesizes the output voltage VDD of the DC power supply and the second differential input signal V IN to form output the second differential output signal V FP . Taking V IP >V IN as an example, at this time the rising speed of the first differential output signal V FN is slower than that of the second differential output signal V FP , as the second differential output signal V FP continues to rise, when it reaches the preset value , the MOS transistor M3 is turned on so as to pull the first differential output signal V FN down to the ground, while the MOS transistor M4 remains in the off state, so that the output node FP is fully charged, so that the second differential output signal V FP presents a high level, at Under the action of the cross-coupled inverter, the second output signal V ON outputs a low level, and the first output signal V OP outputs a high level.

反之,当VIN>VIP,此时第二差分输出信号VFP上升速度慢于第一差分输出信号VFN,随着第一差分输出信号VFN的不断升高,当其达到预设值,MOS管M4导通从而将第二差分输出信号VFP拉低到地,而MOS管M3维持截止状态,使得输出节点FN被完全充电,从而第一差分输出信号VFN呈现高电平,在交叉耦合反相器作用下,第一输出信号VOP输出低电平,第二输出信号VON输出高电平。Conversely, when V IN >V IP , the rising speed of the second differential output signal V FP is slower than that of the first differential output signal V FN , as the first differential output signal V FN continues to rise, when it reaches the preset value , the MOS transistor M4 is turned on so as to pull the second differential output signal V FP down to the ground, while the MOS transistor M3 maintains an off state, so that the output node FN is fully charged, so that the first differential output signal V FN presents a high level, at Under the action of the cross-coupled inverter, the first output signal V OP outputs a low level, and the second output signal V ON outputs a high level.

本实施方式中,前置放大电路A工作在动态模式下,不存在静态功耗;而当再生锁存电路B工作时,直流电源和地之间没有电流通路,故而,再生锁存电路B的静态功耗可忽略不计。In this embodiment, the preamplifier circuit A works in the dynamic mode, and there is no static power consumption; and when the regenerative latch circuit B is working, there is no current path between the DC power supply and the ground, so the regenerative latch circuit B Static power consumption is negligible.

以下结合一个具体的来对本发明进行验证。本实施例利用40nm CMOS工艺实现,直流电源的输出电压VDD=1.1V,整个动态锁存器在5GHz高速时钟下功耗仅为270μW,且占用面积仅为60.75μm2,基于上述电路进行了实验。The present invention is verified below in conjunction with a specific one. This embodiment is realized by 40nm CMOS technology, the output voltage of the DC power supply is VDD=1.1V, the power consumption of the entire dynamic latch is only 270 μW under the 5GHz high-speed clock, and the occupied area is only 60.75 μm2. Experiments are carried out based on the above circuit.

参见图7,图中所示为本发明实施例中提供的一种高速低功耗的动态比较器的瞬态仿真图,比较器可工作到5GHz,每次转换消耗能量仅为54fJ,同时延迟时间缩小到55ps,可见,本发明提供的动态比较器可在高速应用下快速实现低功耗动态锁存功能。Referring to Fig. 7, it is a transient simulation diagram of a high-speed and low-power dynamic comparator provided in the embodiment of the present invention, the comparator can work up to 5GHz, and the energy consumption per conversion is only 54fJ, while delay The time is reduced to 55 ps. It can be seen that the dynamic comparator provided by the present invention can quickly realize the low-power dynamic latch function under high-speed applications.

本实施方式中分别采用PMOS管输入的前置放大电路和NMOS管输入的再生锁存电路,且两部分电路均只有三层堆叠的MOS管,有利于在低电源电压下的高速工作;不同于传统双尾动态比较器的是,本发明只需要单个输入时钟信号就可完成复位和比较过程,不仅简化了比较器的时序,而且有效节省了面积和功耗,实现了一个具有高能效的高速动态比较器。In this embodiment, the preamplifier circuit with PMOS tube input and the regenerative latch circuit with NMOS tube input are respectively used, and both parts of the circuit have only three-layer stacked MOS tubes, which is conducive to high-speed operation under low power supply voltage; different from Compared with the traditional double-tailed dynamic comparator, the present invention only needs a single input clock signal to complete the reset and comparison process, which not only simplifies the timing of the comparator, but also effectively saves area and power consumption, and realizes a high-speed high-speed comparator with high energy efficiency. dynamic comparator.

以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,根据本发明的技术方案及其发明构思加以等同替换或改变,都应涵盖在本发明的保护范围之内。The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any person familiar with the technical field within the technical scope disclosed in the present invention, according to the technical solution of the present invention Any equivalent replacement or change of the inventive concepts thereof shall fall within the protection scope of the present invention.

Claims (4)

1.一种高速低功耗的动态比较器,其特征在于,包括前置放大电路A和再生锁存电路B;1. A dynamic comparator with low power consumption at high speed, is characterized in that, comprises preamplifier circuit A and regenerative latch circuit B; 前置放大电路A包括时钟输入端、第一差分信号输入端、第二差分信号输入端、输出节点FN和输出节点FP;时钟输入端用于输入时钟信号CLK,第一差分信号输入端和第二差分信号输入端分别用于接入第一差分输入信号VIP和第二差分输入信号VINThe preamplifier circuit A includes a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN and an output node FP; the clock input terminal is used to input a clock signal CLK, the first differential signal input terminal and the second differential signal input terminal The two differential signal input terminals are respectively used to access the first differential input signal V IP and the second differential input signal V IN ; 前置放大电路A连接直流电源,输出节点FN合成直流电源的输出电压VDD和第一差分输入信号VIP以输出第一差分输出信号VFN,输出节点FP合成直流电源的输出电压VDD和第二差分输入信号VIN以输出第二差分输出信号VFP;再生锁存电路B与前置放大电路A的输出节点FN和输出节点FP连接,其可用于对第一差分输出信号VFN和第二差分输出信号VFP进行锁存,并输出第一输出信号VOP和第二输出信号VONThe preamplifier circuit A is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V IP to output the first differential output signal V FN , and the output node FP synthesizes the output voltage VDD of the DC power supply and the second The differential input signal V IN is used to output the second differential output signal V FP ; the regenerative latch circuit B is connected to the output node FN and the output node FP of the preamplifier circuit A, which can be used to output the first differential output signal V FN and the second Latching the differential output signal V FP and outputting the first output signal V OP and the second output signal V ON ; 所述高速低功耗的动态比较器根据时钟输入端输入的时钟信号CLK具有两种状态:第一状态下,第一差分输出信号VFN、第二差分输出信号VFP、第一输出信号VOP和第二输出信号VON均处于复位状态;第二状态下,再生锁存电路B对第一差分输出信号VFN和第二差分输出信号VFP进行锁存,并输出第一输出信号VOP和第二输出信号VONThe high-speed and low-power dynamic comparator has two states according to the clock signal CLK input from the clock input terminal: in the first state, the first differential output signal V FN , the second differential output signal V FP , the first output signal V Both OP and the second output signal V ON are in the reset state; in the second state, the regenerative latch circuit B latches the first differential output signal V FN and the second differential output signal V FP , and outputs the first output signal V OP and the second output signal V ON ; 前置放大电路A包括:输入模块、时钟复位模块、交叉耦合模块和尾电流模块;The preamplifier circuit A includes: an input module, a clock reset module, a cross-coupling module and a tail current module; 输出节点FN和输出节点FP通过输入模块分别连接第一差分信号输入端和第二差分信号输入端;输出节点FN和输出节点FP通过串联的输入模块和尾电流模块连接直流电源,尾电流模块与时钟输入端连接并由时钟信号CLK控制其通断;第一差分输出信号VFN可通过交叉耦合模块控制输出节点FP对地导通或断开以控制第二差分输出信号VFP拉低到地,第二差分输出信号VFP可通过交叉耦合模块控制输出节点FN对地导通或断开以控制第一差分输出信号VFN拉低到地;The output node FN and the output node FP are respectively connected to the first differential signal input terminal and the second differential signal input terminal through the input module; the output node FN and the output node FP are connected to the DC power supply through the serial input module and the tail current module, and the tail current module and The clock input terminal is connected and controlled by the clock signal CLK; the first differential output signal V FN can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal V FP to be pulled down to the ground , the second differential output signal V FP can control the output node FN to be turned on or off to the ground through the cross-coupling module to control the first differential output signal V FN to be pulled down to the ground; 输出节点FN和输出节点FP均通过时钟复位模块接地,时钟复位模块与时钟输入端连接并由时钟信号CLK控制其通断;Both the output node FN and the output node FP are grounded through the clock reset module, and the clock reset module is connected to the clock input terminal and controlled by the clock signal CLK to turn it on and off; 第一状态下,尾电流模块断路,时钟复位模块导通,第一差分输出信号VFN和第二差分输出信号VFP复位;第二状态下,尾电流模块导通,时钟复位模块断路,第一差分输出信号VFN根据直流电源的输出电压VDD和第一差分输入信号VIP升降,第二差分输出信号VFP根据直流电源的输出电压VDD和第二差分输入信号VIN升降;In the first state, the tail current module is turned off, the clock reset module is turned on, and the first differential output signal V FN and the second differential output signal V FP are reset; in the second state, the tail current module is turned on, the clock reset module is turned off, and the second differential output signal V FN is reset. A differential output signal V FN rises and falls according to the output voltage VDD of the DC power supply and the first differential input signal V IP , and the second differential output signal V FP rises and falls according to the output voltage VDD of the DC power supply and the second differential input signal V IN ; 交叉耦合模块包括第一通断元件和第二通断元件,输出节点FN和输出节点FP分别通过第一通断元件和第二通断元件接地,输出节点FN与第二通断元件连接并通过第一差分输出信号VFN控制第二通断元件工作状态,输出节点FP与第一通断元件连接并通过第二差分输出信号VFP控制第一通断元件工作状态;The cross-coupling module includes a first on-off element and a second on-off element, the output node FN and the output node FP are respectively grounded through the first on-off element and the second on-off element, and the output node FN is connected to the second on-off element and passed through The first differential output signal V FN controls the working state of the second on-off element, the output node FP is connected to the first on-off element and controls the working state of the first on-off element through the second differential output signal V FP ; 尾电流模块采用PMOS管Mt,其源极连接直流电源,其栅极连接时钟输入端,其漏极连接输入模块;The tail current module adopts PMOS tube Mt, its source is connected to the DC power supply, its gate is connected to the clock input terminal, and its drain is connected to the input module; 再生锁存电路B包括:第一控制模块、第二控制模块和交叉耦合反相器;第一控制模块、第二控制模块和交叉耦合反相器均与直流电源连接;输出节点FN和输出节点FP分别通过第一控制模块和第二控制模块连接交叉耦合反相器,第一控制模块和交叉耦合反相器之间设有输出端OP用于输出第一输出信号VOP,第二控制模块和交叉耦合反相器之间设有输出端ON用于输出第二输出信号VON;再生锁存电路B为完全对称结构;The regenerative latch circuit B includes: a first control module, a second control module and a cross-coupled inverter; the first control module, the second control module and the cross-coupled inverter are all connected to a DC power supply; the output node FN and the output node FP is respectively connected to the cross-coupled inverter through the first control module and the second control module, an output terminal OP is provided between the first control module and the cross-coupled inverter for outputting the first output signal V OP , and the second control module An output terminal ON is provided between the cross-coupled inverter and the second output signal V ON ; the regenerative latch circuit B has a completely symmetrical structure; 第一控制模块包括MOS管M7、MOS管M13和MOS管M15,第二控制模块包括MOS管M8、MOS管M14和MOS管M16,交叉耦合反相器包括MOS管M9、MOS管M10、MOS管M11和MOS管M12;其中,MOS管M7、MOS管M8、MOS管M9和MOS管M10均为NMOS管;MOS管M11和MOS管M12、MOS管M13、MOS管M14、MOS管M15、MOS管M16为PMOS管,且源极均连接直流电源;The first control module includes MOS transistor M7, MOS transistor M13 and MOS transistor M15, the second control module includes MOS transistor M8, MOS transistor M14 and MOS transistor M16, and the cross-coupled inverter includes MOS transistor M9, MOS transistor M10, MOS transistor M11 and MOS tube M12; Among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11 and MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16 is a PMOS tube, and the source is connected to a DC power supply; 交叉耦合反相器中设有节点COP和节点CON,节点COP分别连接MOS管M11的漏极、MOS管M9的漏极、MOS管M10的栅极和MOS管M12的栅极;节点CON分别连接MOS管M12的漏极、MOS管M10的漏极、MOS管M11的栅极和MOS管M9的栅极;The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12; the node CON is respectively connected to The drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9; 输出节点FN分别连接MOS管M7的栅极、MOS管M13的栅极和MOS管M15的栅极,输出端OP分别连接MOS管M7的漏极、MOS管M15的漏极和MOS管M9的源极;MOS管M7的源极接地,MOS管M13的漏极连接节点COP;The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole; the source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP; 输出节点FP分别连接MOS管M8的栅极、MOS管M14的栅极和MOS管M16的栅极,输出端ON分别连接MOS管M8的漏极、MOS管M16的漏极和MOS管M10的源极;MOS管M8的源极接地,MOS管M14的漏极连接节点CON。The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole; the source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON. 2.如权利要求1所述的高速低功耗的动态比较器,其特征在于,输入模块包括MOS管M1和MOS管M2,交叉耦合模块包括MOS管M3和MOS管M4,第一通断元件为MOS管M5,第二通断元件为MOS管M6;2. The high-speed and low-power dynamic comparator according to claim 1, wherein the input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 and a MOS transistor M4, and the first on-off element is a MOS transistor M5, and the second on-off element is a MOS transistor M6; MOS管M1的栅极和MOS管M2的栅极分别作为第一差分信号输入端和第二差分信号输入端;输出节点FN和输出节点FP分别通过MOS管M1和和MOS管M2连接PMOS管Mt的漏极,并分别通过MOS管M5和MOS管M6接地,MOS管M5的栅极和MOS管M6的栅极均与时钟输入端连接;输出节点FN和输出节点FP分别通过MOS管M3和MOS管M4接地,输出节点FN和输出节点FP分别连接MOS管M4的栅极和MOS管M3的栅极。The gate of the MOS transistor M1 and the gate of the MOS transistor M2 are respectively used as the first differential signal input terminal and the second differential signal input terminal; the output node FN and the output node FP are respectively connected to the PMOS transistor Mt through the MOS transistor M1 and the MOS transistor M2 The drain of the MOS transistor M5 and the MOS transistor M6 are connected to the ground respectively, and the gate of the MOS transistor M5 and the gate of the MOS transistor M6 are connected to the clock input terminal; the output node FN and the output node FP are respectively connected to the MOS transistor M3 and the MOS The transistor M4 is grounded, and the output node FN and the output node FP are connected to the gate of the MOS transistor M4 and the gate of the MOS transistor M3 respectively. 3.如权利要求2所述的高速低功耗的动态比较器,其特征在于,MOS管M1和MOS管M2为PMOS管,MOS管M3、MOS管M4、MOS管M5和MOS管M6为NMOS管。3. The dynamic comparator with high speed and low power consumption as claimed in claim 2, wherein MOS transistor M1 and MOS transistor M2 are PMOS transistors, and MOS transistor M3, MOS transistor M4, MOS transistor M5 and MOS transistor M6 are NMOS transistors. Tube. 4.如权利要求1所述的高速低功耗的动态比较器,其特征在于,第一状态下,时钟信号CLK为高电平,第二状态下,时钟信号CLK为低电平。4 . The high-speed and low-power dynamic comparator according to claim 1 , wherein in the first state, the clock signal CLK is at a high level, and in the second state, the clock signal CLK is at a low level.
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