CN105680834B - A kind of dynamic comparer of high-speed low-power-consumption - Google Patents

Abstract

The invention discloses a dynamic comparator with high speed and low power consumption, which includes a preamplifier circuit and a regenerative latch circuit; the preamplifier circuit includes a clock output terminal, a first differential signal input terminal, a second differential signal input terminal, an output Node FN and output node FP; the preamplifier circuit is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal to output the first differential output signal, and the output node FP synthesizes the output voltage VDD of the DC power supply and The second differential input signal to output the second differential output signal; the regenerative latch circuit is connected to the output node FN and the output node FP of the preamplifier circuit, which can be used to latch the first differential output signal and the second differential output signal , and output the first output signal and the second output signal. The dynamic comparator provided by the invention can quickly realize the low power consumption dynamic latch function under high-speed application.

Description

A high-speed and low-power dynamic comparator

technical field

The invention relates to the technical field of analog integrated circuits, in particular to a dynamic comparator with high speed and low power consumption.

Background technique

Comparator (Comparator) is an important component module of many integrated circuits (IC), such as analog-to-digital converter (ADC), transconductance amplifier (OTA), voltage reference source (VR) and clock data recovery circuit (CDR), through detection The differential input voltage produces a corresponding output that displays input voltage information with a larger magnitude. In modern communication systems, with the ever-increasing demand for lighter weight and smaller size in portable devices, comparators need to achieve high-speed operation with low power consumption and low cost. However, with the reduction of advanced CMOS process size (to 40nm and 28nm, even smaller), the power supply voltage of the core circuit is also reduced, but the threshold voltage of the MOS tube cannot be reduced in the same proportion, which limits the comparator The common-mode input range; more importantly, in order to achieve high-speed operation, the size of the MOS tube in the comparator needs to be larger to compensate for the impact of the continuous reduction of the power supply voltage, which will bring more additional chip area occupancy and power consumption.

The structure of a traditional static comparator is shown in Figure 1. The structure includes a pair of differential input transistors, a current mirror load and a current source, which will continuously compare the two input signals without any clock signal to control the timing or enable, so the static comparator can generally be used when the clock cannot be provided signal occasions. However, the static comparator will face the problem of undershoot and overshoot; moreover, since the tail current source of this structure is always on, this will bring a large static power consumption, especially in high-speed applications.

The structure of a traditional static latch comparator is shown in Figure 2. This structure introduces the latch signal latch on the basis of the static comparator. In the reset phase (the latch signal is at low level, and the two latch transistors M5a and M5b are turned on), the differential output signals VOP and VON are pulled down to Ground, four MOS transistors M1a, M1b, M2a and M2b form a pre-amplifier, and mirror the current to the output terminals VOP and VON through M3a and M3b respectively; on the other hand, when the latch signal becomes high, both M5a and M5b are disconnected, and the current The current passing through M3a and M3b will change the output voltage and carry out the regeneration process. Static latching comparators exhibit low kickback noise due to isolation between the drains of the differential input transistors (M1a and M1b) and the output terminals (VOP and VON). However, the pure static power consumption still makes this structure unsuitable for high-speed applications; in addition, M3a/M4a and M3b/M4b operating in the current-limited region will slow down the regeneration process of the comparator of this structure.

The structure of a traditional dynamic comparator is shown in Figure 3. This structure is widely used in high-speed ADCs. Before the comparison operation, the CLK signal is at low level, the comparator performs a reset operation, the clock control tube Mt is disconnected, and the differential output signals VOP and VON are respectively pulled by the pre-charge tubes M7 and M8. High to the power supply voltage VDD; when the CLK signal becomes high level, M7 and M8 are disconnected, and Mt is turned on. In the case of VIP>VIN, all latch tubes M3, M4, M5 and M6 start the regeneration process, because The input tube M1 is turned on earlier than M2, and the output terminal VON is pulled down to the voltage VDD-|Vtp| earlier than VOP, so M6 is turned on before M5. At this time, VOP-VON is the amplified input differential voltage VIP-VIN ; Finally, the output terminal VOP is pulled down to the ground, and VON is pulled up to the power supply voltage VDD; in the case of VIP<VIN, the comparator works vice versa. The dynamic comparator combines strong positive feedback to perform fast comparisons while having good reliability against noise and mismatch; in addition, once the comparison process is completed, the current flow is automatically stopped, that is, there is no static power consumption. However, since the dynamic comparator stacks more MOS transistors, a large voltage margin is required to obtain a suitable delay time, which will cause problems in the low-voltage deep submicron CMOS process; in addition, Mt mainly works in the triode region , causing the tail current to depend on the input common-mode voltage, which can be detrimental to the regeneration process.

The structure of a traditional double-tailed dynamic comparator is shown in Figure 4. As an alternative to the dynamic comparator, this structure includes an input stage and a latch stage with a pair of differentially clocked tail current transistors. When CLK is at a low level, the comparator starts to reset, and M3 and M4 precharge the nodes FN and FP respectively; when CLK is at a high level, the comparator starts to regenerate, and the two tail current transistors Mt1 and Mt2 are both turned on, and the voltages VFN and VFP begins to decrease at the rate IMt1/CFN(P), so an input-dependent differential voltage △VFN(P) will build up; the intermediate stage consisting of M11 and M12 delivers the voltage △VFN(P) to the cross-coupled inverting devices (including M7, M8, M9, and M10), also provide good isolation between input and output, thus reducing kickback noise. The double-tailed dynamic comparator has fewer stacked MOS transistors, so it can work at a lower power supply voltage; moreover, this structure can use a large current in the latch stage to complete fast latching, and use a small current in the input stage to ensure low out of tune. However, the input stage of this structure still requires a high common-mode voltage, which can cause trouble at low supply voltages; in addition, a pair of differential clock signals is required in the dual-tailed dynamic comparator, which brings additional area and Power consumption and possible timing issues.

Contents of the invention

Based on the technical problems existing in the background technology, the present invention proposes a dynamic comparator with high speed and low power consumption.

A high-speed and low-power dynamic comparator proposed by the present invention includes a preamplifier circuit and a regenerative latch circuit;

The preamplifier circuit includes a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN and an output node FP; the clock input terminal is used to input a clock signal CLK, and the first differential signal input terminal and the second differential signal input terminal The differential signal input terminals are respectively used to access the first differential input signal and the second differential input signal;

The preamplifier circuit is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal to output the first differential output signal, and the output node FP synthesizes the output voltage VDD of the DC power supply and the second differential input signal to output The second differential output signal; the regenerative latch circuit is connected to the output node FN and the output node FP of the preamplifier circuit, which can be used to latch the first differential output signal and the second differential output signal, and output the first output signal and a second output signal;

The high-speed and low-power dynamic comparator has two states according to the clock signal CLK output by the clock input terminal: in the first state, the first differential output signal, the second differential output signal, the first output signal and the second output signal Both are in the reset state; in the second state, the regenerative latch circuit latches the first differential output signal and the second differential output signal, and outputs the first output signal and the second output signal.

Preferably, the preamplification circuit includes: an input module, a clock reset module, a cross-coupling module and a tail current module;

The output node FN and the output node FP are respectively connected to the first differential signal input terminal and the second differential signal input terminal through the input module; the output node FN and the output node FP are connected to the DC power supply through the serial input module and the tail current module, and the tail current module and The clock input terminal is connected and controlled by the clock signal CLK; the first differential output signal can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal to be pulled down to the ground, and the second differential output signal The output signal can control the output node FN to be turned on or off to the ground through the cross-coupling module to control the first differential output signal to be pulled down to the ground;

Both the output node FN and the output node FP are grounded through the clock reset module, and the clock reset module is connected to the clock input terminal and controlled by the clock signal CLK to turn it on and off;

In the first state, the tail current module is turned off, the clock reset module is turned on, and the first differential output signal and the second differential output signal are reset; in the second state, the tail current module is turned on, the clock reset module is turned off, and the first differential output signal The second differential output signal rises and falls according to the output voltage VDD of the DC power supply and the first differential input signal, and the second differential output signal rises and falls according to the output voltage VDD of the DC power supply and the second differential input signal.

Preferably, the cross-coupling module includes a first on-off element and a second on-off element, the output node FN and the output node FP are respectively grounded through the first on-off element and the second on-off element, and the output node FN and the second on-off element connected to and control the working state of the second on-off element through the first differential output signal, the output node FP is connected to the first on-off element and controls the working state of the first on-off element through the second differential output signal.

Preferably, the tail current module adopts a PMOS transistor Mt, its source is connected to a DC power supply, its gate is connected to a clock input terminal, and its drain is connected to an input module.

Preferably, the input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 and a MOS transistor M4, the first on-off element is a MOS transistor M5, and the second on-off element is a MOS transistor M6;

The gate of the MOS transistor M1 and the gate of the MOS transistor M2 are respectively used as the first differential signal input terminal and the second differential signal input terminal; the output node FN and the output node FP are respectively connected to the PMOS transistor Mt through the MOS transistor M1 and the MOS transistor M2 The drain of the MOS transistor M5 and the MOS transistor M6 are connected to the ground respectively, and the gate of the MOS transistor M5 and the gate of the MOS transistor M6 are connected to the clock input terminal; the output node FN and the output node FP are respectively connected to the MOS transistor M3 and the MOS The transistor M4 is grounded, and the output node FN and the output node FP are connected to the gate of the MOS transistor M4 and the gate of the MOS transistor M3 respectively.

Preferably, the MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3, the MOS transistor M4, the MOS transistor M5 and the MOS transistor M6 are NMOS transistors.

Preferably, in the first state, the clock signal CLK is at high level, and in the second state, the clock signal CLK is at low level.

Preferably, the regenerative latch circuit includes: a first control module, a second control module and a cross-coupled inverter; the first control module, the second control module and the cross-coupled inverter are all connected to a DC power supply; the output nodes FN and The output node FP is respectively connected to the cross-coupled inverter through the first control module and the second control module, an output terminal OP is provided between the first control module and the cross-coupled inverter for outputting the first output signal, and the second control module An output terminal ON is provided between the cross-coupled inverter and the second output signal; the regenerative latch circuit has a completely symmetrical structure.

Preferably, the first control module includes a MOS transistor M7, a MOS transistor M13, and a MOS transistor M15, the second control module includes a MOS transistor M8, a MOS transistor M14, and a MOS transistor M16, and the cross-coupled inverter includes a MOS transistor M9, a MOS transistor M10 , MOS tube M11 and MOS tube M12; among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11 and MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15 , MOS tube M16 is a PMOS tube, and the source is connected to a DC power supply;

The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12; the node CON is respectively connected to The drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9;

The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole; the source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP;

The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole; the source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON.

In the present invention, the preamplifier circuit A works in a dynamic mode, and there is no static power consumption; and when the regenerative latch circuit B is working, there is no current path between the DC power supply and the ground, so the static power of the regenerative latch circuit B Power consumption is negligible.

In addition, compared with the traditional dynamic comparator, the present invention respectively adopts the preamplifier circuit with PMOS tube input and the regenerative latch circuit with NMOS tube input, and both parts of the circuit have only three-layer stacked MOS tubes, which is beneficial to low power supply High-speed operation under voltage; different from the traditional double-tailed dynamic comparator, the present invention only needs a single input clock signal to complete the reset and comparison process, which not only simplifies the timing of the comparator, but also effectively saves area and power consumption. A high-speed dynamic comparator with high energy efficiency is implemented.

Description of drawings

Fig. 1 is the structural representation of static comparator;

Fig. 2 is a structural schematic diagram of a static latch comparator;

Fig. 3 is a structural schematic diagram of a dynamic comparator;

Fig. 4 is the structural representation of double tail dynamic comparator;

FIG. 5 is a schematic structural diagram of a high-speed and low-power dynamic comparator provided by the present invention;

FIG. 6 is a circuit diagram of a high-speed and low-power dynamic comparator provided in an embodiment of the present invention;

FIG. 7 is a transient simulation diagram of a high-speed and low-power dynamic comparator provided in an embodiment of the present invention.

Detailed ways

Referring to FIG. 5 , a high-speed and low-power dynamic comparator proposed by the present invention includes a preamplifier circuit A and a regenerative latch circuit B.

Referring to FIG. 6, the preamplifier circuit A includes: a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN, an output node FP, an input module, a clock reset module, a cross-coupling module and a tail current module. The clock input terminal is used to input the clock signal CLK, and the first differential signal input terminal and the second differential signal input terminal are respectively used to receive the first differential input signal V _IP and the second differential input signal V _IN . The input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 as a first on-off element and a MOS transistor M4 as a second on-off element, and the clock reset module includes a MOS transistor M5 and a MOS transistor M6. The MOS transistor M1 and the MOS transistor M2 are PMOS transistors, and the MOS transistor M3 , the MOS transistor M4 , the MOS transistor M5 and the MOS transistor M6 are NMOS transistors.

The tail current module adopts a PMOS transistor Mt, its source is connected to the DC power supply, its gate is connected to the clock input terminal to receive the clock signal CLK, and its drain is respectively connected to the source of the MOS transistor M1 and the source of the MOS transistor M2. The gate of the MOS transistor M1 is used as the first differential signal input terminal for receiving the first differential input signal V _IP , and the gate of the MOS transistor M2 is used as the second differential signal input terminal for receiving the second differential input signal V _IN .

The output node FN is respectively connected to the drain of the MOS transistor M1, the drain of the MOS transistor M3, the drain of the MOS transistor M5 and the gate of the MOS transistor M4, the source of the MOS transistor M3 and the source of the MOS transistor M5 are grounded, and the MOS The gate of the transistor M5 is connected to the clock input terminal to receive the clock signal CLK. The output node FP is respectively connected to the drain of the MOS transistor M2, the drain of the MOS transistor M4, the drain of the MOS transistor M6 and the gate of the MOS transistor M3, the source of the MOS transistor M4 and the source of the MOS transistor M6 are both grounded, and the MOS The gate of the transistor M6 is connected to the clock input terminal to receive the clock signal CLK.

The clock signal can control the on-off of the PMOS transistor Mt, the MOS transistor M5 and the MOS transistor M6. When the PMOS transistor Mt is turned on, the DC power supply supplies power to the input module, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V _IP to output the first differential output signal V _FN , and the output node FP synthesizes the output of the DC power supply voltage VDD and the second differential input signal V _IN to output a second differential output signal V _FP . At the same time, the first differential output signal V _FN can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal V _FP to be pulled down to the ground, and the second differential output signal V _FP can be passed through the cross-coupling The module controls the output node FN to be turned on or off to the ground to control the first differential output signal V _FN to be pulled down to the ground.

Specifically, when the clock signal CLK is at a high level, the PMOS transistor Mt is turned off, the MOS transistor M5 and the MOS transistor M6 in the clock reset module are both turned on, and the output node FN and the output node FP are grounded through the MOS transistor M5 and the MOS transistor M6 respectively. , the first differential output signal V _FN and the second differential output signal V _FP are both pulled down to the ground to realize reset; when the clock signal CLK is low level, both the MOS transistor M5 and the MOS transistor M6 are cut off, and the PMOS transistor Mt is turned on. In the input module, the source and gate of the MOS transistor M1 obtain the output voltage VDD of the DC power supply and the first differential input signal V _IP respectively, and the drain of the MOS transistor M1 is connected to the output node FN to output the first differential output signal V _FN , The source and gate of the MOS transistor M2 respectively obtain the output voltage VDD of the DC power supply and the second differential input signal V _IN , and the drain of the MOS transistor M2 is connected to the output node FP to output the second differential output signal V _FP . When the first differential input signal V _IP first rises to a certain value, the MOS transistor M4 is turned on to pull the second differential output signal V _FP down to the ground; otherwise, when the second differential output signal V _FP first rises to a certain value , the MOS transistor M3 is turned on so as to pull down the first differential input signal V _IP to ground.

Referring to Fig. 6, in this embodiment, the regenerative latch circuit B is a completely symmetrical structure, which is connected to the output node FN and the output node FP of the preamplifier circuit A, and it can be used for the first differential output signal V _FN and the second The differential output signal V _FP is latched, and outputs a first output signal V _OP and a second output signal V _ON . The regenerative latch circuit B includes: a first control module, a second control module and a cross-coupled inverter.

The first control module includes MOS transistor M7, MOS transistor M13 and MOS transistor M15, the second control module includes MOS transistor M8, MOS transistor M14 and MOS transistor M16, and the cross-coupled inverter includes MOS transistor M9, MOS transistor M10, MOS transistor M11 and MOS tube M12. Among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, and MOS tube M16 are PMOS tubes, and The sources are all connected to a DC power supply.

The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12. The node CON is respectively connected to the drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9.

The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole. The source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP.

The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole. The source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON.

When the first differential output signal V _FN output from the output node FN is at a high level, the second differential output signal V _FP output from the output node FP is at a low level: the MOS transistor M13 and the MOS transistor M15 are turned off, and the MOS transistor M7 is turned on. The MOS transistor M8 is turned off, the MOS transistor M14 and the MOS transistor M16 are turned on, the first output signal V _OP of the output terminal OP is pulled down to the ground, and the output terminal ON obtains the output voltage VDD of the DC power supply through the MOS transistor M16 to output a high level The second output signal V _ON ; the node CON obtains a high level from the DC power supply through the MOS transistor M14, so that the MOS transistor M11 is cut off, the source of the MOS transistor M9 is grounded through the MOS transistor M7 to conduct, and the node COP is turned on through the MOS transistor M9 and the MOS transistor M14. The transistor M7 is grounded and presents a low level, thus, the MOS transistor M12 is turned on to latch the high level of the node CON, and the MOS transistor M10 is turned off to latch the second output signal V _ON of the output terminal ON. At this time, the MOS transistor M8 of the branch where the output node ON is located is disconnected, and the MOS transistors M11, M13, and M15 of the branch where the output node OP is located are disconnected, so that there is no current path between the DC power supply and the ground, which is beneficial to reduce the regenerative lock Static power consumption of storage circuit B.

When the first differential output signal V _FN output from the output node FN is at a low level, the second differential output signal V _FP output from the output node FP is at a high level; the MOS transistor M13 and the MOS transistor M15 are turned on, and the MOS transistor M7 is turned off. The MOS transistor M8 is turned on, and the MOS transistor M14 and the MOS transistor M16 are turned off, so that the second output signal V _ON is pulled down to the ground by the MOS transistor M8, and the first output signal V _OP obtains a high level from the DC power supply through the MOS transistor M15; The node COP obtains a high level from the DC power supply through the MOS transistor M13, so that the MOS transistor M12 is turned off, the MOS transistor M10 is turned on, and the node CON is grounded to a low level through the MOS transistor M10 and the MOS transistor M8, so that the MOS transistor M11 is turned on To latch the high level of the node COP, the MOS transistor M9 is turned off to latch the first output signal V _OP . At this time, the MOS transistor M7 of the branch where the output node OP is located is disconnected, and the branches M12, M14, and M16 of the output node ON are disconnected, so that there is no current path between the DC power supply and the ground, which is beneficial to reduce the regenerative latch circuit B. Static power.

The high-speed and low-power dynamic comparator provided in this embodiment has two states according to the clock signal CLK output from the clock input terminal.

In the first state, the clock signal CLK is at a high level, the PMOS transistor Mt of the tail current module is turned off to avoid static power consumption, the MOS transistors M5 and MOS transistors M6 in the clock reset module are turned on, and the first differential output signal V _FN and The second differential output signal V _FP is pulled down to ground for reset; MOS transistor M7 and MOS transistor M8 are cut off, MOS transistor M13, MOS transistor M15, MOS transistor M14 and MOS transistor M16 are all turned on, and the first output signal V _OP and the second output signal V _ON obtain a high level from the DC power supply through the MOS transistor M15 and the MOS transistor M16 respectively to reset.

In the second state, the clock signal CLK is at low level, the PMOS transistor Mt of the tail current module is turned on, and the MOS transistors M5 and MOS transistors M6 in the clock reset module are turned off. At this time, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V _IP to output the first differential output signal V _FN , and the output node FP synthesizes the output voltage VDD of the DC power supply and the second differential input signal V _IN to form output the second differential output signal V _FP . Taking V _IP >V _IN as an example, at this time the rising speed of the first differential output signal V _FN is slower than that of the second differential output signal V _FP , as the second differential output signal V _FP continues to rise, when it reaches the preset value , the MOS transistor M3 is turned on so as to pull the first differential output signal V _FN down to the ground, while the MOS transistor M4 remains in the off state, so that the output node FP is fully charged, so that the second differential output signal V _FP presents a high level, at Under the action of the cross-coupled inverter, the second output signal V _ON outputs a low level, and the first output signal V _OP outputs a high level.

Conversely, when V _IN >V _IP , the rising speed of the second differential output signal V _FP is slower than that of the first differential output signal V _FN , as the first differential output signal V _FN continues to rise, when it reaches the preset value , the MOS transistor M4 is turned on so as to pull the second differential output signal V _FP down to the ground, while the MOS transistor M3 maintains an off state, so that the output node FN is fully charged, so that the first differential output signal V _FN presents a high level, at Under the action of the cross-coupled inverter, the first output signal V _OP outputs a low level, and the second output signal V _ON outputs a high level.

In this embodiment, the preamplifier circuit A works in the dynamic mode, and there is no static power consumption; and when the regenerative latch circuit B is working, there is no current path between the DC power supply and the ground, so the regenerative latch circuit B Static power consumption is negligible.

The present invention is verified below in conjunction with a specific one. This embodiment is realized by 40nm CMOS technology, the output voltage of the DC power supply is VDD=1.1V, the power consumption of the entire dynamic latch is only 270 μW under the 5GHz high-speed clock, and the occupied area is only 60.75 μm2. Experiments are carried out based on the above circuit.

Referring to Fig. 7, it is a transient simulation diagram of a high-speed and low-power dynamic comparator provided in the embodiment of the present invention, the comparator can work up to 5GHz, and the energy consumption per conversion is only 54fJ, while delay The time is reduced to 55 ps. It can be seen that the dynamic comparator provided by the present invention can quickly realize the low-power dynamic latch function under high-speed applications.

In this embodiment, the preamplifier circuit with PMOS tube input and the regenerative latch circuit with NMOS tube input are respectively used, and both parts of the circuit have only three-layer stacked MOS tubes, which is conducive to high-speed operation under low power supply voltage; different from Compared with the traditional double-tailed dynamic comparator, the present invention only needs a single input clock signal to complete the reset and comparison process, which not only simplifies the timing of the comparator, but also effectively saves area and power consumption, and realizes a high-speed high-speed comparator with high energy efficiency. dynamic comparator.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any person familiar with the technical field within the technical scope disclosed in the present invention, according to the technical solution of the present invention Any equivalent replacement or change of the inventive concepts thereof shall fall within the protection scope of the present invention.

Claims (4)

1. A dynamic comparator with low power consumption at high speed, is characterized in that, comprises preamplifier circuit A and regenerative latch circuit B; The preamplifier circuit A includes a clock input terminal, a first differential signal input terminal, a second differential signal input terminal, an output node FN and an output node FP; the clock input terminal is used to input a clock signal CLK, the first differential signal input terminal and the second differential signal input terminal The two differential signal input terminals are respectively used to access the first differential input signal V _IP and the second differential input signal V _IN ; The preamplifier circuit A is connected to the DC power supply, the output node FN synthesizes the output voltage VDD of the DC power supply and the first differential input signal V _IP to output the first differential output signal V _FN , and the output node FP synthesizes the output voltage VDD of the DC power supply and the second The differential input signal V _IN is used to output the second differential output signal V _FP ; the regenerative latch circuit B is connected to the output node FN and the output node FP of the preamplifier circuit A, which can be used to output the first differential output signal V _FN and the second Latching the differential output signal V _FP and outputting the first output signal V _OP and the second output signal V _ON ; The high-speed and low-power dynamic comparator has two states according to the clock signal CLK input from the clock input terminal: in the first state, the first differential output signal V _FN , the second differential output signal V _FP , the first output signal V Both _OP and the second output signal V _ON are in the reset state; in the second state, the regenerative latch circuit B latches the first differential output signal V _FN and the second differential output signal V _FP , and outputs the first output signal V _OP and the second output signal V _ON ; The preamplifier circuit A includes: an input module, a clock reset module, a cross-coupling module and a tail current module; The output node FN and the output node FP are respectively connected to the first differential signal input terminal and the second differential signal input terminal through the input module; the output node FN and the output node FP are connected to the DC power supply through the serial input module and the tail current module, and the tail current module and The clock input terminal is connected and controlled by the clock signal CLK; the first differential output signal V _FN can control the output node FP to be turned on or off to the ground through the cross-coupling module to control the second differential output signal V _FP to be pulled down to the ground , the second differential output signal V _FP can control the output node FN to be turned on or off to the ground through the cross-coupling module to control the first differential output signal V _FN to be pulled down to the ground; Both the output node FN and the output node FP are grounded through the clock reset module, and the clock reset module is connected to the clock input terminal and controlled by the clock signal CLK to turn it on and off; In the first state, the tail current module is turned off, the clock reset module is turned on, and the first differential output signal V _FN and the second differential output signal V _FP are reset; in the second state, the tail current module is turned on, the clock reset module is turned off, and the second differential output signal V FN is reset. A differential output signal V _FN rises and falls according to the output voltage VDD of the DC power supply and the first differential input signal V _IP , and the second differential output signal V _FP rises and falls according to the output voltage VDD of the DC power supply and the second differential input signal V _IN ; The cross-coupling module includes a first on-off element and a second on-off element, the output node FN and the output node FP are respectively grounded through the first on-off element and the second on-off element, and the output node FN is connected to the second on-off element and passed through The first differential output signal V _FN controls the working state of the second on-off element, the output node FP is connected to the first on-off element and controls the working state of the first on-off element through the second differential output signal V _FP ; The tail current module adopts PMOS tube Mt, its source is connected to the DC power supply, its gate is connected to the clock input terminal, and its drain is connected to the input module; The regenerative latch circuit B includes: a first control module, a second control module and a cross-coupled inverter; the first control module, the second control module and the cross-coupled inverter are all connected to a DC power supply; the output node FN and the output node FP is respectively connected to the cross-coupled inverter through the first control module and the second control module, an output terminal OP is provided between the first control module and the cross-coupled inverter for outputting the first output signal V _OP , and the second control module An output terminal ON is provided between the cross-coupled inverter and the second output signal V _ON ; the regenerative latch circuit B has a completely symmetrical structure; The first control module includes MOS transistor M7, MOS transistor M13 and MOS transistor M15, the second control module includes MOS transistor M8, MOS transistor M14 and MOS transistor M16, and the cross-coupled inverter includes MOS transistor M9, MOS transistor M10, MOS transistor M11 and MOS tube M12; Among them, MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10 are all NMOS tubes; MOS tube M11 and MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16 is a PMOS tube, and the source is connected to a DC power supply; The cross-coupled inverter is provided with a node COP and a node CON, and the node COP is respectively connected to the drain of the MOS transistor M11, the drain of the MOS transistor M9, the gate of the MOS transistor M10, and the gate of the MOS transistor M12; the node CON is respectively connected to The drain of the MOS transistor M12, the drain of the MOS transistor M10, the gate of the MOS transistor M11 and the gate of the MOS transistor M9; The output node FN is respectively connected to the gate of the MOS transistor M7, the gate of the MOS transistor M13, and the gate of the MOS transistor M15, and the output terminal OP is respectively connected to the drain of the MOS transistor M7, the drain of the MOS transistor M15, and the source of the MOS transistor M9. pole; the source of the MOS transistor M7 is grounded, and the drain of the MOS transistor M13 is connected to the node COP; The output node FP is respectively connected to the gate of the MOS transistor M8, the gate of the MOS transistor M14, and the gate of the MOS transistor M16, and the output terminal ON is respectively connected to the drain of the MOS transistor M8, the drain of the MOS transistor M16, and the source of the MOS transistor M10. pole; the source of the MOS transistor M8 is grounded, and the drain of the MOS transistor M14 is connected to the node CON. 2. The high-speed and low-power dynamic comparator according to claim 1, wherein the input module includes a MOS transistor M1 and a MOS transistor M2, the cross-coupling module includes a MOS transistor M3 and a MOS transistor M4, and the first on-off element is a MOS transistor M5, and the second on-off element is a MOS transistor M6; The gate of the MOS transistor M1 and the gate of the MOS transistor M2 are respectively used as the first differential signal input terminal and the second differential signal input terminal; the output node FN and the output node FP are respectively connected to the PMOS transistor Mt through the MOS transistor M1 and the MOS transistor M2 The drain of the MOS transistor M5 and the MOS transistor M6 are connected to the ground respectively, and the gate of the MOS transistor M5 and the gate of the MOS transistor M6 are connected to the clock input terminal; the output node FN and the output node FP are respectively connected to the MOS transistor M3 and the MOS The transistor M4 is grounded, and the output node FN and the output node FP are connected to the gate of the MOS transistor M4 and the gate of the MOS transistor M3 respectively. 3. The dynamic comparator with high speed and low power consumption as claimed in claim 2, wherein MOS transistor M1 and MOS transistor M2 are PMOS transistors, and MOS transistor M3, MOS transistor M4, MOS transistor M5 and MOS transistor M6 are NMOS transistors. Tube. 4 . The high-speed and low-power dynamic comparator according to claim 1 , wherein in the first state, the clock signal CLK is at a high level, and in the second state, the clock signal CLK is at a low level.