CN106209035A - A kind of two stage comparator - Google Patents

A kind of two stage comparator Download PDF

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Publication number
CN106209035A
CN106209035A CN201610548587.9A CN201610548587A CN106209035A CN 106209035 A CN106209035 A CN 106209035A CN 201610548587 A CN201610548587 A CN 201610548587A CN 106209035 A CN106209035 A CN 106209035A
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pmos
nmos transistor
transistor
electrode
stage
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唐鹤
印钰
高昂
何生生
车来晟
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A kind of two-stage comparator circuit, belongs to Analogous Integrated Electronic Circuits technical field.Including: the input stage being made up of the first NMOS tube (MN1), the second NMOS tube (MN2), the 3rd NMOS tube (MN3), the first PMOS (MP1), the second PMOS (MP2), the 3rd PMOS (MP3) and the 4th PMOS (MP4)；And the latch stage being made up of the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 9th NMOS tube (MN9), the 5th PMOS (MP5), the 6th PMOS (MP6), the 7th PMOS (MP7) and the 8th PMOS (MP8).By the reset to latch stage circuit interior joint X+ and X, reduce imbalance and the noise of circuit；By transistor MP1 and MP2 coupled plus pair of cross in input stage circuit, comparator is made to keep the feature of high speed operation.Comparator of the present invention is applicable in high-precision circuit system.

Description

Two-stage comparator
Technical Field
The invention belongs to the technical field of electronics, relates to the design technology of an analog integrated circuit, and particularly relates to a low-noise low-offset high-speed comparator circuit.
Background
A comparator is a circuit that compares an analog voltage signal with a reference voltage. A conventional double-tailed comparator structure, as shown in fig. 1, is composed of two stages, namely an input stage and a latch stage, wherein the input stage is a first stage, and the latch stage is a second stage. The tail current of the input stage is controlled by a clock signal CLK and the tail current of the latch stage is controlled by an inverted CLKB of the clock signal. When the clock signal CLK is GND, the comparator enters a RESET phase (RESET). The transistors MP1 and MP2 pull the output nodes DI + and DI-of the first stage high to the power supply voltage VDD, so that the transistors MN6 and MN7 are turned on, so the output nodes OUTP and OUTN of the comparators are pulled low to ground, completing the reset. When CLK is VDD, transistors MP1 and MP2 are turned off, and MN1 and MP5 are turned on, so the input stage amplifies the differential input voltage VINP-VINN and outputs to DI + and DI-, and then the latch stage further rapidly amplifies the difference between DI + and DI-by positive feedback, finally making OUTP and OUTN output VDD or GND. The traditional comparator has simple structure and high speed, but has the following defects: 1. the timing of the clock signal CLK and the inverted CLKB of the clock signal must be very accurate; 2. the node X is not reset when the CLK is equal to the GND, so that the offset of the comparator is large; 3. when the comparator enters the comparison stage, the noise is relatively large because the transistor MP5 enters the linear region.
Disclosure of Invention
The invention provides a two-stage comparator circuit which has the characteristics of low offset, low noise, lower time sequence requirement and high speed.
The technical scheme of the invention is as follows:
a two-stage comparator comprises an input stage and a latch stage, wherein the input stage is composed of 3 NMOS transistors and 4 PMOS transistors, and the latch stage is composed of 6 NMOS transistors and 4 PMOS transistors; in the input stage, the gates of the first NMOS transistor MN1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected with a clock signal CLK; the drain of the first NMOS transistor MN1 is connected with the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN 3; the gate of the second NMOS transistor MN2 is connected to the input signal VINN; the gate of the third NMOS transistor MN3 is connected to the input signal VINP; the drain electrode of the second NMOS transistor MN2, the drain electrode of the third PMOS transistor MP3, the drain electrode of the first PMOS transistor MP1 and the gate electrode of the second PMOS transistor MP2 are connected with the DI + output end of the input stage; the drain electrode of the third NMOS transistor MN3, the drain electrode of the fourth PMOS transistor MP4, the drain electrode of the second PMOS transistor MP2 and the gate electrode of the first PMOS transistor MP1 are connected with the DI-output end of the input stage; the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected with power supply voltage; the source electrode of the first NMOS transistor MN1 is grounded; the grid electrode of a sixth NMOS transistor MN6, the grid electrode of an eighth NMOS transistor MN8 and the grid electrode of a seventh PMOS transistor MP7 in the latch stage are connected with the DI + output end of the input stage; the grid electrode of the seventh NMOS transistor MN7, the grid electrode of the ninth NMOS transistor MN9 and the grid electrode of the eighth PMOS transistor MP8 are connected with the DI-output end of the input stage; the drain electrode of the sixth NMOS transistor MN6, the drain electrode of the fourth NMOS transistor MN4, the drain electrode of the fifth PMOS transistor MP5, the gate electrode of the fifth NMOS transistor MN5 and the gate electrode of the sixth PMOS transistor MP6 are connected with the OUTN output node; the grid electrode of the fourth NMOS transistor MN4, the grid electrode of the fifth PMOS transistor MP5, the drain electrode of the fifth NMOS transistor MN5, the drain electrode of the seventh NMOS transistor MN7 and the drain electrode of the sixth PMOS transistor MP6 are connected with an OUTP output node; the source electrode of the fifth PMOS tube MP5, the drain electrode of the eighth NMOS tube MN8 and the drain electrode of the seventh PMOS tube MP7 are connected with an X + node; the drain electrode of the eighth PMOS tube MP8, the source electrode of the sixth PMOS tube MP6 and the drain electrode of the ninth NMOS tube MN9 are connected with an X-node; the source electrode of the seventh PMOS tube MP7 and the source electrode of the eighth PMOS tube MP8 are connected with power supply voltage; the sources of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded.
The invention has the following beneficial effects:
the two-stage comparator circuit has the advantages of low offset, low noise, low time sequence requirement, high speed and the like. Compared with the prior art, the two-stage comparator circuit overcomes the problems that the traditional double-tail comparator has very accurate time sequence requirement, larger offset of the comparator, larger noise and the like. Firstly, the two-stage comparator circuit reduces the offset and noise of the circuit by resetting the nodes X + and X-; secondly, the two-stage comparator circuit keeps the characteristic of high-speed operation of the comparator by adding a pair of cross-coupled transistors MP1 and MP2 in the first stage circuit.
Drawings
Fig. 1 is a schematic diagram of a conventional double tail comparator.
Fig. 2 is a schematic diagram of a two-stage comparator circuit according to the present invention.
Fig. 3 is a simplified diagram of a two-stage comparator circuit provided by the present invention.
FIG. 4 is a schematic diagram of the noise distribution of the two-stage comparator circuit and the conventional two-tail comparator according to the present invention.
Fig. 5 is a schematic diagram of the offset distribution of a conventional double tail comparator.
Fig. 6 is a schematic diagram of the offset distribution of the two-stage comparator provided in the present invention.
Fig. 7 is a speed comparison diagram of the two-stage comparator provided by the present invention and the conventional two-tailed comparator.
Fig. 8 is a table comparing the performance of the two-stage comparator provided by the present invention with that of the conventional two-tailed comparator.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
The invention provides a two-stage comparator circuit aiming at the problems of very accurate time sequence requirement on clock signals, larger offset of a comparator, larger noise and the like of the existing double-tail comparator circuit, and the specific circuit structure is shown in figure 2, the two-stage comparator circuit comprises an input stage and a latch stage, the input stage consists of 3 NMOS (N-channel metal oxide semiconductor) tubes and 4 PMOS (P-channel metal oxide semiconductor) tubes, and the latch stage consists of 6 NMOS tubes and 4 PMOS tubes; in the input stage, the gates of the first NMOS transistor MN1, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected with a clock signal CLK; the drain of the first NMOS transistor MN1 is connected with the source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN 3; the gate of the second NMOS transistor MN2 is connected to the input signal VINN; the gate of the third NMOS transistor MN3 is connected to the input signal VINP; the drain electrode of the second NMOS transistor MN2, the drain electrode of the third PMOS transistor MP3, the drain electrode of the first PMOS transistor MP1 and the gate electrode of the second PMOS transistor MP2 are connected with the DI + output end of the input stage; the drain electrode of the third NMOS transistor MN3, the drain electrode of the fourth PMOS transistor MP4, the drain electrode of the second PMOS transistor MP2 and the gate electrode of the first PMOS transistor MP1 are connected with the DI-output end of the input stage; the source electrodes of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected with power supply voltage; the source electrode of the first NMOS transistor MN1 is grounded; the grid electrode of a sixth NMOS transistor MN6, the grid electrode of an eighth NMOS transistor MN8 and the grid electrode of a seventh PMOS transistor MP7 in the latch stage are connected with the DI + output end of the input stage; the grid electrode of the seventh NMOS transistor MN7, the grid electrode of the ninth NMOS transistor MN9 and the grid electrode of the eighth PMOS transistor MP8 are connected with the DI-output end of the input stage; the drain electrode of the sixth NMOS transistor MN6, the drain electrode of the fourth NMOS transistor MN4, the drain electrode of the fifth PMOS transistor MP5, the gate electrode of the fifth NMOS transistor MN5 and the gate electrode of the sixth PMOS transistor MP6 are connected with the OUTN output node; the grid electrode of the fourth NMOS transistor MN4, the grid electrode of the fifth PMOS transistor MP5, the drain electrode of the fifth NMOS transistor MN5, the drain electrode of the seventh NMOS transistor MN7 and the drain electrode of the sixth PMOS transistor MP6 are connected with an OUTP output node; the source electrode of the fifth PMOS tube MP5, the drain electrode of the eighth NMOS tube MN8 and the drain electrode of the seventh PMOS tube MP7 are connected with an X + node; the drain electrode of the eighth PMOS tube MP8, the source electrode of the sixth PMOS tube MP6 and the drain electrode of the ninth NMOS tube MN9 are connected with an X-node; the source electrode of the seventh PMOS tube MP7 and the source electrode of the eighth PMOS tube MP8 are connected with power supply voltage; the sources of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are grounded.
When the clock signal CLK is equal to GND, the comparator enters a reset state. Transistors MP3 and MP4 pull the first stage outputs DI + and DI-high to the supply voltage VDD, which turns off transistors MP7 and MP8, so that nodes X +, X-and outputs OUTP, OUTN are pulled low to ground through MN8, MN9 and MN6, MN7, respectively, completing the reset.
When the clock signal CLK equals VDD, the comparator enters the comparison phase. The transistor MN1 is turned on, the MP3 and MP4 are turned off, the input stage starts operating, the input differential signal VINP-VINN is amplified and output to DI + and DI-, and then the latch stage further and rapidly amplifies the difference between DI + and DI-by positive and negative feedback, and finally OUTP and OUTN output VDD or GND.
The working principle and the optimization process of the two-stage comparator circuit are explained below with reference to the drawings respectively for the reset process and the comparison process.
1. Resetting the comparator:
as shown in fig. 2, the gates of the transistors MN6, MN7, MN8, MN9, MP7, and MP8 are all connected to the output terminals DI + and DI-of the first stage. When CLK is GND, the comparator enters the reset phase, and the transistors MP3 and MP4 pull the first stage outputs DI + and DI-high to the power supply voltage VDD, which turns off the transistors MP7 and MP8, so that the nodes X +, X-and the outputs OUTP, OUTN are pulled low to ground through MN8, MN9 and MN6, MN7, respectively, completing the reset. The reset process prevents mismatching of circuit node voltages from causing comparator misadjustment. Fig. 5 and 6 show the offset distribution diagrams of the conventional comparator and the comparator of the present invention, respectively. The abscissa is the offset voltage value equivalent to the input end, the ordinate is the frequency, the simulation condition is that the power voltage VDD is 1.2V, the common mode voltage VCM is 0.7V, and the monte carlo simulation tool is utilized to simulate 400 times. The offset of the comparator also satisfies the gaussian distribution, the offset voltage of one standard deviation of the conventional double-tailed comparator is 29.27mV, and the offset voltage of the comparator of the present invention is 11.35mV, as shown in table 1.
2. Comparator comparison process
When CLK is VDD, the comparator enters the comparison stage, and the transistors MN6, MN7, MN8, MN9, MP7, and MP8 all serve as input transistors of the latch stage. The transistor MN1 is turned on, the MP3 and MP4 are turned off, the input stage starts operating, the input differential signal VINP-VINN is amplified and output to DI + and DI-, and then the latch stage further and rapidly amplifies the difference between DI + and DI-by positive and negative feedback, and finally OUTP and OUTN output VDD or GND. Since the voltages at nodes X + and X-are equal to 0 during the reset phase, the transistors MP7 and MP8 operate in the saturation region at the beginning of the comparison phase, greatly reducing the latch stage noise. The reason for the noise reduction is specifically described below.
The noise sources of the MOSFET are channel thermal noise and flicker noise, while the noise of the MOSFET at high frequency is mainly from the channel thermal noise.
The irregular thermal motion of channel carriers generates noise voltage on channel resistance, the voltage causes fluctuation of channel potential distribution, effective grid voltage fluctuates, and accordingly drain current fluctuates, and the generated noise is channel thermal noise. The channel thermal noise can be modeled by a current source connected across the drain and source with a spectral density of
I n 2 ‾ = 4 k T β ( V G S - V T ) H ( η ) - - - 1
Wherein,k is Boltzmann's constant, T is temperature, VGSIs the gate-source voltage, VTIs the threshold voltage, V, of the transistorDSIs the drain-source voltage, CoxIs the gate capacitance per unit area, μ is the surface mobility of the substrate channel region, W is the channel width, and L is the channel length. It can be seen that channel thermal noise is derived from channel resistance and is also a function of device operating conditions.
When the device is brought into the saturation region,
I n 2 ‾ = 4 k T β ( V G S - V T ) × 2 3 - - - 2
when the device is in the non-saturation region,at this time
I n 2 ‾ > 4 k T β ( V G S - V T ) × 2 3 - - - 3
It can be seen that the channel thermal noise decreases rapidly with increasing drain-source voltage, reaching a minimum in the saturation region. The comparator of the invention enables the transistors MP7 and MP8 to work in a saturation region at the beginning of the comparison stage by resetting the nodes X + and X-, thereby greatly reducing the noise of the latch stage.
Fig. 4 is a schematic diagram showing the noise distribution of the comparator of the present invention and the conventional two-tailed comparator. The abscissa is the differential input voltage, the ordinate is the probability that the comparator outputs a high level, and the simulation conditions are that the power supply voltage VDD is 1.2V and the common mode voltage VCM is 0.7V. Since the noise satisfies the gaussian distribution, we can obtain that one standard deviation of the input equivalent noise voltage of the conventional two-tailed comparator is 1.7mV, while the comparator of the present invention is 0.46mV, as shown in table 1. The noise of the comparator of the invention is less than one third of that of the traditional comparator, and the noise characteristic is greatly improved.
As shown in FIG. 2, in order to achieve low noise and low offset, the comparator of the present invention divides the latch stage tail current tube of the conventional double tail comparator into two transistors MP7 and MP8, and adds a pair of reset tubes MN8 and MN9 at the circuit nodes X + and X-. This, of course, increases the parasitic capacitance at the DI + and DI-terminals, affecting the speed of the input stage of the comparator, thereby reducing the overall speed of the comparator.
In order to reduce the influence of the increase of parasitic capacitance on the speed of the comparator, the comparator of the invention adds a pair of cross-coupled transistors MP1 and MP2 in a first stage circuit. The comparator circuit of the present invention is simplified to fig. 3, where CL is the parasitic capacitance of DI + and DI-terminals, and the parasitic capacitance of both terminals is equal due to the complete symmetry of the circuit. Assuming that the input signal VINP is greater than VINN, transistors MN2 and MN3 are both on, but the drain-source current of MN3 is greater than the drain-source current of MN2, the parasitic capacitance of the DI-terminal discharges more quickly, resulting in the voltage at the DI-terminal being less than the voltage at the DI + terminal. The gate of the transistor MP1 is connected to the DI-terminal, the gate of the transistor MP2 is connected to the DI + terminal, and since the absolute value of the gate-source voltage of MP1 is greater than the absolute value of the gate-source voltage of MP2, the source-drain current of MP1 is greater than the source-drain current of MP2, and the charging speed of the DI + terminal to the parasitic capacitance is greater than that of the DI-terminal, the differential voltage of the DI + terminal is further expanded, and positive feedback is formed.
The transistors MP1 and MP2, which are connected in a cross-coupled pair, not only increase the speed of the input stage, but also increase the gain of the input stage, provide a greater differential input to the latch stage, reduce the comparison time of the latch stage, and thereby reduce the effect of the increase in parasitic capacitance at the output of the first stage on the speed of the comparator.
Fig. 7 is a schematic diagram comparing delay times of the comparator of the present invention and the conventional two-tailed comparator. The abscissa is the differential input voltage, the ordinate is the comparative delay time, and the simulation conditions are that the power supply voltage VDD is 1.2V and the common-mode voltage VCM is 0.7V. From the figure we can see that the comparator delay time is inversely proportional to the absolute value of the input differential voltage. As shown in table 1, when the differential input voltage is 0.1mV, the delay time of the conventional two-tailed comparator is 99.66ps, and the delay time of the comparator of the present invention is 117ps, which are not very different. The speed of the comparator is reduced and the delay time is prolonged due to the increase of the parasitic capacitance of the first-stage output end of the comparator, but the speed difference between the comparator and the traditional comparator is not large because the first-stage circuit is provided with a pair of cross-coupling pairs to improve the speed of the comparator.
The foregoing describes in detail a two-stage comparator circuit provided by the present invention, and the principle and the embodiments of the present invention are described by using specific embodiments, and the above embodiments are only used to help understanding the basic principle and the core idea of the present invention, and modifications of the specific embodiments on the basis of the basic principle and the core idea of the present invention should fall within the scope of the present invention.

Claims (1)

1. A two-stage comparator comprises an input stage and a latch stage, wherein the input stage is composed of 3 NMOS transistors and 4 PMOS transistors, and the latch stage is composed of 6 NMOS transistors and 4 PMOS transistors; in the input stage, the gates of a first NMOS transistor (MN1), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4) are connected with a clock signal (CLK); the drain electrode of the first NMOS transistor (MN1) is connected with the source electrode of the second NMOS transistor (MN2) and the source electrode of the third NMOS transistor (MN 3); the gate of the second NMOS transistor (MN2) is connected with an input signal (VINN); the gate of the third NMOS transistor (MN3) is connected with the input signal (VINP); the drain electrode of the second NMOS transistor (MN2), the drain electrode of the third PMOS transistor (MP3), the drain electrode of the first PMOS transistor (MP1) and the gate electrode of the second PMOS transistor (MP2) are connected with the DI + output end of the input stage; the drain electrode of the third NMOS transistor (MN3), the drain electrode of the fourth PMOS transistor (MP4), the drain electrode of the second PMOS transistor (MP2) and the gate electrode of the first PMOS transistor (MP1) are connected with the DI-output end of the input stage; the source electrodes of the first PMOS tube (MP1), the second PMOS tube (MP2), the third PMOS tube (MP3) and the fourth PMOS tube (MP4) are connected with power supply voltage; the source electrode of the first NMOS tube (MN1) is grounded; the grid electrode of a sixth NMOS transistor (MN6), the grid electrode of an eighth NMOS transistor (MN8) and the grid electrode of a seventh PMOS transistor (MP7) in the latch stage are connected with the DI + output end of the input stage; the grid electrode of the seventh NMOS transistor (MN7), the grid electrode of the ninth NMOS transistor (MN9) and the grid electrode of the eighth PMOS transistor (MP8) are connected with the DI-output end of the input stage; the drain electrode of the sixth NMOS transistor (MN6), the drain electrode of the fourth NMOS transistor (MN4), the drain electrode of the fifth PMOS transistor (MP5), the gate electrode of the fifth NMOS transistor (MN5) and the gate electrode of the sixth PMOS transistor (MP6) are connected with the OUTN output node; the grid electrode of the fourth NMOS tube (MN4), the grid electrode of the fifth PMOS tube (MP5), the drain electrode of the fifth NMOS tube (MN5), the drain electrode of the seventh NMOS tube (MN7) and the drain electrode of the sixth PMOS tube (MP6) are connected with the OUTP output node; the source electrode of the fifth PMOS tube (MP5), the drain electrode of the eighth NMOS tube (MN8) and the drain electrode of the seventh PMOS tube (MP7) are connected with an X + node; the drain electrode of the eighth PMOS tube (MP8), the source electrode of the sixth PMOS tube (MP6) and the drain electrode of the ninth NMOS tube (MN9) are connected with an X-node; the source electrode of the seventh PMOS tube (MP7) and the source electrode of the eighth PMOS tube (MP8) are connected with the power supply voltage; the sources of the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7), the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) are grounded.
CN201610548587.9A 2016-07-13 2016-07-13 A kind of two stage comparator Pending CN106209035A (en)

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Publication number Priority date Publication date Assignee Title
CN108305648B (en) * 2018-04-29 2023-12-19 山东泉景胜跃信息技术有限公司 DDR4 standard high-speed receiver circuit
CN109379074A (en) * 2018-11-21 2019-02-22 灿芯半导体(上海)有限公司 A kind of level shifting circuit
CN109727616A (en) * 2018-12-12 2019-05-07 珠海博雅科技有限公司 A kind of method and device of emulation metal-oxide-semiconductor amplifying circuit imbalance
CN112448721A (en) * 2019-08-29 2021-03-05 天津大学青岛海洋技术研究院 Low-power consumption comparator with low delay distortion characteristic of self-biasing circuit
CN112448721B (en) * 2019-08-29 2023-05-05 天津大学青岛海洋技术研究院 Low-power consumption comparator with low delay distortion characteristic of self-bias circuit
CN112350696B (en) * 2020-10-23 2023-01-20 广东工业大学 Double-feedback loop comparator
CN112350696A (en) * 2020-10-23 2021-02-09 广东工业大学 Double-feedback loop comparator
CN112636729B (en) * 2020-12-14 2022-12-09 重庆百瑞互联电子技术有限公司 Power dynamic comparator circuit with ultra-low power consumption
CN112636729A (en) * 2020-12-14 2021-04-09 重庆百瑞互联电子技术有限公司 Power dynamic comparator circuit with ultra-low power consumption
CN112953496B (en) * 2021-02-04 2022-04-22 电子科技大学 High-speed dynamic comparator
CN112953496A (en) * 2021-02-04 2021-06-11 电子科技大学 High-speed dynamic comparator
CN113364437A (en) * 2021-06-10 2021-09-07 上海磐启微电子有限公司 Method for realizing ultra-low power consumption high-speed comparator circuit
CN113364437B (en) * 2021-06-10 2024-07-23 上海磐启微电子有限公司 Method for realizing ultra-low power consumption high-speed comparator circuit

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Application publication date: 20161207