CN113131886A - Operational amplifier - Google Patents
Operational amplifier Download PDFInfo
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- CN113131886A CN113131886A CN202010042529.5A CN202010042529A CN113131886A CN 113131886 A CN113131886 A CN 113131886A CN 202010042529 A CN202010042529 A CN 202010042529A CN 113131886 A CN113131886 A CN 113131886A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
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Abstract
The application discloses an operational amplifier, which comprises an input stage circuit, a cascode amplifying circuit, an output stage circuit and a substrate biasing circuit. The substrate bias circuit is used for setting the substrate voltage of the differential transistor pair of the input stage circuit based on the input common-mode voltage of the differential input signal, and increasing the conduction threshold value of the differential transistor pair by adjusting the substrate voltage of the differential transistor pair, so that the differential transistor pair of the input stage circuit can still work in a saturation region under the lower input common-mode voltage, and the operational amplifier can work normally.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to an operational amplifier.
Background
An operational amplifier is a device capable of amplifying voltage or power of an input signal, and is widely applied to the fields of communication, PC, consumption, automobiles, industry and the like.
Fig. 1 shows a circuit schematic of an operational amplifier according to the prior art. The operational amplifier can be further divided into a single-stage operational amplifier, a two-stage operational amplifier, a multi-stage operational amplifier, and the like. As shown in fig. 1, a general operational amplifier 100 of a two-stage operational amplifier includes an input stage circuit 110, a cascode circuit 120, an output stage circuit 130, and a quiescent current control circuit 140.
The input stage circuit 110 includes a transistor Mp1, a transistor Mp2, and a current source I1. The transistor Mp1 and the transistor Mp2 form a differential transistor pair, i.e. the first terminals of the transistor Mp1 and the transistor Mp2 are connected to each other, and the first terminals of the transistor Mp1 and the transistor Mp2 are both connected to the second terminal of the current source I1, and the first terminal of the current source I1 is connected to the supply voltage VDD. The control terminal of the transistor Mp1 receives the differential input signal VIN and the control terminal of the transistor Mp2 receives the differential input signal VIP. The second ends of the transistor Mp1 and the transistor Mp2 respectively output two paths of differential current signals.
The cascode circuit 120 includes transistors Mp 3-Mp 6, and transistors Mn1-Mn 4.
The transistor Mp3, the transistor Mp5, the transistor Mn1 and the transistor Mn3 are connected in series in this order in a first branch between the supply voltage VDD and ground. In the on state of the four, current flows from the power supply voltage VDD to ground through the transistor Mp3, the transistor Mp5, the transistor Mn1, and the transistor Mn 3.
The transistor Mp4, the transistor Mp6, the transistor Mn2 and the transistor Mn4 are in turn connected in series in a second branch between the supply voltage VDD and ground. In the on state of the four, current flows from the power supply voltage VDD to ground through the transistor Mp4, the transistor Mp6, the transistor Mn2, and the transistor Mn 4.
The control terminals of the transistor Mn1 and the transistor Mn2 are connected to each other, and the control terminals of both receive the bias voltage Vb 3. The second terminal of the transistor Mn1 is connected to the second terminal of the transistor Mp1 to receive the differential current signal output by the transistor Mp1, the second terminal of the transistor Mn2 is connected to the second terminal of the transistor Mp2 to receive the differential current signal output by the transistor Mp2, and the first terminal of the transistor Mn2 is connected to the output stage circuit 130 to output a single path of differential amplified signal.
The second terminal of the transistor Mn1 is connected to the first terminal of the transistor Mn3, and the second terminal of the transistor Mn2 is connected to the first terminal of the transistor Mn 4. The second terminals of the transistor Mn3 and the transistor Mn4 are both grounded. The control terminals of the transistor Mn3 and the transistor Mn4 are connected to each other, and the control terminals of both are connected to the first terminal of the transistor Mn 1.
The first terminal of the transistor Mn1 is connected to the second terminal of the transistor Mp5, the first terminal of the transistor Mn2 is connected to the second terminal of the transistor Mp6, and the second terminal of the transistor Mp6 is connected to the output stage circuit 130 to output another differential amplified signal. The control terminals of the transistor Mp5 and the transistor Mp6 are connected to each other, and both receive the bias voltage Vb 2.
The first terminal of the transistor Mp5 is connected to the second terminal of the transistor Mp3, and the first terminal of the transistor Mp6 is connected to the second terminal of the transistor Mp 4. The first terminals of the transistor Mp3 and the transistor Mp4 are both connected to the supply voltage VDD. The control terminals of the transistor Mp3 and the transistor Mp4 are connected to each other, and both receive the bias voltage Vb 1.
The output stage circuit 130 includes an output tube Mpout and an output tube Mnout connected in series between the power supply voltage VDD and ground in this order, and an intermediate node of the output tube Mpout and the output tube Mnout is used to provide the output signal Vout.
The quiescent current control circuit 140 is used to control the magnitude of the quiescent current of the output stage circuit 130 and implement the class AB operation mode. The working mode for realizing the AB class is as follows: the output stage circuit has smaller static current flowing through the output stage circuit in a static state, can output larger current to a load in a dynamic state, and has higher output efficiency and smaller cross-over distortion.
In the conventional operational amplifier 100, the substrates of the transistor Mp1 and the transistor Mp2 in the input stage circuit 110 are both connected to the power supply voltage VDD, and this connection can make the input common-mode voltage below 0V. However, for a high voltage operational amplifier, when the input common mode voltage is equal to 0V, the voltage difference Vgb between the gates and the substrate of the transistor Mp1 and the transistor Mp2 approaches the power supply voltage VDD. Since the power supply voltage VDD in the high-voltage operational amplifier is generally relatively large (the power supply voltage VDD is close to 40V), the voltage difference Vgb may cause damage to the transistor Mp1 and the transistor Mp 2.
Therefore, there is a need for an improved operational amplifier of the prior art to increase the input common mode voltage range of the input stage circuit.
Disclosure of Invention
In view of the above, the present invention provides an operational amplifier, which improves the safety and stability of a differential transistor pair of an input stage circuit under any input common mode voltage.
According to an embodiment of the present invention, there is provided an operational amplifier including: the input stage circuit comprises a differential transistor pair, wherein the differential transistor pair is used for receiving a differential input signal and outputting two paths of differential current signals; the cascode amplifying circuit receives the differential current signals and outputs a pair of differential output signals; and an output stage circuit that receives the differential output signal and implements rail-to-rail output, wherein the operational amplifier further includes a substrate bias circuit for setting a substrate voltage of a differential transistor pair of the input stage circuit based on an input common mode voltage of the differential input signal.
Preferably, the substrate bias circuit includes: a first current source having a first terminal connected to a supply voltage and a second terminal; a resistor having a first terminal connected to the second terminal of the first current source and a second terminal; and the first transistor and the second transistor form a differential transistor pair, control ends of the first transistor and the second transistor are used for receiving the differential input signal, a first end of the first transistor and a second end of the second transistor are connected with the second end of the resistor, the second end of the resistor is grounded, and an intermediate node of the first current source and the resistor is used for providing a substrate voltage of the differential transistor pair of the input stage circuit.
Preferably, the substrates of the first transistor and the second transistor are connected to an intermediate node between the first current source and the resistor.
Preferably, the substrate voltage of a desired value is obtained by setting the values of the first current source and the resistor.
Preferably, the operational amplifier further comprises a quiescent current control circuit for controlling a quiescent current of the output stage circuit.
Preferably, the input stage circuit includes: a second current source having a first terminal connected to a supply voltage and a second terminal; and the third transistor and the fourth transistor form a differential transistor pair, control ends of the third transistor and the fourth transistor are used for receiving the differential input signal, a first end of the third transistor and a second end of the fourth transistor are connected with a second end of the second current source, and the second end of the third transistor and the fourth transistor is used for outputting the two paths of differential current signals.
Preferably, the cascode amplification circuit includes: a fifth transistor, a seventh transistor, a ninth transistor, and an eleventh transistor connected in series between the positive power supply terminal and ground; and a sixth transistor, an eighth transistor, a tenth transistor, and a twelfth transistor connected in series between the positive power source terminal and ground, wherein control terminals of the fifth transistor and the sixth transistor are connected to each other and receive a first bias voltage, control terminals of the seventh transistor and the eighth transistor are connected to each other, and receives a second bias voltage, control terminals of the ninth transistor and the tenth transistor are connected to each other, and receives a third bias voltage, control terminals of the eleventh transistor and the twelfth transistor are connected to each other, and is connected to a first terminal of the ninth transistor, second terminals of the ninth transistor and the tenth transistor respectively receiving the differential current signal, a second terminal of the eighth transistor and a first terminal of the tenth transistor are used to output the differential output signal.
Preferably, the output stage circuit includes a first output tube and a second output tube sequentially connected between the power supply voltage and ground, wherein control ends of the first output tube and the second output tube are connected to the cascode amplifying circuit to receive the differential output signal, and an intermediate node of the first output tube and the second output tube is configured to provide an output signal.
Preferably, the first to eighth transistors and the first output tube are P-type MOSFETs, respectively, and the ninth to twelfth transistors and the second output tube are N-type MOSFETs, respectively.
The operational amplifier comprises an input stage circuit, a cascode amplifying circuit, an output stage circuit and a substrate biasing circuit, wherein the substrate biasing circuit is used for setting the substrate voltage of a differential transistor pair of the input stage circuit based on the input common-mode voltage of a differential input signal, and the conduction threshold value of the differential transistor pair is increased by adjusting the substrate voltage of the differential transistor pair, so that the differential transistor pair of the input stage circuit can still work in a saturation region under the lower input common-mode voltage, and the operational amplifier can work normally.
Further, since the voltage difference between the gate and the substrate of the differential transistor pair of the operational amplifier of this embodiment is a fixed value and does not change with the change of the input common mode voltage and the power supply voltage, the differential transistor pair of the input stage circuit of the operational amplifier of this embodiment can always operate in a safe range, thereby improving the safety and stability of the differential transistor pair of the input stage circuit under any input common mode voltage.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a circuit schematic of an operational amplifier according to the prior art;
fig. 2 shows a circuit schematic of an operational amplifier according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOSFET, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
The invention is further illustrated with reference to the following figures and examples.
Fig. 2 shows a circuit schematic of an operational amplifier according to an embodiment of the invention. As shown in fig. 2, the operational amplifier 200 includes an input stage circuit 210, a cascode amplification circuit 220, an output stage circuit 230, a quiescent current control circuit 240, and a substrate bias circuit 250. The input stage circuit 210 is also called a pre-stage circuit, and is generally a two-terminal input high-performance differential amplifier circuit, which includes a differential transistor pair for inputting differential input signals VIP and VIN, and outputting two differential current signals according to the differential input signals VIP and VIN. The cascode circuit 220 is a main amplifying circuit of the operational amplifier, and functions to obtain a pair of differential output signals according to the two differential current signals of the input stage circuit 210. Output stage circuit 230 receives the differential output signal and implements a rail-to-rail output. The quiescent current control circuit 240 is used to control the magnitude of the quiescent current of the output stage circuit 230 and implement the class AB operation. The substrate bias circuit 250 is used to set the substrate voltages of the differential transistor pairs in the input stage circuit 210 based on the input common mode voltages of the differential input signals VIP and VIN to ensure that the differential transistor pairs in the input stage circuit 210 can still operate properly when the input common mode voltages of the differential input signals VIP and VIN are low.
The working mode for realizing the AB class is as follows: the output stage circuit has smaller static current flowing through the output stage circuit in a static state, can output larger current to a load in a dynamic state, and has higher output efficiency and smaller cross-over distortion.
Further, the input stage circuit 210 includes a transistor Mp1, a transistor Mp2, and a current source I1. The transistor Mp1 and the transistor Mp2 form a differential transistor pair, i.e. the first terminals of the transistor Mp1 and the transistor Mp2 are connected to each other, and the first terminals of the transistor Mp1 and the transistor Mp2 are both connected to the second terminal of the current source I1, and the first terminal of the current source I1 is connected to the supply voltage VDD. The control terminal of the transistor Mp1 receives the differential input signal VIN and the control terminal of the transistor Mp2 receives the differential input signal VIP. The second ends of the transistor Mp1 and the transistor Mp2 respectively output two paths of differential current signals.
The cascode circuit 220 includes transistors Mp 3-Mp 6, and transistors Mn1-Mn 4.
The transistor Mp3, the transistor Mp5, the transistor Mn1 and the transistor Mn3 are connected in series in this order in a first branch between the supply voltage VDD and ground. In the on state of the four, current flows from the power supply voltage VDD to ground through the transistor Mp3, the transistor Mp5, the transistor Mn1, and the transistor Mn 3.
The transistor Mp4, the transistor Mp6, the transistor Mn2 and the transistor Mn4 are in turn connected in series in a second branch between the supply voltage VDD and ground. In the on state of the four, current flows from the power supply voltage VDD to ground through the transistor Mp4, the transistor Mp6, the transistor Mn2, and the transistor Mn 4.
The control terminals of the transistor Mn1 and the transistor Mn2 are connected to each other, and the control terminals of both receive the bias voltage Vb 3. The second terminal of the transistor Mn1 is connected to the second terminal of the transistor Mp1 to receive the differential current signal output by the transistor Mp1, the second terminal of the transistor Mn2 is connected to the second terminal of the transistor Mp2 to receive the differential current signal output by the transistor Mp2, and the first terminal of the transistor Mn2 is connected to the output stage circuit 230 to output a single path of differential amplified signal.
The second terminal of the transistor Mn1 is connected to the first terminal of the transistor Mn3, and the second terminal of the transistor Mn2 is connected to the first terminal of the transistor Mn 4. The second terminals of the transistor Mn3 and the transistor Mn4 are both grounded. The control terminals of the transistor Mn3 and the transistor Mn4 are connected to each other, and the control terminals of both are connected to the first terminal of the transistor Mn 1.
The first terminal of the transistor Mn1 is connected to the second terminal of the transistor Mp5, the first terminal of the transistor Mn2 is connected to the second terminal of the transistor Mp6, and the second terminal of the transistor Mp6 is connected to the output stage circuit 230 to output another differential amplified signal. The control terminals of the transistor Mp5 and the transistor Mp6 are connected to each other, and both receive the bias voltage Vb 2.
The first terminal of the transistor Mp5 is connected to the second terminal of the transistor Mp3, and the first terminal of the transistor Mp6 is connected to the second terminal of the transistor Mp 4. The first terminals of the transistor Mp3 and the transistor Mp4 are both connected to the supply voltage VDD. The control terminals of the transistor Mp3 and the transistor Mp4 are connected to each other, and both receive the bias voltage Vb 1.
The output stage circuit 230 includes an output tube Mpout and an output tube Mnout connected in series between the power supply voltage VDD and ground in this order, and an intermediate node of the output tube Mpout and the output tube Mnout is used to provide the output signal Vout.
The substrate bias circuit 250 includes a transistor Mp7, a transistor Mp8, a current source I2, and a resistor R1. The transistor Mp7 and the transistor Mp8 form a differential transistor pair, i.e. the first terminals of the transistor Mp7 and the transistor Mp8 are connected to each other, and the first terminals of the transistor Mp7 and the transistor Mp8 are both connected to the second terminal of the resistor R1, the first terminal of the resistor R1 is connected to the second terminal of the current source I2, and the first terminal of the current source I2 is connected to the supply voltage VDD. The intermediate node of the current source I2 and the resistor R1 is connected to the substrate of the transistor Mp1 and the transistor Mp2 to provide the substrate voltages of the transistor Mp1 and the transistor Mp 2. The control terminal of the transistor Mp7 receives the differential input signal VIP, the control terminal of the transistor Mp8 receives the differential input signal VIN, and the second terminals of the transistor Mp7 and the transistor Mp8 are grounded. In addition, the substrates of the transistor Mp7 and the transistor Mp8 are also connected to an intermediate node of the current source I2 and the resistor R1.
In the above embodiment, the transistors Mp1-Mp8 and the output tube Mpout employ P-type MOSFETs, respectively, and the transistors Mn1-Mn4 and the output tube Mnout employ N-type MOSFETs, respectively.
The principle of the operational amplifier of the present embodiment is: the substrate bias circuit 250 sets the substrate voltage Vbulk of the transistor Mp1 and the transistor Mp2 in the input stage circuit 210 according to the input common mode voltage of the differential input signals VIP and VIN, wherein the substrate voltage Vbulk is:
Vbulk＝Vcm+Vgsp1+I2×R1
where Vcm is the input common mode voltage of the differential input signals VIP and VIN, Vgsp1 is the gate-source voltage of the transistor Mp7 and the transistor Mp8, I2 is the current provided by the current source I2, and R1 is the resistance of the resistor R1. By setting the values of the current source I2 and the resistor R1, the desired value of the substrate voltage Vbulk can be obtained.
The drain-source voltage Vds of the transistor Mp1 and the transistor Mp2 is:
Vds＝Vcm+Vgsp2-Vds_Mn
where Vcm is the input common mode voltage of the differential input signals VIP and VIN, Vgsp2 is the gate-source voltage of the transistor Mp1 or the transistor Mp2, and Vds _ Mn is the drain-source voltage of the transistor Mn3 or the transistor Mn 2.
According to the transistor saturation current formula, the peak current when the transistor Mp1 and the transistor Mp2 work in the saturation region is:
Vdsat＝Vgsp2-Vth
wherein the proportionality coefficient munFor low field electron mobility, Cox is the gate oxide capacitance per unit area, Vdsat is the drain-source voltage when transistor Mp1 and transistor Mp2 operate in the saturation region, and Vth is the turn-on threshold of transistor Mp1 and transistor Mp 2.
Due to the substrate bias effect, the conduction thresholds of the transistor Mp1 and the transistor Mp2 can be increased by setting the values of the current source I2 and the resistor R1 to obtain the substrate voltage Vbulk with a desired value, so that Vds > Vdsat can still be established at a low input common mode voltage, that is, the transistor Mp1 and the transistor Mp2 can still operate in a saturation region at a low input common mode voltage, so that the operational amplifier can operate normally.
Further, the voltage difference between the gates and the substrate of the transistor Mp1 and the transistor Mp2 is:
Vgb＝Vbulk-Vcm
and:
Vbulk＝Vcm+Vgsp1+I2×R1
therefore, the voltage difference between the gate and the substrate of the transistor Mp1 and the transistor Mp2 can be obtained as follows:
Vgb＝Vgsp1+I2×R1
generally, I2 × R1 is about 1V, so that the differential transistor pair of the input stage circuit can operate in a safe range regardless of the input common mode voltage and the power supply voltage.
In summary, the operational amplifier according to the embodiment of the present invention includes an input stage circuit, a cascode amplifying circuit, an output stage circuit, and a substrate bias circuit, where the substrate bias circuit is configured to set a substrate voltage of a differential transistor pair of the input stage circuit based on an input common-mode voltage of a differential input signal, and increase a conduction threshold of the differential transistor pair by adjusting the substrate voltage of the differential transistor pair, so that the differential transistor pair of the input stage circuit can still operate in a saturation region at a lower input common-mode voltage, thereby ensuring that the operational amplifier can operate normally.
Further, since the voltage difference between the gate and the substrate of the differential transistor pair of the operational amplifier of this embodiment is a fixed value and does not change with the change of the input common mode voltage and the power supply voltage, the differential transistor pair of the input stage circuit of the operational amplifier of this embodiment can always operate in a safe range, thereby improving the safety and stability of the differential transistor pair of the input stage circuit under any input common mode voltage.
It should be noted that although the device is described herein as being an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be understood by those skilled in the art that conductivity type refers to the mechanism by which conduction occurs, for example by conduction through holes or electrons, and thus does not relate to the doping concentration but to the doping type, for example P-type or N-type. It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reactive action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (9)
1. An operational amplifier, comprising:
the input stage circuit comprises a differential transistor pair, wherein the differential transistor pair is used for receiving a differential input signal and outputting two paths of differential current signals;
the cascode amplifying circuit receives the differential current signals and outputs a pair of differential output signals; and
an output stage circuit receiving the differential output signal and implementing a rail-to-rail output,
wherein the operational amplifier further comprises a substrate bias circuit for setting a substrate voltage of a differential transistor pair of the input stage circuit based on an input common mode voltage of the differential input signal.
2. The operational amplifier of claim 1, wherein the substrate bias circuit comprises:
a first current source having a first terminal connected to a supply voltage and a second terminal;
a resistor having a first terminal connected to the second terminal of the first current source and a second terminal; and
a first transistor and a second transistor, which form a differential transistor pair, wherein control terminals of the first transistor and the second transistor are used for receiving the differential input signal, a first terminal is connected with a second terminal of the resistor, a second terminal is grounded,
wherein an intermediate node of the first current source and the resistor is used to provide a substrate voltage of a differential transistor pair of the input stage circuit.
3. The operational amplifier of claim 2, wherein the substrates of the first transistor and the second transistor are connected to an intermediate node of the first current source and the resistor.
4. The operational amplifier of claim 2, wherein the substrate voltage of a desired value is obtained by setting the values of the first current source and the resistor.
5. The operational amplifier of claim 1, further comprising a quiescent current control circuit for controlling the quiescent current of the output stage circuit.
6. The operational amplifier of claim 2, wherein the input stage circuit comprises:
a second current source having a first terminal connected to a supply voltage and a second terminal; and
and the control ends of the third transistor and the fourth transistor are used for receiving the differential input signal, the first end of the third transistor and the fourth transistor is connected with the second end of the second current source, and the second end of the third transistor and the fourth transistor is used for outputting the two paths of differential current signals.
7. The operational amplifier of claim 6, wherein the cascode amplification circuit comprises:
a fifth transistor, a seventh transistor, a ninth transistor, and an eleventh transistor connected in series between the positive power supply terminal and ground; and
a sixth transistor, an eighth transistor, a tenth transistor, and a twelfth transistor connected in series between the positive power supply terminal and ground,
wherein control terminals of the fifth transistor and the sixth transistor are connected to each other and receive a first bias voltage,
control terminals of the seventh transistor and the eighth transistor are connected to each other and receive a second bias voltage,
control terminals of the ninth transistor and the tenth transistor are connected to each other and receive a third bias voltage,
control terminals of the eleventh transistor and the twelfth transistor are connected to each other and to a first terminal of the ninth transistor,
second terminals of the ninth transistor and the tenth transistor respectively receive the differential current signal,
a second terminal of the eighth transistor and a first terminal of the tenth transistor are used to output the differential output signal.
8. The operational amplifier of claim 7, wherein the output stage circuit comprises a first output tube and a second output tube connected in sequence between the power supply voltage and ground,
wherein control ends of the first output tube and the second output tube are connected with the cascode amplification circuit to receive the differential output signal,
the intermediate node of the first output tube and the second output tube is used for providing an output signal.
9. The operational amplifier of claim 8, wherein the first to eighth transistors and the first output tubes are P-type MOSFETs, respectively, and the ninth to twelfth transistors and the second output tubes are N-type MOSFETs, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010042529.5A CN113131886B (en) | 2020-01-15 | 2020-01-15 | Operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010042529.5A CN113131886B (en) | 2020-01-15 | 2020-01-15 | Operational amplifier |
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| CN113131886B CN113131886B (en) | 2022-10-14 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114039560A (en) * | 2021-10-13 | 2022-02-11 | 杭州深谙微电子科技有限公司 | Operational amplifier and output stage circuit thereof |
| CN116346047A (en) * | 2021-12-24 | 2023-06-27 | 圣邦微电子（北京）股份有限公司 | Rail-to-rail operational amplifier and input stage structure thereof |
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| CN101986557A (en) * | 2010-11-24 | 2011-03-16 | 无锡思泰迪半导体有限公司 | Method and structure for eliminating offset voltage of operational amplifier by using lining bias effect |
| CN103427773A (en) * | 2012-05-21 | 2013-12-04 | 三星半导体(中国)研究开发有限公司 | Rail-to-rail operational amplifier |
| CN107733382A (en) * | 2017-09-11 | 2018-02-23 | 天津大学 | The rail-to-rail constant transconductance amplifier of automatic biasing |
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| CN101986557A (en) * | 2010-11-24 | 2011-03-16 | 无锡思泰迪半导体有限公司 | Method and structure for eliminating offset voltage of operational amplifier by using lining bias effect |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114039560A (en) * | 2021-10-13 | 2022-02-11 | 杭州深谙微电子科技有限公司 | Operational amplifier and output stage circuit thereof |
| CN116346047A (en) * | 2021-12-24 | 2023-06-27 | 圣邦微电子（北京）股份有限公司 | Rail-to-rail operational amplifier and input stage structure thereof |
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|---|---|
| CN113131886B (en) | 2022-10-14 |
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