CN112564649A

CN112564649A - Operational amplifier circuit

Info

Publication number: CN112564649A
Application number: CN201910850933.2A
Authority: CN
Inventors: 尤俊仁; 陈琨元; 谢嘉毫
Original assignee: FocalTech Systems Ltd
Current assignee: FocalTech Systems Ltd
Priority date: 2019-09-10
Filing date: 2019-09-10
Publication date: 2021-03-26

Abstract

An operational amplifier circuit, comprising: an input stage circuit for receiving an input voltage signal; a gain stage circuit coupled to the input stage circuit; an output stage circuit coupled to the gain stage circuit for providing an output voltage signal; a compensation circuit coupled to the input stage circuit and the output stage circuit; and a feedforward capacitor circuit coupled to the output stage circuit and the gain stage circuit. The output stage circuit comprises a P-type output transistor and an N-type output transistor, wherein the drains of the P-type output transistor and the N-type output transistor are connected together; the feedforward capacitor circuit comprises a first capacitor and a second capacitor, and is used for driving the gain stage circuit to quickly start a P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantaneously, and driving the gain stage circuit to quickly start an N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal falls instantaneously.

Description

Operational amplifier circuit

Technical Field

The present invention relates to an operational amplifier circuit, and more particularly, to an amplifier circuit having a feed-forward capacitor for increasing an instantaneous response speed.

Background

In a flat panel display, an Operational Amplifier (OP) is usually used as a source driver to drive a data line, and an input voltage signal representing a color is applied to a non-inverting input terminal and an inverting input terminal of the OP Amplifier, and after differential amplification by the OP Amplifier, the amplified color signal is transmitted to a flat panel display such as an LCD panel through the data line for display operation.

With the trend of high resolution and large area of the display, the load of the source driving operational amplifier has larger resistance and capacitance, and the transient response speed of the source driving operational amplifier is limited due to the limited area and power consumption of the source driving operational amplifier. However, due to the rapid progress of industry, the demand for display resolution and panel size has increased dramatically, which results in faster transient response speed of the source-driving operational amplifier and avoids increasing the overall static power consumption.

However, the current operational amplifier cannot increase the transient response speed without increasing the static power consumption, so it is difficult to satisfy the requirements of the current display for high resolution and low static power consumption, and there is still a need for improvement.

Disclosure of Invention

The present invention is directed to an operational amplifier circuit, which adds a feed-forward capacitor to accelerate the transient response of the output of the operational amplifier, and does not increase the static power consumption of the operational amplifier.

To achieve the above object, the present invention provides an operational amplifier circuit, comprising: an input stage circuit for receiving an input voltage signal; a gain stage circuit coupled to the input stage circuit; an output stage circuit, coupled to the gain stage circuit, for providing an output voltage signal, wherein the output stage circuit includes a P-type output transistor and an N-type output transistor, and drains of the P-type output transistor and the N-type output transistor are connected together; a compensation circuit coupled to the input stage circuit and the output stage circuit; and a feedforward capacitor circuit coupled to the output stage circuit and the gain stage circuit, wherein the feedforward capacitor circuit includes a first capacitor and a second capacitor, and is used for driving the gain stage circuit to quickly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal is raised instantaneously, and driving the gain stage circuit to quickly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal is lowered instantaneously.

The foregoing summary, as well as the following detailed description, is exemplary in nature and is intended to further illustrate the present invention as claimed, and other objects and advantages of the invention will be apparent from the following description and drawings.

Drawings

FIG. 1 is a block diagram of an operational amplifier circuit of the present invention.

Fig. 2 shows a circuit diagram of a first embodiment of the operational amplifier circuit of the present invention.

Fig. 3 shows a circuit diagram of a second embodiment of the operational amplifier circuit of the present invention.

FIG. 4 shows a simulation example of the operational amplifier circuit of the present invention.

FIG. 5 is a schematic diagram of an operational amplifier circuit according to a third embodiment of the present invention.

Description of the symbols:

input stage circuit 11 and gain stage circuit 13

Compensation circuit 15 output stage circuit 17

Feedforward capacitance circuit 19

First current mirror 111 and second current mirror 112

P-type differential input circuit 113N-type differential input circuit 114

First active load 115 and second active load 116

Input voltage signal VIN, VIP output voltage signal Vout

NMOS transistors 1151 to 1154 and PMOS transistors 1161 to 1164

Node VP2 node VN2

First gain circuit 131 and second gain circuit 132

Floating AB control circuit 133

PMOS transistor

1311,1312

NMOS transistor

1321,1322

Node VP1 node VN1

First compensation capacitor 151 and second compensation capacitor 152

P-type output transistor 171N-type output transistor 172

First capacitance 191 and second capacitance 192

Third capacitor 193 fourth capacitor 194

First assembly 195 second assembly 196

Third Assembly 197 fourth Assembly 198

Gate connection PP Gate connection NN

First current mirror 211 and second current mirror 212

Rail-to-rail differential input circuit 213

Input voltage signals INP, INN

PMOS transistor

2131,2132

NMOS transistor

2133,2134

First gain circuit 231 and second gain circuit 232

Floating AB control circuit 233

PMOS transistor

2311,2312

NMOS transistors

2321,2322

First compensation capacitor 251 and second compensation capacitor 252

P-type output transistor 271N-type output transistor 272

First capacitor 291 and second capacitor 292

First Assembly 295 second Assembly 296

Operational amplifier

41,51 load 43

Measurement point MP auxiliary operational amplifier 52

Waveforms

53,55,57

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 1 is a block diagram of an operational amplifier circuit according to the present invention, wherein the operational amplifier circuit includes an input stage circuit 11, a gain stage circuit 13, a compensation circuit 15, an output stage circuit 17 and a feedforward capacitor circuit 19. As shown, the input stage circuit 11 receives an input voltage signal, the gain stage circuit 13 is coupled to the input stage circuit 11 for increasing an output current of the input stage circuit 11, the compensation circuit 15 is coupled to the input stage circuit 11 and the output stage circuit 17, or further coupled to the gain stage circuit 13 for providing frequency compensation to maintain stability of the operational amplifier circuit and increase a Phase margin (Phase margin), the output stage circuit 17 is coupled to the gain stage circuit 13 for providing a gain output voltage signal, the feedforward capacitor circuit 19 is coupled to the output stage circuit 17 and the gain stage circuit 13, or further coupled to the input stage circuit 11 for detecting an output voltage response and using positive feedback to increase an instantaneous response speed of the operational amplifier circuit.

Fig. 2 further shows a circuit diagram of a first embodiment of the operational amplifier circuit of the present invention, in which the operational amplifier of the present embodiment is a Class AB operational amplifier (Class AB operational amplifier), in the present embodiment, the input stage circuit 11 includes a first current mirror 111, a second current mirror 112, a P-type differential input circuit 113, an N-type differential input circuit 114, a first active load 115 and a second active load 116, wherein the first current mirror 111, the P-type differential input circuit 113 and the first active load 115 are sequentially coupled together and connected between the power Voltage (VDD) and the ground Voltage (VSS), and the second active load 116, the N-type differential input circuit 114 and the second current mirror 112 are sequentially coupled together and connected between the power Voltage (VDD) and the ground Voltage (VSS); the first current mirror 111 and the second current mirror 112 provide constant current for circuit operation, wherein the current mirrors are known circuits in circuit design, and fig. 2 exemplarily shows that the current mirrors can be composed of two PMOS transistors or two NMOS transistors. The P-type differential input circuit 113 and the N-type differential input circuit 114 are used for receiving the input voltage signals VIN and VIP, wherein the differential input circuit is a circuit known in the circuit design, and fig. 2 exemplarily shows that the P-type differential input circuit 113 may be composed of two PMOS transistors, and the N-type differential input circuit 114 may be composed of two NMOS transistors. The first active load 115 and the second active load 116 exhibit a constant current nonlinear resistance characteristic as loads for differential input signals, wherein the active loads are conventional circuits in circuit design, and FIG. 2 exemplarily shows that the first active load 115 may be composed of four NMOS transistors 1151-1154, gates of the four NMOS transistors 1151-1154 are all connected to a node VN2, gates and drains of the NMOS transistors 1151 are connected together, the second active load 116 may be composed of four PMOS transistors 1161-1164, gates of the four PMOS transistors 1161-1164 are all connected to a node VP2, and gates and drains of the PMOS transistors 1162 are connected together.

The gain stage circuit 13 of the present embodiment includes a first gain circuit 131, a second gain circuit 132 and a floating class-AB control circuit 133, the first gain circuit 131, the floating class-AB control circuit 133 and the second gain circuit 132 are sequentially coupled together and connected between the power Voltage (VDD) and the ground Voltage (VSS), wherein the first gain circuit 131 is used to increase the current output by the second active load 116 of the input stage circuit 11, the second gain circuit 132 is used to increase the current output by the first active load 115 of the input stage circuit 11 to provide the driving current of the operational amplifier, the gain circuit is a known circuit in the circuit design, fig. 2 exemplarily shows that the first gain circuit 131 can be composed of two

PMOS transistors

1311,1312, and the gates of the two

PMOS transistors

1311,1312 are connected to the node VP1, the gates and the drains of the PMOS transistors 1311 are connected together, the second gain circuit 132 may be formed by two

NMOS transistors

1321,1322, wherein the gates of the two

NMOS transistors

1321,1322 are connected to the node VN1, and the gate and the drain of the NMOS transistor 1321 are connected together. The floating class-AB control circuit 133 is coupled to the first gain circuit 131 and the second gain circuit 132 for providing a floating current source to drive the first gain circuit 131 and the second gain circuit 132, wherein the floating class-AB control circuit is a known circuit in circuit design, and fig. 2 exemplarily shows that the floating class-AB control circuit 133 can be composed of four PMOS transistors and four NMOS transistors.

The compensation circuit 15 of the present embodiment includes a first compensation capacitor 151 and a second compensation capacitor 152, wherein the first compensation capacitor 151 is coupled between the second active load 116 of the input stage circuit 11 and the output stage circuit 17, the second compensation capacitor 152 is coupled between the first active load 115 of the input stage circuit 11 and the output stage circuit 17, and a stacked Miller frequency compensation scheme (stacked Miller frequency compensation scheme) is implemented by the first compensation capacitor 151 and the second compensation capacitor 152 to provide a compensated driving current to enhance a phase margin and reduce oscillation, so as to maintain stability of the operational amplifier circuit, as shown in the figure, one end of the first compensation capacitor 151 is connected to a connection point between a drain of the PMOS transistor 1163 of the second active load 116 and a source of the PMOS transistor 1164, the other end of the first compensation capacitor 151 is connected to a connection point between a drain of the P-type output transistor 171 and a drain of the N-type output transistor 172 in the output stage circuit 17, one end of the second compensation capacitor 152 is connected to a connection point between the source of the NMOS transistor 1153 and the drain of the NMOS transistor 1154 of the first active load 115, and the other end of the second compensation capacitor 151 is connected to a connection point between the drains of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17.

The output stage circuit 17 of the present embodiment includes a P-type output transistor 171 and an N-type output transistor 172 coupled together to provide the output voltage signal Vout with gain according to the compensated driving current, wherein the output stage circuit 17 is configured as: the drain of the P-type output transistor 171 is connected to the drain of the N-type output transistor 172, the gate of the P-type output transistor 171 is connected to the drain of the PMOS transistor 1312 of the first gain circuit 131 and the drain of the PMOS transistor 1164 of the second active load 116, the source of the P-type output transistor 171 is connected to the power supply Voltage (VDD), the gate of the N-type output transistor 172 is connected to the drain of the NMOS transistor 1322 of the second gain circuit 132 and the drain of the NMOS transistor 1153 of the first active load 115, and the source of the N-type output transistor 172 is connected to the ground Voltage (VSS).

The feedforward capacitor circuit 19 of the present embodiment includes a first capacitor 191, a second capacitor 192, a third capacitor 193, and a fourth capacitor 194, wherein one end of the first capacitor 191 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the first capacitor 191 is connected to the node VP1 of the first gain circuit 131 through a first component 195; one end of the second capacitor 192 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the second capacitor 192 is connected to the node VN1 of the second gain circuit 132 through a second component 196; one end of the third capacitor 193 is connected to the drain node of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the third capacitor 193 is connected to the node VP2 of the second active load 116 through a third element 197; one end of the fourth capacitor 194 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the fourth capacitor 194 is connected to the node VN2 of the first active load 115 through a fourth element 198. The first element 195, the second element 196, the third element 197 and the fourth element 198 are respectively impedances in a circuit, which may be wires, resistors, diodes, Metal Oxide Semiconductors (MOS), or the like.

By means of the first capacitor 191 and the second capacitor 192, the gain stage circuit 13 is driven to rapidly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout when the waveform of the output voltage signal Vout is rising instantaneously, and the gain stage circuit 13 is driven to rapidly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout when the waveform of the output voltage signal Vout is falling instantaneously. In detail, when the waveform of the output voltage Vout instantaneously rises, the high voltage is coupled to the node VP1 through the first capacitor 191 and the first device 195, and is coupled to the node VN1 through the second capacitor 192 and the second device 196, so that the voltage at the node VP1 rises due to the voltage coupling, and the voltage at the node VN1 rises due to the voltage coupling, which causes the PMOS transistor 1312 of the first gain circuit 131 to be turned off, the NMOS transistor 1322 of the second gain circuit 132 to be turned on, which indirectly causes the voltage at the gate connection PP of the P-type output transistor 171 to fall, and the voltage at the gate connection NN of the N-type output transistor 172 to turn on the P-type output transistor 171 of the output stage circuit 17 quickly to charge the output voltage signal Vout, thereby speeding up the rising time of the output voltage signal Vout. On the contrary, when the waveform of the output voltage signal Vout instantaneously falls, the low voltage is coupled to the node VP1 through the first capacitor 191 and the first device 195, and coupled to the node VN1 through the second capacitor 192 and the second device 196, so that the voltage at the node VP1 falls due to the voltage coupling, and the voltage at the node VN1 falls due to the voltage coupling, which causes the PMOS transistor 1312 of the first gain circuit 131 to be turned on, the NMOS transistor 1322 of the second gain circuit 132 to be turned off, which indirectly causes the voltage at the gate connection PP of the P-type output transistor 171 to rise, and the voltage at the gate connection NN of the N-type output transistor 172 to rise, thereby rapidly turning on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout, and further speeding up the falling time of the output voltage signal Vout.

Similarly, the third capacitor 193 and the fourth capacitor 194 can drive the input stage circuit 11 to rapidly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout when the waveform of the output voltage signal Vout is rising instantaneously, and drive the input stage circuit 11 to rapidly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout when the waveform of the output voltage signal Vout is falling instantaneously. In detail, when the waveform of the output voltage Vout instantaneously rises, the high voltage is coupled to the node VP2 through the third capacitor 193 and the third element 197, and is coupled to the node VN2 through the fourth capacitor 194 and the fourth element 198, so that the voltage of the node VP2 rises due to the voltage coupling, and the voltage of the node VN2 rises due to the voltage coupling, the PMOS transistor 1164 of the second active load 116 is turned off, the NMOS transistor 1153 of the first active load 115 is turned on, the voltage on the gate connection PP of the P-type output transistor 171 and the voltage on the gate connection NN of the N-type output transistor 172 indirectly fall, and the P-type output transistor 171 of the output stage circuit 17 is turned on quickly to charge the output voltage signal Vout, thereby increasing the time for the output voltage signal Vout to rise. On the contrary, when the waveform of the output voltage signal Vout instantaneously falls, the low voltage is coupled to the node VP2 through the third capacitor 193 and the third element 197 and coupled to the node VN2 through the fourth capacitor 194 and the fourth element 198, so that the voltage at the node VP2 falls due to the voltage coupling and the voltage at the node VN2 falls due to the voltage coupling, the PMOS transistor 1164 of the second active load 116 is turned on and the NMOS transistor 1153 of the first active load 115 is turned off, which indirectly causes the voltage at the gate connection PP of the P-type output transistor 171 and the voltage at the gate connection NN of the N-type output transistor 172 to quickly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout, thereby speeding up the falling time of the output voltage signal Vout.

In the circuit of the present embodiment, the instantaneous response speed of the operational amplifier can be increased only by the first capacitor 191 and the second capacitor 192, but when the operational amplifier is configured in a unity gain (unity gain) mode, and the difference between the output voltage signal Vout and the input voltage signal VIN, VIP is too large, the input stage circuit 11 and the gain stage circuit 13 will pull each other, resulting in the occurrence of spike interference (glitch) in the output waveform and the unsmooth, so the instantaneous response speed of the operational amplifier needs to be increased by the third capacitor 193 and the fourth capacitor 194 at the same time, and the third capacitor 193 and the fourth capacitor 194 are designed to be larger than the first capacitor 191 and the second capacitor 192, so as to avoid the unsmooth output voltage.

FIG. 3 is a circuit diagram of a second embodiment of an operational amplifier circuit according to the present invention, in which the operational amplifier of the present embodiment is a cross-coupled class AB operational amplifier (FOLD cascode class AB operational amplifier), in the present embodiment, the input stage circuit 11 includes a first current mirror 211, a second current mirror 212 and a rail-to-rail differential input circuit 213, wherein the first current mirror 211, the rail-to-rail differential input circuit 213 and the second current mirror 212 are sequentially coupled together and connected between a power Voltage (VDD) and a ground Voltage (VSS); the first current mirror 211 and the second current mirror 212 provide constant current for circuit operation, wherein the current mirrors are known circuits in circuit design, and fig. 3 exemplarily shows that the current mirrors may be formed by one PMOS transistor or one NMOS transistor. The rail-to-rail differential input circuit 213 is used for receiving the input voltage signals INP, INN, wherein the rail-to-rail differential input circuit is a circuit known in the circuit design, and fig. 3 exemplarily shows that the rail-to-rail differential input circuit 213 can be composed of two

PMOS transistors

2131,2132 and two

NMOS transistors

2133,2134.

The gain stage circuit 13 of the present embodiment includes a first gain circuit 231, a second gain circuit 232 and a floating class-AB control circuit 233, wherein the first gain circuit 231, the floating class-AB control circuit 233 and the second gain circuit 232 are coupled together in sequence and connected between the power Voltage (VDD) and the ground Voltage (VSS), the first gain circuit 231 is used to increase the current output by the rail-to-rail differential input circuit 213 of the input stage circuit 11, the second gain circuit 232 is used to increase the current output by the rail-to-rail differential input circuit 213 of the input stage circuit 11 to provide the driving current of the operational amplifier, wherein the gain circuit is a circuit known in the circuit design, fig. 3 exemplarily shows that the first gain circuit 231 can be composed of two PMOS transistors 2311,2312, and the gates of the two PMOS transistors 2311,2312 are connected to a node VP1, the gates and the drains of the PMOS transistors 2311 are connected together, the second gain circuit 231 may be composed of two NMOS transistors 2321,2322, and the gates of the two NMOS transistors 2321,2322 are connected to a node VN1, and the gate and the drain of the NMOS transistor 2321 are connected together. The floating class-AB control circuit 233 is coupled to the first gain circuit 231 and the second gain circuit 232, and is used to provide a floating current source to drive the first gain circuit 231 and the second gain circuit 232, wherein the floating class-AB control circuit is a known circuit in circuit design, and fig. 3 exemplarily shows that the floating class-AB control circuit 233 can be composed of four PMOS transistors and four NMOS transistors.

The compensation circuit 15 of the present embodiment includes a first compensation capacitor 251 and a second compensation capacitor 252, wherein the first compensation capacitor 251 is coupled between the rail-to-rail differential input circuit 213 of the input stage circuit 11 and the first gain circuit 231 of the gain stage circuit 13 and the output stage circuit 17, and the second compensation capacitor 252 is coupled between the rail-to-rail differential input circuit 213 of the input stage circuit 11 and the second gain circuit 232 of the gain stage circuit 13 and the output stage circuit 17, so that a stacked Miller frequency compensation scheme (stacked Miller frequency compensation scheme) is implemented by the first compensation capacitor 251 and the second compensation capacitor 252 to provide a compensated driving current, so as to enhance the phase margin and reduce the oscillation, thereby maintaining the stability of the operational amplifier circuit. As shown, one end of the first compensation capacitor 251 is connected to the drain of the NMOS transistor 2133 of the rail-to-rail differential input circuit 213 and the drain of the PMOS transistor 2312 of the first gain circuit 231, the other end of the first compensation capacitor 251 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, one end of the second compensation capacitor 252 is connected to the drain of the PMOS transistor 2131 of the rail-to-rail differential input circuit 213 and the drain of the NMOS transistor 2322 of the second gain circuit 232, and the other end of the second compensation capacitor 252 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17.

The output stage circuit 17 of the present embodiment includes a P-type output transistor 271 and an N-type output transistor 272 coupled together to provide a gain output voltage signal Vout according to the compensated driving current, wherein the output stage circuit 17 is configured to: the drain of the P-type output transistor 271 is connected to the drain of the N-type output transistor 272, the gate of the P-type output transistor 271 is connected to the drain of the PMOS transistor 2312 of the first gain circuit 231, the source of the P-type output transistor 271 is connected to the power supply Voltage (VDD), the gate of the N-type output transistor 272 is connected to the drain of the NMOS transistor 2322 of the second gain circuit 232, and the source of the N-type output transistor 272 is connected to the ground Voltage (VSS).

The feed-forward capacitor circuit 19 of the present embodiment includes a first capacitor 291 and a second capacitor 292, wherein one end of the first capacitor 291 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, and the other end of the first capacitor 291 is connected to the node VP1 of the first gain circuit 231 through a first component 295; one end of the second capacitor 292 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, and the other end of the second capacitor 292 is connected to the node VN1 of the second gain circuit 232 via a second component 296. The first and

second elements

295 and 296 are resistors in a circuit, which may be wires, resistors, diodes, or Metal Oxide Semiconductors (MOS).

With the first capacitor 291 and the second capacitor 292, the gain stage circuit 13 is driven to rapidly turn on the P-type output transistor 271 of the output stage circuit 17 to charge the output voltage signal Vout when the waveform of the output voltage signal Vout is rising instantaneously, and the gain stage circuit 13 is driven to rapidly turn on the N-type output transistor 272 of the output stage circuit 17 to discharge the output voltage signal Vout when the waveform of the output voltage signal Vout is falling instantaneously. In detail, when the waveform of the output voltage Vout instantaneously rises, the high voltage is coupled to the node VP1 through the first capacitor 291 and the first device 295, and is coupled to the node VN1 through the second capacitor 292 and the second device 296, so that the voltage of the node VP1 rises due to the voltage coupling, and the voltage of the node VN1 rises due to the voltage coupling, which causes the PMOS transistor 2312 of the first gain circuit 231 to be turned off, the NMOS transistor 2322 of the second gain circuit 232 to be turned on, which indirectly causes the voltage on the gate connection PP of the P-type output transistor 271 to fall, and the voltage on the gate connection NN of the N-type output transistor 272 to fall, so as to quickly turn on the P-type output transistor 271 of the output stage circuit 17 to charge the output voltage Vout, thereby speeding up the rising time of the output voltage Vout. On the contrary, when the waveform of the output voltage signal Vout instantaneously falls, the low voltage is coupled to the node VP1 through the first capacitor 291 and the first device 295, and coupled to the node VN1 through the second capacitor 292 and the second device 296, so that the voltage at the node VP1 falls due to the voltage coupling, and the voltage at the node VN1 falls due to the voltage coupling, which causes the PMOS transistor 2312 of the first gain circuit 231 to be turned on, the NMOS transistor 2322 of the second gain circuit 232 to be turned off, which indirectly causes the voltage at the gate connection PP of the P-type output transistor 271 to rise and the voltage at the gate connection NN of the N-type output transistor 272 to rise, thereby rapidly turning on the N-type output transistor 272 of the output stage circuit 17 to discharge the output voltage signal Vout, and further speeding up the falling time of the output voltage signal Vout.

To prove the excellent effect of the invention, Hspice simulation software is used for verifying and comparing the instantaneous reaction speed under the condition of adding the feedforward capacitor with the instantaneous reaction speed under the condition of not adding the feedforward capacitor. As shown in fig. 4, under the condition that the difference between the input voltage signals of the operational amplifier is 0.2V to 4.8V, the load 43 (RL: 20K, CL: 200 pF) with the fifth-order resistor (R) and the capacitor (C) added to the output of the operational amplifier 41 measures the instantaneous response speed of the output from the 0.2V transition state to 4.8V, and the measurement point MP is the front end of the fifth-order RC with the percentage of the output waveform voltage (10% to 90%, 1% to 99%).

When the simulated operational amplifier 41 is based on the operational amplifier circuit of the first embodiment of fig. 2, the measured output voltages are 10% to 90% and 1% to 99%, and the results are shown in tables 1 and 2:

TABLE 1

TABLE 2

As shown in tables 1 and 2, the first embodiment of the present invention can increase the instantaneous response speed by 167-331 ns when the percentage of the measured output voltage is 10% -90%, and can increase the instantaneous response speed by 95-258 ns when the percentage of the measured output voltage is 1% -99%.

When the simulated operational amplifier 41 is based on the operational amplifier circuit of the second embodiment of fig. 3, the measured output voltages were in the percentages of 10% to 90% and 1% to 99%, and the results obtained are shown in tables 3 and 4:

TABLE 3

TABLE 4

As shown in tables 3 and 4, the second embodiment of the present invention can increase the instantaneous response speed of 227-266 ns when the percentage of the measured output voltage is 10-90%, and can increase the instantaneous response speed of 222-269 ns when the percentage of the measured output voltage is 1-99%.

In addition, since the present invention utilizes the coupling phenomenon of the feedforward capacitor to speed up the transient time of the operational amplifier, it has a better effect when the waveform of the input voltage signal is a steep waveform, if the waveform of the input voltage signal is a rounded waveform, as shown in fig. 5, an auxiliary operational amplifier 52 can be added at the input end of the operational amplifier 51 (i.e. the input end of the input stage circuit 11) implemented by the operational amplifier circuit of the present invention, the waveform of the input voltage signal is corrected by the auxiliary operational amplifier 52 to change the rounded waveform into a steep waveform, so as to exert the excellent effect of the present invention, for example, if the waveform 53 of the input voltage signal is RC charging and discharging, it can be equivalent to a rounded waveform of two steep segments, the two steep segments can be corrected into a corrected waveform 55 of one steep segment by the waveform correction of the auxiliary operational amplifier 52, therefore, the coupling amount of the operational amplifier 51 of the feedforward capacitor of the present invention is greatly increased, and the instantaneous response speed of the waveform 57 of the output voltage signal of the operational amplifier 51 is increased.

The above-described embodiments are merely exemplary for convenience in explanation, and the scope of the claims of the present invention should be determined by the claims rather than by the limitations of the above-described embodiments.

Claims

1. An operational amplifier circuit, comprising:

an input stage circuit for receiving an input voltage signal;

a gain stage circuit coupled to the input stage circuit;

an output stage circuit, coupled to the gain stage circuit, for providing an output voltage signal, wherein the output stage circuit includes a P-type output transistor and an N-type output transistor, and drains of the P-type output transistor and the N-type output transistor are connected together;

a compensation circuit coupled to the input stage circuit and the output stage circuit; and

and the feedforward capacitor circuit comprises a first capacitor and a second capacitor and is used for driving the gain stage circuit to quickly start a P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantaneously, and driving the gain stage circuit to quickly start an N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal falls instantaneously.

2. The operational amplifier circuit of claim 1, wherein the gain stage circuit comprises a first gain circuit, a floating class AB control circuit and a second gain circuit coupled together in sequence, wherein the first gain circuit comprises two PMOS transistors having gates connected to a first node, the second gain circuit comprises two NMOS transistors having gates connected to a second node.

3. The operational amplifier circuit as claimed in claim 2, wherein one end of the first capacitor is connected to the drain connection points of the P-type and N-type output transistors, the other end of the first capacitor is connected to the first node through a first component, one end of the second capacitor is connected to the drain connection points of the P-type and N-type output transistors, and the other end of the second capacitor is connected to the second node through a second component.

4. The operational amplifier circuit as claimed in claim 3, wherein the input stage circuit comprises a first current mirror, a P-type differential input circuit and a first active load coupled together in sequence, and a second active load, an N-type differential input circuit and a second current mirror coupled together in sequence, wherein the second active load is formed by four PMOS transistors having their gates connected to a third node, the first active load is formed by four NMOS transistors having their gates connected to a fourth node.

5. The operational amplifier circuit as claimed in claim 4, wherein the compensation circuit comprises a first compensation capacitor and a second compensation capacitor, the first compensation capacitor is coupled between the second active load and the drain connection points of the P-type output transistor and the N-type output transistor, and the second compensation capacitor is coupled between the first active load and the drain connection points of the P-type output transistor and the N-type output transistor.

6. The operational amplifier circuit as claimed in claim 4, wherein the feedforward capacitance circuit further comprises a third capacitor and a fourth capacitor for driving the input stage circuit to rapidly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal is rising instantaneously, and driving the input stage circuit to rapidly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal is falling instantaneously.

7. The operational amplifier circuit as claimed in claim 6, wherein one terminal of the third capacitor is connected to the drain connection points of the P-type and N-type output transistors, the other terminal of the third capacitor is connected to the third node through a third element, one terminal of the fourth capacitor is connected to the drain connection points of the P-type and N-type output transistors, and the other terminal of the fourth capacitor is connected to the fourth node through a fourth element.

8. The operational amplifier circuit as set forth in claim 4, wherein the gate of the P-type output transistor is connected to the drain of a PMOS transistor of the first gain circuit and the drain of a PMOS transistor of the second active load, and the gate of the N-type output transistor is connected to the drain of an NMOS transistor of the second gain circuit and the drain of an NMOS transistor of the first active load.

9. The operational amplifier circuit of claim 7, wherein said first element, said second element, said third element and said fourth element comprise a wire, a resistor, a diode or a Metal Oxide Semiconductor (MOS).

10. The operational amplifier circuit of claim 3, wherein the input stage circuit comprises a first current mirror, a rail-to-rail differential input circuit, and a second current mirror coupled together in sequence.

11. The operational amplifier circuit as set forth in claim 10, wherein the compensation circuit comprises a first compensation capacitor coupled between the rail-to-rail differential input circuit and the first gain circuit and the drain connection points of the P-type output transistor and the N-type output transistor, and a second compensation capacitor coupled between the rail-to-rail differential input circuit and the second gain circuit and the drain connection points of the P-type output transistor and the N-type output transistor.

12. The operational amplifier circuit as set forth in claim 10, wherein the gate of the P-type output transistor is connected to the drain of a PMOS transistor of the first gain circuit, and the gate of the N-type output transistor is connected to the drain of an NMOS transistor of the second gain circuit.

13. The operational amplifier circuit of claim 10, wherein said first element and said second element comprise a wire, a resistor, a diode, or a Metal Oxide Semiconductor (MOS).

14. The operational amplifier circuit as claimed in claim 1, further comprising an auxiliary operational amplifier disposed at an input of the input stage circuit.