CN220492858U - Push-pull type output circuit for preventing reverse input electric leakage - Google Patents
Push-pull type output circuit for preventing reverse input electric leakage Download PDFInfo
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- CN220492858U CN220492858U CN202322047230.0U CN202322047230U CN220492858U CN 220492858 U CN220492858 U CN 220492858U CN 202322047230 U CN202322047230 U CN 202322047230U CN 220492858 U CN220492858 U CN 220492858U
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- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model relates to the field of push-pull circuit operation, in particular to a push-pull output circuit for preventing reverse input electric leakage, which comprises an upper tube circuit and a lower tube circuit, wherein the upper tube circuit and the lower tube circuit are electrically connected, and output is high level when the input voltages of the upper tube circuit and the lower tube circuit are both high level; when the input voltages of the upper tube circuit and the lower tube circuit are both low levels, outputting the low levels; when the power supply voltage of the output electrode is 0 and the output is high, the voltage of the substrate is increased, the diode in the upper tube circuit is conducted in the forward direction, no leakage current exists between the drain electrode and the substrate, and the power supply of the output electrode is protected. The utility model solves the problem that when the power supply voltage of the output electrode is 0V and the high level is applied to the output end, a large leakage current is generated, and the output electrode circuit can be burnt out seriously.
Description
Technical Field
The utility model relates to the technical field of push-pull circuits, in particular to a push-pull output circuit for preventing reverse input leakage.
Background
The push-pull digital IO circuit is a common circuit structure and can be used for amplifying signals, driving loads and other various application occasions; an upper tube and a lower tube circuit are generally formed by a PNP type transistor and an NPN type transistor, and an input signal is amplified through the transistors and output to a load; the upper pipe and the lower pipe work alternately to realize the driving of the load.
In the push-pull digital IO circuit, when the power supply voltage of the output electrode is 0v and the high level is applied to the output end, since the substrate of the PMOS transistor is connected to the power supply (0 v at this time), vdb of the PMOS transistor is larger than the forward conduction voltage of the diode parasitic between the drain of the PMOS transistor and the substrate, so that a large leakage current is generated from the drain of the PMOS transistor to the substrate, and the output electrode circuit may be burned out in severe cases.
Disclosure of Invention
In order to overcome the problems existing in the existing circuit, the utility model adopts the following technical scheme: a push-pull output circuit for preventing reverse input leakage, comprising: the upper tube circuit is electrically connected with the lower tube circuit, when the power supply voltage of the output electrode is 0V and the output VO is at a high level, the substrate voltage of the upper tube circuit is increased, a diode in the upper tube circuit is conducted forward, no leakage current exists between the drain electrode of the upper tube circuit and the substrate, and the output electrode power supply VCCIO is protected.
Further, the method further comprises the following steps: when the input voltages VIP and VIN of the upper tube circuit and the lower tube circuit are both high levels, the output VO is high level; when the input voltages VIP and VIN of the upper tube circuit and the lower tube circuit are both low levels, the output VO is low level; the input voltage polarity of the upper tube circuit and the lower tube circuit is synchronously controlled to synchronously change the output voltage, so that the function of driving the load circuit is realized.
Further, the upper tube circuit includes: the positive electrode of the diode D1 is connected with the drain electrode of the PMOS tube P2, the negative electrode of the diode D1 is connected with the drain electrode of the PMOS tube P1 after being connected with an output electrode power supply VCCIO, the positive electrode of the diode D1 is also respectively connected with the substrates of the PMOS tube P1 and the PMOS tube P2, and the common end of the grid electrode of the PMOS tube P1 and the source electrode of the PMOS tube P2 is grounded after being connected with the resistor R1; the grid electrode of the PMOS tube P2 is connected with the input voltage.
Further, the down tube circuit includes: the common end of the drain electrode of the NMOS tube N1 and the source electrode of the PMOS tube P1 is connected with the load output end, the common end of the gate electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 is connected with the resistor R2 and then grounded, and the common ends of the source electrode of the NMOS tube N1 and the source electrode of the NMOS tube N2 are grounded; the gate of the NMOS transistor N2 is connected with the input voltage.
Further, the types of the PMOS tube P1 and the PMOS tube P2 include, but are not limited to, SI2323DS-T1.
Further, the types of NMOS tube N1 and NMOS tube N2 include, but are not limited to, si2302DDS.
Further, the model of diode D1 includes, but is not limited to, S1A-S1M.
The utility model has the beneficial effects that:
1. by adding diode D1 and connecting the substrates of P2 and P1, the drain does not generate a large leakage current to the substrate when the output electrode power supply voltage is 0V and the output terminal is connected to the high level, and the output electrode power supply VCCIO can be protected.
Drawings
FIG. 1 is a schematic diagram of a push-pull output circuit for preventing reverse input leakage in accordance with the present utility model;
wherein, 1, upper tube circuit; 2. and a down tube circuit.
Detailed Description
The utility model will now be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, a push-pull output circuit for preventing reverse input leakage includes: the upper tube circuit 1 and the lower tube circuit 2 are electrically connected, and when the inputs VIP and VIN of the upper tube circuit 1 and the lower tube circuit 2 are both high levels, the output VO is high level; the output VO is low when the inputs VIP and VIN of the upper tube circuit 1 and the lower tube circuit 2 are both low; when the output electrode power supply voltage VCCIO is 0 and the output VO is at a high level, the substrate voltage rises, the diode in the upper tube circuit 1 is conducted in the forward direction, no leakage current exists between the drain electrode and the substrate, and the output electrode power supply is protected.
The upper tube circuit 1 includes: the positive electrode of the diode D1 is connected with the drain electrode of the PMOS tube P2, the negative electrode of the diode D1 is connected with the drain electrode of the PMOS tube P1 after being connected with an output electrode power supply VCCIO, the positive electrode of the diode D1 is also respectively connected with the substrates of the PMOS tube P1 and the PMOS tube P2, and the common end of the grid electrode of the PMOS tube P1 and the source electrode of the PMOS tube P2 is grounded after being connected with the resistor R1; the gate of the PMOS transistor P2 is connected to the input voltage VIP.
The down tube circuit 2 includes: the common end of the drain electrode of the NMOS tube N1 and the source electrode of the PMOS tube P1 is connected with the load output end VO, the common end of the gate electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 is connected with the resistor R2 and then grounded, and the common ends of the source electrode of the NMOS tube N1 and the source electrode of the NMOS tube N2 are grounded; the gate of the NMOS transistor N2 is connected to the input voltage VIN.
Working principle:
when the circuit works normally, VIP and VIN are in-phase signals, when VIP is in high level, VIN is in high level, the PMOS tube P2 is closed, the grid electrode of the PMOS tube P1 is connected with GND through the resistor R1, and the PMOS tube P1 is conducted; the NMOS tube N2 is on, the grid electrode of the NMOS tube N1 is connected with GND through the NMOS tube N2, and the NMOS tube N1 is off, so that the output VO is VCCIO high level.
When VIP is low level and VIN is low level, the PMOS tube P2 is conducted, the grid electrode of the PMOS tube P1 is connected with VCCIO-0.2V (0.2V is the forward conducting voltage of the Schottky diode D1) through the PMOS tube P2, and the PMOS tube P1 is turned off; the NMOS tube N2 is turned off, the grid electrode of the NMOS tube N1 is connected with VCCIO through a resistor R2, and the NMOS tube N1 is turned on, so that the output VO is GND low level.
When VCCIO is 0V, VO is connected with the output of the peripheral circuit connected with the VCCIO, and the drain voltage of the PMOS tube P1 is higher than the substrate voltage of the PMOS tube P1 under the assumption that VO is 3.3V; since the diode D1 is reversely biased and the D1 tube is in an off state, the substrate voltage of the PMOS tube P1 is raised to 3.3V-0.2V along with VO. The parasitic diode D1 between the drain of the PMOS transistor P1 and the substrate is turned on in the forward direction, but no current path is provided, so that a large leakage current is not generated.
With the above-described preferred embodiments according to the present utility model as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present utility model. The technical scope of the present utility model is not limited to the description, but must be determined according to the scope of claims.
Claims (4)
1. A push-pull output circuit for preventing reverse input leakage, characterized by: the diode is connected in a forward direction, no leakage current exists between the drain electrode and the substrate, and the output electrode power supply is protected;
further comprises: when the input voltages of the upper tube circuit and the lower tube circuit are both high levels, outputting the high levels; when the input voltages of the upper tube circuit and the lower tube circuit are both low levels, outputting the low levels;
the upper tube circuit includes: the positive electrode of the diode D1 is connected with the drain electrode of the PMOS tube P2, the negative electrode of the diode D1 is connected with the drain electrode of the PMOS tube P1 after being connected with an output electrode power supply VCCIO, the positive electrode of the diode D1 is also respectively connected with the substrates of the PMOS tube P1 and the PMOS tube P2, and the common end of the grid electrode of the PMOS tube P1 and the source electrode of the PMOS tube P2 is grounded after being connected with the resistor R1;
the down tube circuit includes: the common end of the drain electrode of the NMOS tube N1 and the source electrode of the PMOS tube P1 is connected with the load output end, the common end of the gate electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 is connected with the resistor R2 and then grounded, and the common ends of the source electrode of the NMOS tube N1 and the source electrode of the NMOS tube N2 are grounded.
2. The push-pull output circuit for preventing reverse input leakage as claimed in claim 1, wherein: the model of the PMOS tube P1 and the model of the PMOS tube P2 are SI2323DS-T1.
3. The push-pull output circuit for preventing reverse input leakage as claimed in claim 1, wherein: the model of the NMOS tube N1 and the model of the NMOS tube N2 are Si2302DDS.
4. The push-pull output circuit for preventing reverse input leakage as claimed in claim 1, wherein: the diode D1 is of the type S1A-S1M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322047230.0U CN220492858U (en) | 2023-07-31 | 2023-07-31 | Push-pull type output circuit for preventing reverse input electric leakage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322047230.0U CN220492858U (en) | 2023-07-31 | 2023-07-31 | Push-pull type output circuit for preventing reverse input electric leakage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220492858U true CN220492858U (en) | 2024-02-13 |
Family
ID=89828893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322047230.0U Active CN220492858U (en) | 2023-07-31 | 2023-07-31 | Push-pull type output circuit for preventing reverse input electric leakage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220492858U (en) |
-
2023
- 2023-07-31 CN CN202322047230.0U patent/CN220492858U/en active Active
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