CN116760371B - Bias circuit for rail-to-rail input operational amplifier - Google Patents
Bias circuit for rail-to-rail input operational amplifier Download PDFInfo
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- CN116760371B CN116760371B CN202311009087.4A CN202311009087A CN116760371B CN 116760371 B CN116760371 B CN 116760371B CN 202311009087 A CN202311009087 A CN 202311009087A CN 116760371 B CN116760371 B CN 116760371B
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- 238000010586 diagram Methods 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45051—Two or more differential amplifiers cascade coupled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45056—One or both transistors of the cascode stage of a differential amplifier being composed of more than one transistor
Abstract
The invention discloses a bias circuit for a rail-to-rail input operational amplifier, which comprises two MOS (metal oxide semiconductor) tubes, a resistor and a current source, wherein the source electrode of a first MOS tube is connected with the drain electrode of a second MOS tube, and the drain electrode of the first MOS tube is connected between a power supply and the ground after being sequentially connected with the resistor and the current source; the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are connected to the P-type load tube or the N-type load tube and used for providing bias voltage. After the bias circuit adopts the scheme, the common-gate current mirror is realized in a self-adaptive control mode, and bias current which is not influenced by input common-mode voltage and input to a tail current source is provided for a later-stage circuit, so that the bias state of an output stage and the overall performance of the operational amplifier are stable.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a bias circuit for a rail-to-rail input operational amplifier.
Background
The rail-to-rail input operational amplifier mainly comprises a rail-to-rail input stage, a Class-AB output control circuit, a P-type load tube, an N-type load tube and a Class-AB output stage, wherein the output end of the rail-to-rail input stage is respectively connected to the P-type load tube and the N-type load tube, the input end of the Class-AB output control circuit is respectively connected with the P-type load tube and the N-type load tube, the output end of the Class-AB output control circuit is connected with the Class-AB output stage, and the output end of the Class-AB output stage is used as the output end OUT of the operational amplifier.
When the rail-to-rail input operational amplifier works, when an input signal of the rail-to-rail input operational amplifier is close to a positive power rail and a negative power rail, working states of a P input pair transistor, an N input pair transistor and corresponding tail current sources in the rail-to-rail input stage are changed, so that bias current distribution of circuits of the later stages of the operational amplifier load transistor and the like is changed, and parameters such as static power consumption, offset voltage and the like of the operational amplifier output stage are caused to fluctuate, and performance stability of the operational amplifier in a full common mode input range is affected.
In order to make the operational amplifier work normally, the input signal is amplified without distortion, a proper and stable static working point is needed in the operational amplifier circuit, and the bias circuit is used for providing direct current and direct voltage for the operational amplifier circuit, which is also called direct current (static) bias circuit. The bias voltage can be provided by setting a bias circuit of the P-type load tube or the N-type load tube.
Fig. 1 shows a specific implementation form of a bias circuit of a conventional P-type load tube, in which a rail-to-rail input stage adopts a combination structure of PMOS input pair tubes and NMOS input pair tubes, specifically including NMOS tubes NM10, NM20, PMOS tubes PM10, PM20, and tail current sources I110, I120, a gate connection INN of NM10, a gate connection INP of NM20, a source of NM10 and a source of NM20 are connected together and are connected to an input end of I110, and an output end of I110 is grounded; the gate of PM10 is connected with INN, the gate of PM20 is connected with INP, the source of PM10 is connected with the source of PM20, and is commonly connected to the output end of I120, and the input end of I120 is connected with a power supply;
the P-type load tube comprises PMOS tubes PM 30-PM 60, wherein the source electrode of the PM30 and the source electrode of the PM40 are both connected to a power supply; the drain of PM30 is connected to the source of PM50 and commonly connected to the drain of NM 10; the drain of PM40 is connected to the source of PM60 and commonly connected to the drain of NM 20; the drain of PM60 is connected to a Class-AB output control circuit;
the N-type load tube comprises NMOS tubes NM 30-NM 60, wherein a grid electrode of NM30 is connected with a grid electrode of NM40, and a grid electrode of NM50 is connected with a grid electrode of NM 60; the drain electrode of the NM30 is connected with the drain electrode of the PM50, and the drain electrode of the NM40 is connected to a Class-AB output control circuit; the source of NM30 is connected to the drain of NM50 and commonly connected to the drain of PM 10; the source of NM40 is connected to the drain of NM60 and commonly connected to the drain of PM 20; the source of NM50 and the source of NM60 are both grounded;
the Class-AB output stage comprises a PMOS tube PM70 and an NMOS tube NM70, wherein the source electrode of the PM70 is connected with a power supply, the grid electrode of the PM70 is connected to a Class-AB output control circuit, the source electrode of the NM70 is grounded, and the grid electrode of the NM70 is connected to the Class-AB output control circuit; the drain of PM70 is connected to the drain of NM70 and serves as the output OUT of the operational amplifier.
The bias circuit comprises PMOS tubes PM80 and PM90, a resistor R10 and a current source I130, wherein the source electrode of the PM80 is connected with a power supply, the grid electrode of the PM80 is respectively connected with the grid electrode of the PM30, the grid electrode of the PM40 and the drain electrode of the PM90, the drain electrode of the PM90 is connected with the source electrode of the PM90, and the grid electrode of the PM90 is respectively connected with the grid electrode of the PM50 and the grid electrode of the PM 60; one end of R10 is connected with the drain electrode of PM90, the other end of R10 is respectively connected with the grid electrode of PM90 and the input end of I130, and the output end of I130 is grounded.
I130, R10, PM90 and PM80 form a bias circuit of the P-type load tube, and provide bias voltage for the P-type load tube. Wherein, PM80 and PM30, PM40 constitute the current mirror, and the width-to-length ratio of PM80 to PM40 determines the magnitude of the currents I0 and I1, that is to say the magnitude of the current of current source I130 is equal to the magnitude of the current I0 flowing through PM80, and the current mirror formed by PM80 and PM40 determines the magnitude of the current I1. When the input common mode range is high to a certain voltage, NM10 and NM20 of the NMOS input pair tube work normally, wherein the current flowing through NM20 is recorded as I2, and at the moment, the current I3 = I1-I2 flowing through PM60 and Class AB output control circuit; when the input common mode range is close to the ground, NM10 and NM20 enter the off state, and no current flows through NM20, i.e. i2=0 at this time, then the current i3=i1 flowing through the PM60 and the Class AB output control circuit, and the magnitude of the current flowing through the Class AB output control section determines the static power consumption of the output stage, thereby affecting the output stage impedance.
From the above analysis, when NM10 and NM20 are in normal operation and enter into cut-off state, the current flowing through the Class AB output control circuit changes, and the current I2 flowing into NM20 is generally larger, so that the static power consumption of the output stage changes greatly, resulting in a large change of the output impedance, and affecting the stability of the operational amplifier.
Disclosure of Invention
The invention aims to provide a bias circuit for a rail-to-rail input operational amplifier, which can realize the bias state of an output stage and the stability of the overall performance of the operational amplifier.
In order to achieve the above object, the solution of the present invention is:
the bias circuit for the rail-to-rail input operational amplifier comprises a rail-to-rail input stage, a Class-AB output control circuit, a P-type load tube, an N-type load tube and a Class-AB output stage, wherein the P-type load tube comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected to a power supply; the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the sixth PMOS tube is connected to the Class-AB output control circuit;
the bias circuit comprises a first amplifier, an eighth PMOS tube, a ninth PMOS tube, a first resistor and a third current source, wherein the output end of the first amplifier is respectively connected with the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube, the positive input end of the first amplifier is connected with the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube, and the negative input end of the first amplifier is connected with the drain electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the source electrode of the eighth PMOS tube is connected with a power supply, the grid electrode of the eighth PMOS tube, the drain electrode of the ninth PMOS tube and one end of the first resistor are connected, the grid electrode of the ninth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the grid electrode of the ninth PMOS tube is also respectively connected with the other end of the first resistor and the input end of the third current source; the output end of the third current source is grounded.
The rail-to-rail input stage comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first tail current source and a second tail current source, wherein the grid electrode of the first NMOS tube is connected with an inverted input end INN, the grid electrode of the second NMOS tube is connected with a forward input end INP, the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and is commonly connected with the input end of the first tail current source, and the output end of the first tail current source is grounded; the grid electrode of the first PMOS tube is connected with the inverting input end INN, the grid electrode of the second PMOS tube is connected with the forward input end INP, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is commonly connected to the output end of the second tail current source, and the input end of the second tail current source is connected with a power supply; the drain electrode of the first PMOS tube is connected to the N-type load tube, and the drain electrode of the second PMOS tube is connected to the N-type load tube;
the drain electrode of the first NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the source electrode of the fifth PMOS tube, and the drain electrode of the second NMOS tube is respectively connected with the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube.
The N-type load tube comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and is connected to the drain electrode of the third NMOS tube; the drain electrode of the third NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fourth NMOS tube is connected to the Class-AB output control circuit; the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are grounded.
The Class-AB output stage comprises a seventh PMOS tube and a seventh NMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a power supply, the grid electrode of the seventh PMOS tube is connected to a Class-AB output control circuit, the source electrode of the seventh NMOS tube is grounded, and the grid electrode of the seventh NMOS tube is connected to the Class-AB output control circuit; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube and is used as the output end OUT of the operational amplifier.
The bias circuit for the rail-to-rail input operational amplifier comprises a rail-to-rail input stage, a Class-AB output control circuit, a P-type load tube, an N-type load tube and a Class-AB output stage, wherein the N-type load tube comprises a first three NMOS tube, a first four NMOS tube, a first five NMOS tube and a first six NMOS tube, the grid electrode of the first three NMOS tube is connected with the grid electrode of the first four NMOS tube, and the grid electrode of the first five NMOS tube is connected with the grid electrode of the first six NMOS tube; the drain electrode of the first NMOS tube is connected to the P-type load tube, and the drain electrode of the first NMOS tube is connected to the Class-AB output control circuit; the source electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the first fourth NMOS tube is connected with the drain electrode of the first sixth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the first fifth NMOS tube and the source electrode of the first sixth NMOS tube are grounded;
the bias circuit comprises a second amplifier, a first eighth NMOS tube, a first ninth NMOS tube, a second resistor and a first third current source, wherein the output end of the second amplifier is respectively connected with the grid electrode of the first fifth NMOS tube and the grid electrode of the first sixth NMOS tube, the negative input end of the second amplifier is respectively connected with the source electrode of the first fourth NMOS tube and the drain electrode of the first sixth NMOS tube, and the positive input end of the second amplifier is respectively connected with the source electrode of the first eighth NMOS tube and the drain electrode of the first ninth NMOS tube; the input end of the first third current source is connected with a power supply, the output end of the first third current source is respectively connected with one end of the second resistor and the grid electrode of the first eighth NMOS tube, and the grid electrode of the first eighth NMOS tube is also respectively connected with the grid electrode of the first third NMOS tube and the grid electrode of the first fourth NMOS tube; the other end of the second resistor is respectively connected with the drain electrode of the first eighth NMOS tube and the grid electrode of the first ninth NMOS tube; the source electrode of the first nine NMOS tubes is grounded.
The rail-to-rail input stage comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first diode NMOS tube, a first PMOS tube, a first diode PMOS tube, a first tail current source and a first diode tail current source, wherein a grid electrode of the first NMOS tube is connected with an inverted input end INN, a grid electrode of the first diode NMOS tube is connected with a forward input end INP, a source electrode of the first NMOS tube is connected with a source electrode of the first diode NMOS tube and is commonly connected with an input end of the first diode tail current source, and an output end of the first diode tail current source is grounded; the grid electrode of the first one-to-one PMOS tube is connected with the inverting input end INN, the grid electrode of the first two-to-one PMOS tube is connected with the forward input end INP, the source electrode of the first one-to-one PMOS tube is connected with the source electrode of the first two-to-one PMOS tube and is commonly connected to the output end of the first two-tail current source, and the input end of the first two-tail current source is connected with a power supply; the drain electrode of the first NMOS tube is connected to the P-type load tube, and the drain electrode of the first NMOS tube is connected to the P-type load tube;
the drain electrodes of the first PMOS tubes are respectively connected with the source electrodes of the first third NMOS tubes and the drain electrodes of the first fifth NMOS tubes, and the drain electrodes of the first two PMOS tubes are respectively connected with the source electrodes of the first fourth NMOS tubes and the drain electrodes of the first sixth NMOS tubes.
The P-type load tube comprises a first third PMOS tube, a first fourth PMOS tube, a first fifth PMOS tube and a first sixth PMOS tube, wherein the grid electrode of the first third PMOS tube is connected with the grid electrode of the first fourth PMOS tube and is connected to the drain electrode of the first fifth PMOS tube; the grid electrode of the first fifth PMOS tube is connected with the grid electrode of the first sixth PMOS tube; the source electrode of the first third PMOS tube and the source electrode of the first fourth PMOS tube are connected to a power supply; the drain electrode of the first third PMOS tube is connected with the source electrode of the first fifth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the first fourth PMOS tube is connected with the source electrode of the first sixth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the first sixth PMOS tube is connected to the Class-AB output control circuit; the drain electrode of the first fifth PMOS tube is connected with the drain electrode of the first third NMOS tube.
The Class-AB output stage comprises a first seventh PMOS tube and a first seventh NMOS tube, wherein the source electrode of the first seventh PMOS tube is connected with a power supply, the grid electrode of the first seventh PMOS tube is connected to a Class-AB output control circuit, the source electrode of the first seventh NMOS tube is grounded, and the grid electrode of the first seventh NMOS tube is connected to the Class-AB output control circuit; the drain electrode of the first seventh PMOS tube is connected with the drain electrode of the first seventh NMOS tube and is used as an output end OUT of the operational amplifier.
After the scheme is adopted, the common-gate current mirror is realized in a self-adaptive control mode, and bias current which is not influenced by input common-mode voltage and input to a tail current source is provided for a later-stage circuit, so that the bias state of an output stage and the overall performance of the operational amplifier are stable.
Drawings
FIG. 1 is a circuit diagram of a prior art rail-to-rail input operational amplifier including a P-type load tube biasing circuit;
FIG. 2 is a block diagram of a rail-to-rail input operational amplifier of the present invention providing a bias voltage for a P-type load tube;
FIG. 3 is a schematic diagram of a bias circuit for providing bias voltages to a P-type load tube in accordance with the present invention;
fig. 4 is a diagram of a bias circuit for providing bias voltage to an N-type load tube in accordance with the present invention.
Detailed Description
The technical scheme and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 2, which is a schematic diagram of the present invention applied to a rail-to-rail input operational amplifier, a bias circuit is connected to a P-type load tube to provide a bias voltage for the P-type load tube.
As shown in fig. 3, the present invention provides a bias circuit for a rail-to-rail input operational amplifier, which is connected to a P-type load tube to provide a bias voltage for the P-type load tube. The bias circuit comprises an amplifier A1, a PMOS tube PM8, a PMOS tube PM9, a resistor R1 and a current source I13, wherein the output end of the amplifier A1 is respectively connected with the grid of PM3 and the grid of PM4, and the connection point is defined as a point C; the positive input of the amplifier A1 is defined as point a, which is also connected to the drain of PM4 and the source of PM 6; the negative input of the amplifier A1 is defined as point B, which is connected to the drain of PM8 and the source of PM9, respectively; the source electrode of PM8 is connected with a power supply, the grid electrode of PM8, the drain electrode of PM9 and one end of R1 are connected, the grid electrode of PM9 is respectively connected with the grid electrode of PM5 and the grid electrode of PM6, the grid electrode of PM9 is also respectively connected with the other end of R1 and the input end of I13, and the output end of I13 is grounded. The rest circuit structure in the operational amplifier is the same as the existing structure, and will not be described again.
Based on the analysis of the circuit of fig. 1, there is still a current relation i1=i2+i3 in the circuit of fig. 3, but unlike the conventional architecture, PM4 no longer forms a current mirror with PM8, the magnitude of current I1 is determined by I2 and I3, the gate potential of PM3, PM4, i.e. point C, is feedback-regulated by amplifier A1, so that the voltages at points a and B are equal, i.e. the source voltages of PM6 and PM9 are equal, where PM6 and PM9 form a current mirror, and the current I3 flowing through the PM6 and Class AB output control circuit is proportional to the current I0, determined by the dimensions of PM9 and PM 6. When the dimensions of PM9 and PM6 are fixed, the magnitude of the current I3 remains unchanged. The static power consumption of the output stage is not changed, the impedance is stable, and the stability of the operational amplifier is not affected when the input common-mode voltage is changed.
As shown in fig. 4, the present invention further provides a bias circuit for providing bias voltage for an N-type load tube, which includes an amplifier A2, an NMOS tube NM18, an NMOS tube NM19, a resistor R2 and a current source I113, wherein an output end of the amplifier A2 is connected to a gate of NM15 and a gate of NM16 respectively; the negative input end of the amplifier A2 is respectively connected with the source electrode of the NM14 and the drain electrode of the NM 16; the positive input end of the amplifier A2 is connected with the source electrode of the NM18 and the drain electrode of the NM 19; the input end of the current source I113 is connected with a power supply, the output end of the current source I113 is respectively connected with one end of R2 and the grid electrode of NM18, and the grid electrode of NM18 is also respectively connected with the grid electrode of NM13 and the grid electrode of NM 14; the other end of R2 is respectively connected with the drain electrode of NM18 and the grid electrode of NM 19; the source of NM19 is grounded.
In operation, there is a current relationship i1=i2+i3, but unlike the conventional architecture, NM16 no longer forms a current mirror with NM19, the magnitude of the current I1 is determined by I2 and I3, the gate potentials of NM13 and NM14 are controlled by feedback regulation of amplifier A2, so that the source voltages of NM14 and PM18 are equal, NM14 and NM18 form a current mirror, and the current I3 flowing through NM14 and Class AB output control circuits is proportional to the current I0, which is determined by the dimensions of NM14 and NM 18. When the dimensions of NM14 and NM18 are fixed, the magnitude of current I3 remains unchanged. The static power consumption of the output stage is not changed, the impedance is stable, and the stability of the amplifier is not affected when the input common-mode voltage is changed.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.
Claims (6)
1. The bias circuit for the rail-to-rail input operational amplifier comprises a rail-to-rail input stage, a Class-AB output control circuit, a P-type load tube, an N-type load tube and a Class-AB output stage, wherein the P-type load tube comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube; the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected to a power supply; the drain electrode of the third PMOS tube is connected with the source electrode of the fifth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the sixth PMOS tube is connected to the Class-AB output control circuit; the method is characterized in that:
the bias circuit comprises a first amplifier, an eighth PMOS tube, a ninth PMOS tube, a first resistor and a third current source, wherein the output end of the first amplifier is respectively connected with the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube, the positive input end of the first amplifier is connected with the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube, and the negative input end of the first amplifier is connected with the drain electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the source electrode of the eighth PMOS tube is connected with a power supply, the grid electrode of the eighth PMOS tube, the drain electrode of the ninth PMOS tube and one end of the first resistor are connected, the grid electrode of the ninth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the grid electrode of the ninth PMOS tube is also respectively connected with the other end of the first resistor and the input end of the third current source; the output end of the third current source is grounded;
the rail-to-rail input stage comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first tail current source and a second tail current source, wherein the grid electrode of the first NMOS tube is connected with an inverted input end INN, the grid electrode of the second NMOS tube is connected with a forward input end INP, the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and is commonly connected with the input end of the first tail current source, and the output end of the first tail current source is grounded; the grid electrode of the first PMOS tube is connected with the inverting input end INN, the grid electrode of the second PMOS tube is connected with the forward input end INP, the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is commonly connected to the output end of the second tail current source, and the input end of the second tail current source is connected with a power supply; the drain electrode of the first PMOS tube is connected to the N-type load tube, and the drain electrode of the second PMOS tube is connected to the N-type load tube;
the drain electrode of the first NMOS tube is respectively connected with the drain electrode of the third PMOS tube and the source electrode of the fifth PMOS tube, and the drain electrode of the second NMOS tube is respectively connected with the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube;
the source current of the fourth PMOS tube is equal to the sum of the drain current of the second NMOS tube and the drain current of the sixth PMOS tube, the sixth PMOS tube and the ninth PMOS tube form a current mirror, the drain current of the sixth PMOS tube is in direct proportion to the current flowing through the ninth PMOS tube, and when the sizes of the sixth PMOS tube and the ninth PMOS tube are fixed, the drain current of the sixth PMOS tube is kept unchanged; the static power consumption of the output stage is not changed, the impedance is stable, and the stability of the operational amplifier is not affected when the input common-mode voltage is changed.
2. The bias circuit for a rail-to-rail input operational amplifier of claim 1, wherein: the N-type load tube comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and is connected to the drain electrode of the third NMOS tube; the drain electrode of the third NMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the fourth NMOS tube is connected to the Class-AB output control circuit; the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are grounded.
3. The bias circuit for a rail-to-rail input operational amplifier of claim 1, wherein: the Class-AB output stage comprises a seventh PMOS tube and a seventh NMOS tube, wherein the source electrode of the seventh PMOS tube is connected with a power supply, the grid electrode of the seventh PMOS tube is connected to a Class-AB output control circuit, the source electrode of the seventh NMOS tube is grounded, and the grid electrode of the seventh NMOS tube is connected to the Class-AB output control circuit; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube and is used as the output end OUT of the operational amplifier.
4. The bias circuit for the rail-to-rail input operational amplifier comprises a rail-to-rail input stage, a Class-AB output control circuit, a P-type load tube, an N-type load tube and a Class-AB output stage, wherein the N-type load tube comprises a first three NMOS tube, a first four NMOS tube, a first five NMOS tube and a first six NMOS tube, the grid electrode of the first three NMOS tube is connected with the grid electrode of the first four NMOS tube, and the grid electrode of the first five NMOS tube is connected with the grid electrode of the first six NMOS tube; the drain electrode of the first NMOS tube is connected to the P-type load tube, and the drain electrode of the first NMOS tube is connected to the Class-AB output control circuit; the source electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the first fourth NMOS tube is connected with the drain electrode of the first sixth NMOS tube and is commonly connected to the rail-to-rail input stage; the source electrode of the first fifth NMOS tube and the source electrode of the first sixth NMOS tube are grounded; the method is characterized in that:
the bias circuit comprises a second amplifier, a first eighth NMOS tube, a first ninth NMOS tube, a second resistor and a first third current source, wherein the output end of the second amplifier is respectively connected with the grid electrode of the first fifth NMOS tube and the grid electrode of the first sixth NMOS tube, the negative input end of the second amplifier is respectively connected with the source electrode of the first fourth NMOS tube and the drain electrode of the first sixth NMOS tube, and the positive input end of the second amplifier is respectively connected with the source electrode of the first eighth NMOS tube and the drain electrode of the first ninth NMOS tube; the input end of the first third current source is connected with a power supply, the output end of the first third current source is respectively connected with one end of the second resistor and the grid electrode of the first eighth NMOS tube, and the grid electrode of the first eighth NMOS tube is also respectively connected with the grid electrode of the first third NMOS tube and the grid electrode of the first fourth NMOS tube; the other end of the second resistor is respectively connected with the drain electrode of the first eighth NMOS tube and the grid electrode of the first ninth NMOS tube; the source electrode of the first nine NMOS tube is grounded;
the rail-to-rail input stage comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first diode NMOS tube, a first PMOS tube, a first diode PMOS tube, a first tail current source and a first diode tail current source, wherein a grid electrode of the first NMOS tube is connected with an inverted input end INN, a grid electrode of the first diode NMOS tube is connected with a forward input end INP, a source electrode of the first NMOS tube is connected with a source electrode of the first diode NMOS tube and is commonly connected with an input end of the first diode tail current source, and an output end of the first diode tail current source is grounded; the grid electrode of the first one-to-one PMOS tube is connected with the inverting input end INN, the grid electrode of the first two-to-one PMOS tube is connected with the forward input end INP, the source electrode of the first one-to-one PMOS tube is connected with the source electrode of the first two-to-one PMOS tube and is commonly connected to the output end of the first two-tail current source, and the input end of the first two-tail current source is connected with a power supply; the drain electrode of the first NMOS tube is connected to the P-type load tube, and the drain electrode of the first NMOS tube is connected to the P-type load tube;
the drain electrodes of the first two-to-one PMOS (P-channel metal oxide semiconductor) transistors are respectively connected with the source electrodes of the first third NMOS transistor and the drain electrodes of the first fifth NMOS transistor, and the drain electrodes of the first two-to-one PMOS transistor are respectively connected with the source electrodes of the first fourth NMOS transistor and the drain electrodes of the first sixth NMOS transistor;
the source current of the first sixth NMOS tube is equal to the sum of the drain current of the first diode PMOS tube and the drain current of the first fourth NMOS tube, the first fourth NMOS tube and the first eighth NMOS tube form a current mirror, the drain current of the first fourth NMOS tube is in direct proportion to the current flowing through the first eighth NMOS tube, and when the sizes of the first fourth NMOS tube and the first eighth NMOS tube are fixed, the drain current of the first fourth NMOS tube is kept unchanged; the static power consumption of the output stage is not changed, the impedance is stable, and the stability of the operational amplifier is not affected when the input common-mode voltage is changed.
5. The bias circuit for a rail-to-rail input operational amplifier of claim 4, wherein: the P-type load tube comprises a first third PMOS tube, a first fourth PMOS tube, a first fifth PMOS tube and a first sixth PMOS tube, wherein the grid electrode of the first third PMOS tube is connected with the grid electrode of the first fourth PMOS tube and is connected to the drain electrode of the first fifth PMOS tube; the grid electrode of the first fifth PMOS tube is connected with the grid electrode of the first sixth PMOS tube; the source electrode of the first third PMOS tube and the source electrode of the first fourth PMOS tube are connected to a power supply; the drain electrode of the first third PMOS tube is connected with the source electrode of the first fifth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the first fourth PMOS tube is connected with the source electrode of the first sixth PMOS tube and is commonly connected to the rail-to-rail input stage; the drain electrode of the first sixth PMOS tube is connected to the Class-AB output control circuit; the drain electrode of the first fifth PMOS tube is connected with the drain electrode of the first third NMOS tube.
6. The bias circuit for a rail-to-rail input operational amplifier of claim 4, wherein: the Class-AB output stage comprises a first seventh PMOS tube and a first seventh NMOS tube, wherein the source electrode of the first seventh PMOS tube is connected with a power supply, the grid electrode of the first seventh PMOS tube is connected to a Class-AB output control circuit, the source electrode of the first seventh NMOS tube is grounded, and the grid electrode of the first seventh NMOS tube is connected to the Class-AB output control circuit; the drain electrode of the first seventh PMOS tube is connected with the drain electrode of the first seventh NMOS tube and is used as an output end OUT of the operational amplifier.
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| WO2023097965A1 (en) * | 2021-12-03 | 2023-06-08 | 深圳飞骧科技股份有限公司 | Low dropout linear regulator having fast transient response, chip, and electronic device |
| CN116526833A (en) * | 2023-06-29 | 2023-08-01 | 江苏润石科技有限公司 | Charge pump with stable output voltage and rail-to-rail input operational amplifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230032759A1 (en) * | 2021-07-27 | 2023-02-02 | Microchip Technology Incorporated | Op-Amp with Random Offset Trim across Input Range with Rail-to-Rail Input |
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2023
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100842405B1 (en) * | 2007-05-25 | 2008-07-01 | 삼성전자주식회사 | High voltage cmos rail-to-rail input/output operational amplifier |
| CN202503479U (en) * | 2012-03-16 | 2012-10-24 | 聚辰半导体(上海)有限公司 | A class AB operational amplifier with high gain and a high power supply rejection ration |
| CN110275051A (en) * | 2018-03-14 | 2019-09-24 | 意法设计与应用股份有限公司 | Current sensor with expanded voltage range |
| CN114167930A (en) * | 2021-12-03 | 2022-03-11 | 昆山启达微电子有限公司 | Rail-to-rail AB type operational amplifier with wide power supply voltage range |
| WO2023097965A1 (en) * | 2021-12-03 | 2023-06-08 | 深圳飞骧科技股份有限公司 | Low dropout linear regulator having fast transient response, chip, and electronic device |
| CN116526833A (en) * | 2023-06-29 | 2023-08-01 | 江苏润石科技有限公司 | Charge pump with stable output voltage and rail-to-rail input operational amplifier |
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| CN116760371A (en) | 2023-09-15 |
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