CN111654244A

CN111654244A - High-linearity G omega-level equivalent resistance circuit with PVT robustness

Info

Publication number: CN111654244A
Application number: CN202010542835.5A
Authority: CN
Inventors: 张雷; 陈华平
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2020-06-15
Filing date: 2020-06-15
Publication date: 2020-09-11

Abstract

The invention discloses a high-linearity G omega-level equivalent resistance circuit with PVT robustness, and belongs to the field of analog integrated circuit design. The equivalent circuit structure comprises four stages of current dividers and an input resistor, wherein each current divider comprises an operational amplifier and two groups of current dividing transistors. The operational amplifier is based on a two-stage Miller amplifier structure and comprises a two-stage differential transconductance common-source amplifier and an inter-stage compensation circuit, wherein the inter-stage compensation circuit consists of a resistor and a capacitor and is used for improving the stability of the operational amplifier; the shunt transistor is composed of two groups of same PMOS tubes, each group comprises two PMOS tubes, and the size of one PMOS tube is several times that of the other PMOS tube. The circuit of the invention realizes hundreds of G omega equivalent resistance, simultaneously maintains higher level of linearity, and has simple structure and easy realization.

Description

High-linearity G omega-level equivalent resistance circuit with PVT robustness

Technical Field

The invention belongs to the field of analog integrated circuit design, and particularly relates to a high-linearity G omega-level equivalent resistance circuit with PVT robustness.

Background

In recent years, with the rise of auto-driven automobiles and smart homes and the continuous development of the aerospace and military fields, the sensors and the corresponding analog front-end circuits thereof have higher requirements on stability. The analog front-end circuit is often required to normally work within a Temperature range of-40 to 125 ℃, which provides a great challenge to the Process-Voltage-Temperature (PVT) stability of the chip. Because the bandwidth of the output signal of the sensor is often low, and weak direct current bias generated due to instability of the external environment is prevented from influencing the direct current working point of the whole analog front-end circuit, the analog front-end circuit of the sensor often needs a large resistor of a G omega level to realize a low-pass filter of extremely low frequency cut-off frequency, or is applied to a direct current servo circuit, so as to solve the problem that the output end of an amplifier is saturated due to the weak direct current bias. However, for the integrated circuit process, the well resistor, the p +/n + resistor, the Poly resistor, the metal resistor, etc. need to realize the G Ω resistance, and therefore, a very large chip area is occupied. Additional circuit technology is therefore required to implement the G Ω stage of resistance.

One approach that has prevailed in the past for achieving large resistances is to use a pseudo-resistance approach: the drains of the two grid-drain connected PMOS transistors are connected together, and the two sources are used as two poles of a resistor, so that the current flowing through the two PMOS transistors can reach the nA magnitude when the bias works in a sub-threshold region, and the equivalent resistance value of the PMOS transistors meets the requirement. However, the resistance realized in this way has two important disadvantages: one is poor linearity. The equivalent resistance value of the pseudo-resistor structure is related to bias voltages of two sources, and even if the amplitude of an input signal is tens of mV, the equivalent resistance value of the circuit can be changed violently along with the input voltage; second is the lack of PVT stability. According to the current formula of the sub-threshold region of the transistor, the current flowing through the transistor can have significant variation with temperature, and the non-ideality of the process manufacturing can cause further deterioration of the equivalent resistance value. The disadvantages of the pseudo-resistive structure limit its application scenarios. Another way is to use an operational amplifier plus one-way shunt architecture as shown in fig. 1. For the first-stage current divider structure, an input signal Vin is converted into a current V through a resistor R_inand/R, and flows through PMOS transistors connected across the inverting input and output of the operational amplifier. Since both transistors operate under the same bias condition and the size of the PMOS transistor M1 is N times the size of the PMOS transistor M2, the current flowing through the transistor M2, i.e., the output current of the shunt, is reduced by N times. The equivalent resistance value realized by the first-stage shunt is N.R. The resistance value which can be realized after the four-stage shunt is connected in series is N⁴R. Regulating ginsengThe equivalent resistance of G omega level can be realized. Another advantage of this shunt configuration is good linearity in the power supply rail from VSS to VDD. Because the bias states of the two PMOS transistors are always the same during the transition of the input signal from VSS to VDD, the ratio of the current flowing through the whole transistor is always kept at N times: when Vin<At 0, the gate-source voltages Vgs of the PMOS transistors M1 and M2<0, both of which operate in the subthreshold or saturation region. As long as the bias voltage of each port of the two PMOS transistors is the same, the proportion of the current flowing through the two PMOS transistors is the same as the size of the two PMOS transistors; when Vin>At 0, the gate-source voltages Vgs of the MOS transistors M1 and M2>0, when the parasitic drain-well PN junction is activated, both transistors operate in a diode-like fashion, with the sources of M1 and M2 serving as the anodes and the gates as the cathodes of the diodes. The magnitude of the current through the diode is equal to the junction current per unit area multiplied by the junction area, which is proportional to the size of the PMOS transistor, so that the proportion of the current through the two PMOS transistors is the same as their size, also when the two PMOS transistors are biased in the same condition. However, this circuit has the disadvantage that the shunt structure is still strongly affected by temperature: when the temperature is reduced to a certain degree, the structure can not realize the rail-to-rail input range, Vin>The circuit nonlinearity is severe at 0. The reason for this is that at Vin>At 0, the two PMOS transistors operate as diodes. However, since the junction current per unit area of the PMOS transistor is reduced due to the temperature reduction, the output voltage of the operational amplifier needs to be reduced in order to keep the two PMOS transistors under the same bias. However, the voltage variation range of the output end of the operational amplifier is limited, so that the two PMOS transistors can not work under the same bias condition, and the current values flowing through the two PMOS transistors can not keep N times of the relationship.

Disclosure of Invention

In view of the above, the present invention is to provide a high linearity G Ω equivalent resistor circuit with PVT robustness to overcome the shortcomings of the prior art. On the basis of the original current shunt, the invention adds another shunt tube pair as compensation: as shown in dashed lines in fig. 2, are again two diode-connected PMOS transistors, the sources of which are connected together and which operate the output of the amplifier. The two shunts are connected in parallel. When Vin <0, the two PMOS transistors M1 and M2 connected by the solid line work in a subthreshold region or a saturation region, and the bias voltage is the same, and at the same time, the two PMOS transistors M3 and M4 connected by the dashed line work in a diode-like manner because the parasitic drain-well junction is activated, but the current flowing through the former is much larger than the current flowing through the latter, so that N-fold attenuation of the current can be normally realized at this time; similarly, when Vin >0, the two PMOS transistors M3 connected by the dotted line operate in the subthreshold region or saturation region, while the PMOS transistors M1 and M2 connected by the solid line operate in the form of diodes, and the current attenuation by a factor of N is also realized. By adding one set of current shunt tubes, the two sets of current shunt tubes work in a sub-threshold region or a saturation region when Vin <0 and Vin >0 respectively, and therefore the influence of a transistor working in a diode mode is weakened. The circuit structure can work normally under different PVT conditions, and the equivalent resistance value of the circuit structure can keep high linearity under different PVT conditions.

In order to achieve the purpose, the invention adopts the following technical scheme:

a high linearity G omega level equivalent resistance circuit with PVT robustness is characterized by comprising an input resistor and a four-level current divider;

each stage of current divider respectively comprises an operational amplifier and two groups of current dividing transistors, wherein the operational amplifier comprises a two-stage differential transconductance common-source amplifier and an interstage compensating circuit; the first stage of differential transconductance common-source amplifier is a differential input single-ended output common-source amplifier taking an active current mirror as a load and consists of a tail current transistor, a first stage of amplifying transistor and a first stage of load transistor; the second-stage differential transconductance common-source amplifier is a single-end common-source amplifier and consists of a second-stage amplifying transistor and a second-stage load transistor; the interstage compensation circuit is formed by connecting a resistor and a capacitor in series; each group of current shunt transistors consists of two PMOS transistors with one large and one small, the grid width of the large PMOS transistor is several times of that of the small PMOS transistor, and the grid lengths are consistent;

the connection relationship of the above devices is as follows: the input end of the first-stage current divider is connected with one end of the input resistor in series, the other end of the input resistor is used as the input end of the equivalent resistor circuit, and the output end of the fourth-stage current divider is used as the output end of the equivalent resistor circuit; the current divider comprises two groups of current dividing transistors, wherein the source electrode of each PMOS transistor in each group is connected with the substrate, and the grid electrode and the drain electrode are connected to form a diode connection mode; the source electrodes of two PMOS transistors in a group of current shunt transistors are connected and then connected to the output end of a corresponding operational amplifier, the drain electrodes of large-size PMOS transistors in the group of current shunt transistors are connected to the inverting input end of the corresponding operational amplifier, the positive phase input end of the operational amplifier is connected with bias voltage, and the drain electrodes of small-size PMOS transistors serve as the output end of the corresponding current shunt; the drain electrodes of two PMOS transistors in the other group of current shunt transistors are connected and then connected to the output end of the corresponding operational amplifier, the source electrode of the large-size PMOS transistor in the group of current shunt transistors is connected to the inverting input end of the corresponding operational amplifier, and the source electrode of the small-size PMOS transistor is used as the output end of the corresponding current shunt; the source electrodes and the drain electrodes of the two large-size PMOS transistors are connected and then serve as input ends of the corresponding current shunts, and the drain electrodes and the source electrodes of the two small-size PMOS transistors are connected and then serve as output ends of the corresponding current shunts.

The invention has the technical characteristics and beneficial effects that:

1. the linearity of the equivalent resistance value of the circuit under various PVT working conditions is improved. Under the severe working conditions that the power supply voltage value has +/-10% fluctuation, the process is irrational and the temperature is changed from minus 40 ℃ to 125 ℃, the circuit can normally work, and the linearity can be maintained at a high level while hundreds of G omega equivalent resistance is realized;

2. the additional power consumption, chip area and chip complexity added is small compared to the old structure before modification. For the one-way type current divider structure before modification, four operational amplifiers occupy the largest circuit area. And the area of the shunt pipe is only doubled by adopting a complementary shunt structure. The added current tube has little influence on the power consumption, the area and the complexity of the whole circuit.

Drawings

FIG. 1 is a schematic diagram of an equivalent resistance circuit of the prior art;

FIG. 2 is a schematic diagram of a G Ω -level high linearity equivalent resistance circuit with PVT stability according to the present invention;

FIG. 3 is a comparison of output currents of different structures at 1.8V supply voltage, TT process angle and-40 deg.C;

fig. 4 (a) and (b) show the linearity comparison of equivalent resistance values of the circuit before and after improvement under different process angles.

Detailed Description

In order to make the objects, technical solutions and features of the present invention clearer and more clear, the following detailed description and description of specific embodiments are provided with reference to the accompanying drawings.

The high-linearity G omega-level equivalent resistance circuit with PVT robustness, provided by the invention, has a circuit structure as shown in figure 2, and consists of a four-level current divider and an input resistor which are connected in series; each level of current shunt has the same structure and consists of an operational amplifier and a plurality of current shunt pipes; the operational amplifier is based on a two-stage Miller amplifier structure and consists of a two-stage differential transconductance common-source amplifier and an interstage compensating circuit; the first-stage differential transconductance common-source amplifier is a differential input single-ended output common-source amplifier taking an active current mirror as a load and consists of a tail current tube, an amplifying tube and a load tube; the second-stage differential transconductance common-source amplifier is a single-end common-source amplifier and consists of an amplifying tube and a load tube. The interstage compensation circuit consists of a resistor and a capacitor and is used for improving the phase margin of the two-stage differential transconductance common-source amplifier so as to improve the stability of the whole circuit; the current shunt pipe comprises two groups of PMOS transistor pairs, each group of PMOS transistor pairs respectively comprises a big PMOS transistor and a small PMOS transistor, the source electrode of each PMOS transistor in the group is connected with the substrate, the grid electrode and the drain electrode are connected to form a diode connection mode, one group is connected with the source electrode, and the other group is connected with the drain electrode; the grid width of the large-size transistor is N times of the grid width of the small-size transistor, the two grids are consistent in length, the virtual short and virtual disconnection characteristics of the operational amplifier are hesitated, and the bias voltages of the large transistor and the small transistor are the same, so that the output current is 1/N times of the input current, and the attenuation of the specific times of the current is realized. The specific connection mode of the circuit of the embodiment of the invention is as follows:

the operational amplifiers a1 to a4 have the same structure, and now, an operational amplifier a1 is taken as an example for explanation, the operational amplifier a1 is composed of transistors M17, M18, M19, M20, M21, M22 and M23, a resistor Rcb and a capacitor Ccb, wherein the transistors M17, M18, M21 and M23 are PMOS transistors, and the transistors M19, M20 and M22 are NMOS transistors. The grid electrode of the PMOS transistor M21 is connected with a bias voltage Vbias provided by an external circuit, the source electrode of the PMOS transistor M21 is connected with a power supply VDD, and the drain electrode of the PMOS transistor M21 is connected with the common end of the source electrodes of the PMOS transistors M17 and M18; the grid of the PMOS transistor M17 is used as the negative pole V-of the inverting input end of the operational amplifier A1 to access the input signal, the source of the PMOS transistor M17 is connected with the drain of the M21, and the drain of the PMOS transistor M17 is connected with the drain of the NMOS transistor M19; the gate of the PMOS transistor M18 is used as the positive electrode V + of the positive phase input end of the operational amplifier a1 to access the input signal, the source of the PMOS transistor M18 is connected to the drain of the PMOS transistor M21, and the drain of the PMOS transistor M18 is connected to the drain of the NMOS transistor M20; the grid electrode of the NMOS transistor M19 is connected with the source electrode, the drain electrode of the PMOS transistor M17 is connected, and the source electrode of the NMOS transistor M19 is grounded VSS; the grid electrode of the NMOS transistor M20 is connected with the grid electrode of the NMOS transistor M19, the drain electrode of the NMOS transistor M20 is connected with the drain electrode of the PMOS transistor M18, and the source electrode of the NMOS transistor M20 is grounded with VSS; the gate of the NMOS transistor M22 is connected with the drain of the NMOS transistor M20, the drain of the NMOS transistor M22 is connected with the drain of the PMOS transistor M23 and serves as the output end OUT of the amplifier circuit, and the source of the NMOS transistor M22 is grounded VSS; the grid electrode of the PMOS transistor M23 is connected with a bias voltage Vbias provided by an external circuit, the drain electrode of the PMOS transistor M23 is connected with the drain electrode of the NMOS transistor M22 and serves as an output end OUT of the method circuit, and the source electrode of the PMOS transistor M23 is connected with a power supply VDD; one end of the capacitor Ccb is connected in series with one end of the resistor Rcb, the other end of the capacitor Ccb is connected with the drain of the NMOS transistor M22, and the other end of the resistor Rcb is connected with the common end of the gate of the NMOS transistor M22 and the drain of the NMOS transistor M20.

Each stage of current divider respectively consists of a corresponding operational amplifier (A1, A2, A3 or A4) and four transistors (M1-M4, M5-M8, M9-M12 or M1-M16), wherein the four transistors are all PMOS transistors. Taking the first stage current divider as an example, the first stage current divider is composed of an operational amplifier a1 and four PMOS transistors M1 to M4. The non-inverting input terminal of the operational amplifier a1 is connected to the bias voltage Vref. The grid electrode and the drain electrode of the PMOS transistor M1 are connected, and are connected with the inverting input end of the operational amplifier A1, and the source electrode of the PMOS transistor M1 is connected with the output end OUT of the operational amplifier; the grid electrode and the drain electrode of the PMOS transistor M2 are connected, and the grid electrode and the drain electrode of the PMOS transistor M4 are connected, and the source electrode of the PMOS transistor M2 is connected with the output end OUT of the operational amplifier A1; the grid electrode and the drain electrode of the PMOS transistor M3 are connected, and are connected with the output end OUT of the operational amplifier A1, and the source electrode of the PMOS transistor M3 is connected with the inverting input end of the operational amplifier A1; the gate and the drain of the PMOS transistor M4 are connected to the output terminal OUT of the operational amplifier a1, the source of the PMOS transistor M4 is connected to the drain of the PMOS transistor M2, and the output terminal of the PMOS transistor M4 serving as a primary current divider is connected to the inverting input terminal of the next-stage current divider.

The complete circuit structure consists of four stages of current dividers and an input resistor R, wherein the output of the current divider of the previous stage is used as the input of the next stage, and the output of the last stage is used as the output of the whole circuit. The input of the first stage is connected in series with one end of a resistor R, and the other end of the resistor R is used as the input of the whole circuit.

The embodiment of the high-linearity G omega-level equivalent resistance circuit with PVT robustness of the invention is explained as follows:

in this embodiment, a 65nm CMOS process (which is a conventional fabrication process in the art) is used to fabricate a G Ω -level high linearity equivalent resistance circuit with PVT stability, and simulation results thereof are shown in fig. 3 and 4.

Fig. 3 shows the output current of the complementary structure and the unidirectional structure varying with the input voltage under the environment of 1.8V power supply voltage, TT process angle and-40 ℃, and it can be seen that under the working environment, the unidirectional structure can only work normally under the condition that Vin is less than 0, and the complementary structure can work normally for the rail-to-rail input signal. Furthermore, it can be seen that the slope of the complementary structure curve is about 11.25pA/V, i.e., the equivalent resistance is about 88.9 G.OMEGA.. Fig. 4 shows the linearity of the equivalent resistance of the circuit under various extreme environments. It can be seen that the equivalent resistance value of the circuit structure varies linearly with the input voltage under each process corner condition.

In conclusion, the invention can realize the G omega equivalent resistance with high linearity while ensuring the normal work of the circuit under various severe environments.

The above examples demonstrate the correctness and effectiveness of the present invention. The above description is only the G Ω level high linearity equivalent resistance circuit under the specific CMOS process and the specific resistance and the specific application environment, and is not intended to limit the protection scope of the present invention.

Claims

1. A high linearity G omega level equivalent resistance circuit with PVT robustness is characterized by comprising an input resistor and a four-level current divider;

2. The high linearity G omega level equivalent resistance circuit according to claim 1, wherein in each operational amplifier, the two-stage differential transconductance common-source amplifier comprises seven transistors, a resistor and a capacitor, the first to fourth transistors are PMOS transistors, and the fifth to seventh transistors are NMOS transistors; the gates of the first transistor M17 and the second transistor M18 are respectively used as the inverting input terminal and the non-inverting input terminal of the corresponding operational amplifier, the sources of the first transistor M17 and the second transistor M18 are connected and then connected to the drain of the fifth transistor M21, and the drains of the first transistor M17 and the second transistor M18 are respectively connected to the drains of the third transistor M19 and the fourth transistor M20; the gates of the third transistor M19 and the fourth transistor M20 are connected and then connected to the drain of the third transistor M19, the sources of the third transistor M19, the fourth transistor M20 and the sixth transistor M22 are all connected, the drain of the fourth transistor M20 is connected to the gate of the sixth transistor M22, and the drain of the sixth transistor M22 and the drain of the seventh transistor M23 are connected as the output end of the corresponding amplifier circuit; after the resistor of the interstage compensation circuit is connected with one end of the capacitor in series, the other ends of the resistor and the capacitor are respectively connected between the source electrode of the fourth transistor M20 and the source electrode of the sixth transistor M22 and the output end of the amplifier circuit, the grid electrodes of the sixth transistor M22 and the seventh transistor M23 are connected, and the source electrodes of the sixth transistor M22 and the seventh transistor M23 are connected. The substrates of all PMOS tubes in the operational amplifier are connected with a power supply voltage VDD, and the substrates of all NMOS tubes are connected with a ground potential VSS.