CN114356016B - Low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit - Google Patents
Low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit Download PDFInfo
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Abstract
The invention discloses a low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit, which comprises: the input end of the constant voltage source is connected with the first signal input end; the first operational amplifier is connected with the first signal input end; the mirror circuit is connected with the second signal input end, the power end and the first operational amplifier; the compensation circuit is connected with the mirror image circuit and the power supply end; the super source electrode follower circuit is connected with the compensation circuit and the power supply end; the operational amplifier tail current circuit is connected with the super source follower circuit, the power end and the signal output end. According to the invention, the super source follower is inserted to isolate large parasitic capacitance from higher output impedance, so that the loop bandwidth of the LDO is expanded; the slew rate of the operational amplifier is increased, and the transient performance of the LDO is improved.
Description
Technical Field
The invention relates to the technical field of chip circuits, in particular to a low-power consumption CMOS ultra-wide temperature range transient enhancement type LDO circuit.
Background
The stability influencing factor of the traditional LDO (Low Dropout Regulator, linear voltage stabilizer) is that a main pole exists at the output end of the LDO, the main pole is influenced by an output capacitor and a load current, and increasing the load current directly leads to the frequency of the main pole to be high. Meanwhile, load current also has influence on the direct current gain of the system, the influence on the adjusting tube is mainly larger, the intrinsic gain of the adjusting tube is adjusted, if the load current is increased, the loop gain is reduced at a lower speed than the main pole point acceleration ratio, and the loop bandwidth of the system is increased. The effect of the high frequency parasitic pole of the system will not be negligible at this point, which will reduce the phase margin of the system and make the system prone to instability. The influence of parasitic poles is also very large, if the driving current of the parasitic capacitance of the grid electrode of the adjusting tube is increased, the transient characteristic of the LDO can be obviously improved, but the quiescent current of the LDO is increased, and the efficiency is reduced. In the low-power consumption LDO, the charging and discharging current of the grid electrode of the regulating tube is the tail current of the nA stage of the first-stage operational amplifier, so that the low-power consumption LDO is limited by the operational amplifier SR, and the transient regulating capability of the LDO for the rapid change of the output load is limited.
In order to solve the problem of compromise between LDO power consumption and area, the LDO of this patent design adopts active resistance to replace passive resistance. In theory, both the NMOS and PMOS devices in diode connection form can be used as active resistors, but the substrates of the NMOS devices in N-well CMOS process are required to be grounded, so that a lining bias effect is caused, and the threshold voltages of the NMOS devices connected by different diodes are error, thereby affecting the accuracy of the ratio. Thus we use the active resistance of PMOS.
Disclosure of Invention
The preferred embodiments of the present invention will be described in detail below with reference to the attached drawings, which further illustrate the present invention.
First, a low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit according to an embodiment of the present invention will be described with reference to fig. 1, and is used for controlling internal circuits of a CMOS chip, and has a wide application scenario.
As shown in fig. 1, the low-power CMOS ultra-wide temperature range transient enhancement LDO circuit of the embodiment of the invention has a constant voltage source IO, a first operational amplifier I1, a mirror circuit, a compensation circuit, a super source follower circuit, and an operational amplifier tail current circuit.
Specifically, as shown in fig. 1, in the embodiment, the input end of the constant voltage source IO is connected to the first signal input end PO, the constant voltage source IO is used for providing a stable voltage, the inverting input end of the first operational amplifier I1 is connected to the output end of the constant voltage source IO, the first operational amplifier I1 is connected to the first signal input end PO, the first operational amplifier I1 is used for clamping, the mirror circuit is connected to the second signal input end Iblou (i.e. a constant current source), the power supply end VDD and the first operational amplifier I1, the mirror circuit is used for realizing a high-precision mirror image, maintaining the stability of a reference power supply, the compensating circuit is connected to the mirror circuit and the power supply end VDD, the compensating circuit is used for performing a secondary temperature compensation, the super source follower circuit is connected to the compensating circuit and the power supply end VDD, the super source follower circuit is used for improving the transient performance of the LDO at the cost of micro power consumption, and simultaneously increasing the loop bandwidth of the LDO, the tail current circuit is connected to the super source follower circuit, the power supply end VDD and the signal output end, the tail current circuit is used for increasing the driving capacity of an adjusting transistor gate, the active resistor and the active capacitance is reduced by the effective capacitance, and the effective capacitance is reduced by the effective capacitance to a certain reduction of the effective capacitance, and the effective capacitance is realized, and the stability is improved.
Further, as shown in fig. 1, in an embodiment, the mirror circuit includes: first MOS pipe MO, second MOS pipe M1, third MOS pipe M2, fourth MOS pipe M6, fifth MOS pipe M7, sixth MOS pipe M8, seventh MOS pipe M9, eighth MOS pipe M10, ninth MOS pipe M11 and tenth MOS pipe M12. The grid electrode of the first MOS tube MO, the grid electrode of the second MOS tube M1, the grid electrode of the third MOS tube M2 and the drain electrode of the first MOS tube MO are connected and then connected with the second signal input end Iblou, the source electrode of the first MOS tube MO is grounded, the drain electrode of the second MOS tube M1 is connected with the grid electrode of the fourth MOS tube M6 and the drain electrode of the fourth MOS tube M6, the source electrode of the second MOS tube M1 is grounded, the drain electrode of the third MOS tube M2 is connected with the drain electrode of the fifth MOS tube M7, the source electrode of the third MOS tube M2 is grounded, the source electrode of the fourth MOS tube M6 is connected with the power end VDD, the grid electrode of the fifth MOS tube M7, the grid electrode of the sixth MOS tube M8, the grid electrode of the tenth MOS tube M12 and the compensation circuit are connected, the source electrode of the fifth MOS tube M7 is connected with the power supply end VDD, the drain electrode of the sixth MOS tube M8 is connected with the drain electrode of the eighth MOS tube M10, the grid electrode of the eighth MOS tube M10 and the grid electrode of the ninth MOS tube M11, the source electrode of the sixth MOS tube M8 is connected with the power supply end VDD, the grid electrode of the seventh MOS tube M9 is connected with the output end of the first operational amplifier I1, the drain electrode of the seventh MOS tube M9 is connected with the drain electrode of the ninth MOS tube M11 and the same-direction input end of the first operational amplifier I1, the source electrode of the seventh MOS tube M9 is connected with the drain electrode of the tenth MOS tube M12, the source electrode of the eighth MOS tube M10 is grounded, the source electrode of the ninth MOS tube M11 is grounded, and the source electrode of the tenth MOS tube M12 is connected with the power supply end VDD.
Further, as shown in fig. 1, in the embodiment, the first MOS transistor MO, the second MOS transistor M1, the third MOS transistor M2, the eighth MOS transistor M10, and the ninth MOS transistor M11 are NMOS transistors, and the fourth MOS transistor M6, the fifth MOS transistor M7, the sixth MOS transistor M8, the seventh MOS transistor M9, and the tenth MOS transistor M12 are PMOS transistors.
Further, as shown in fig. 1, in an embodiment, the compensation circuit includes: eleventh MOS transistor M3, first triode Q1, second triode Q2, first resistance R0 and second resistance R1. The grid of eleventh MOS pipe M3 links to each other with mirror circuit, the drain electrode of eleventh MOS pipe M3 links to each other with power supply end VDD, the source of eleventh MOS pipe M3 is grounded through first resistance R0, the base of first triode Q1 links to each other with the emitter of first triode Q1 after the base of second triode Q2 links to each other, the source of eleventh MOS pipe M3 links to each other, the collector of first triode Q1 is grounded, the collector of second triode Q2 is grounded, the emitter of second triode Q2 links to each other with one end of second resistance R1, super source follower circuit, the other end of second resistance R1 links to each other with power supply end VDD.
Further, as shown in fig. 1, in the embodiment, the eleventh MOS transistor M3 is an NMOS transistor.
Further, as shown in fig. 1, in an embodiment, the super source follower circuit includes: the system comprises a second operational amplifier I2 and a twelfth MOS tube M13, wherein the reverse input end of the second operational amplifier I2 is connected with a compensation circuit, the homodromous input end of the second operational amplifier I2 is connected with an operational amplifier tail current circuit, the output end of the second operational amplifier I2 is connected with the grid electrode of the twelfth MOS tube M13, the source electrode of the twelfth MOS tube M13 is connected with a power supply end VDD, and the drain electrode of the twelfth MOS tube M13 is connected with the operational amplifier tail current circuit.
Further, as shown in fig. 1, in the embodiment, the twelfth MOS transistor M13 is a PMOS transistor.
Further, as shown in fig. 1, in an embodiment, the op-amp tail current circuit includes: thirteenth MOS transistor M14, fourteenth MOS transistor M15, fifteenth MOS transistor M16, sixteenth MOS transistor M17, seventeenth MOS transistor M18, eighteenth MOS transistor 19, nineteenth MOS transistor M5, and twentieth MOS transistor M4. The source electrode of the thirteenth MOS tube M14 is connected with the super source follower circuit, the drain electrode of the eighteenth MOS tube 19 and the grid electrode of the nineteenth MOS tube M5, the grid electrode of the thirteenth MOS tube M14 is connected with the drain electrode of the thirteenth MOS tube M14 and the source electrode of the fourteenth MOS tube M15, the grid electrode of the fourteenth MOS tube M15 is connected with the drain electrode of the fourteenth MOS tube M15 and the source electrode of the fifteenth MOS tube M16, the grid electrode of the fifteenth MOS tube M16 is connected with the source electrode of the sixteenth MOS tube M17, the drain electrode of the fifteenth MOS tube M16, the super source follower circuit, the drain electrode of the nineteenth MOS tube M5 and the source electrode of the nineteenth MOS tube M5, the grid electrode of the sixteenth MOS tube M17 is connected with the drain electrode of the sixteenth MOS tube M17 and the source electrode of the seventeenth MOS tube M18, the grid electrode of the seventeenth MOS tube M18 is grounded, the source electrode of the eighteenth MOS tube M19 is connected with the grid electrode of the twentieth MOS tube M4 and then connected with the signal output end, and the drain electrode of the twentieth MOS tube M4 is grounded.
Further, as shown in fig. 1, in the embodiment, the eighteenth MOS transistor 19, the nineteenth MOS transistor M5, and the twentieth MOS transistor M4 are NMOS transistors, and the thirteenth MOS transistor M14, the fourteenth MOS transistor M15, the fifteenth MOS transistor M16, the sixteenth MOS transistor M17, and the seventeenth MOS transistor M18 are PMOS transistors.
In the above, the low-power consumption CMOS ultra-wide temperature range transient enhancement LDO circuit according to the embodiment of the invention is described with reference to fig. 1, which has the following advantages:
(1) The completion of the reference power supply through the design framework is not influenced by the influence of the process, and the consistency and stability of the reference power supply are maintained.
(2) The wide temperature of minus 40 ℃ to plus 150 ℃ is completed through the design framework, the positive temperature coefficient and the negative temperature coefficient are mutually offset, and the temperature is not affected at all.
(3) The super source stage follower is inserted into the grid electrode of the adjusting tube with larger parasitic capacitance and the output stage of the operational amplifier with higher output impedance, so that the large parasitic capacitance and the higher output impedance can be isolated, and the loop bandwidth of the LDO is expanded; the slew rate of the operational amplifier is increased, and the transient performance of the LDO is improved; the super source-stage follower has low input capacitance and small output impedance, and has good front-back impedance matching.
It should be noted that in this specification the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises an element.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.
Drawings
Fig. 1 is a circuit diagram of a low power CMOS ultra-wide temperature range transient enhancement LDO circuit according to an embodiment of the present invention.
Claims (6)
1. A low power CMOS ultra-wide temperature range transient enhanced LDO circuit, comprising:
the input end of the constant voltage source is connected with the first signal input end;
the inverting input end of the first operational amplifier is connected with the output end of the constant voltage source, and the first operational amplifier is connected with the first signal input end;
the mirror circuit is connected with the second signal input end, the power end and the first operational amplifier;
the compensation circuit is connected with the mirror image circuit and the power supply end;
the super source follower circuit is connected with the compensation circuit and the power supply end;
the operational amplifier tail current circuit is connected with the super source follower circuit, the power end and the signal output end;
the compensation circuit includes: the device comprises an eleventh MOS tube, a first triode, a second triode, a first resistor and a second resistor;
the grid electrode of the eleventh MOS tube is connected with the mirror circuit, the drain electrode of the eleventh MOS tube is connected with the power supply end, and the source electrode of the eleventh MOS tube is grounded through the first resistor;
the base electrode of the first triode is connected with the base electrode of the second triode and then is connected with the emitter electrode of the first triode and the source electrode of the eleventh MOS tube, and the collector electrode of the first triode is grounded;
the collector electrode of the second triode is grounded, and the emitter electrode of the second triode is connected with one end of the second resistor and the super source follower circuit;
the other end of the second resistor is connected with the power supply end;
the super source follower circuit includes: a second operational amplifier and a twelfth MOS transistor;
the reverse input end of the second operational amplifier is connected with the compensation circuit, the homodromous input end of the second operational amplifier is connected with the operational amplifier tail current circuit, and the output end of the second operational amplifier is connected with the grid electrode of the twelfth MOS tube;
the source electrode of the twelfth MOS tube is connected with the power supply end, and the drain electrode of the twelfth MOS tube is connected with the tail current circuit of the operational amplifier;
the tail current circuit of the operational amplifier comprises: thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, and twentieth MOS transistors;
the source electrode of the thirteenth MOS tube is connected with the super source follower circuit, the drain electrode of the eighteenth MOS tube and the grid electrode of the nineteenth MOS tube, and the grid electrode of the thirteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube and the source electrode of the fourteenth MOS tube;
the grid electrode of the fourteenth MOS tube is connected with the drain electrode of the fourteenth MOS tube and the source electrode of the fifteenth MOS tube;
the grid electrode of the fifteenth MOS tube is connected with the source electrode of the sixteenth MOS tube, the drain electrode of the fifteenth MOS tube, the super source follower circuit, the drain electrode of the nineteenth MOS tube and the source electrode of the nineteenth MOS tube;
the grid electrode of the sixteenth MOS tube is connected with the drain electrode of the sixteenth MOS tube and the source electrode of the seventeenth MOS tube;
the grid electrode of the seventeenth MOS tube and the drain electrode of the seventeenth MOS tube are grounded;
the source electrode of the eighteenth MOS tube is connected with the grid electrode of the twentieth MOS tube and then is connected with the signal output end, and the grid electrode of the eighteenth MOS tube, the source electrode of the twentieth MOS tube and the drain electrode of the twentieth MOS tube are grounded.
2. The low power CMOS ultra-wide temperature range transient enhanced LDO circuit of claim 1, wherein the mirroring circuit comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor;
the grid electrode of the first MOS tube, the grid electrode of the second MOS tube, the grid electrode of the third MOS tube and the drain electrode of the first MOS tube are connected and then connected with the second signal input end, and the source electrode of the first MOS tube is grounded;
the drain electrode of the second MOS tube is connected with the grid electrode of the fourth MOS tube and the drain electrode of the fourth MOS tube, and the source electrode of the second MOS tube is grounded;
the drain electrode of the third MOS tube is connected with the drain electrode of the fifth MOS tube, and the source electrode of the third MOS tube is grounded;
the source electrode of the fourth MOS tube is connected with the power supply end;
the grid electrode of the fifth MOS tube, the grid electrode of the sixth MOS tube, the grid electrode of the tenth MOS tube and the compensation circuit are connected, and the source electrode of the fifth MOS tube is connected with the power supply end;
the drain electrode of the sixth MOS tube is connected with the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube and the grid electrode of the ninth MOS tube, and the source electrode of the sixth MOS tube is connected with the power supply end;
the grid electrode of the seventh MOS tube is connected with the output end of the first operational amplifier, the drain electrode of the seventh MOS tube is connected with the drain electrode of the ninth MOS tube and the same-direction input end of the first operational amplifier, and the source electrode of the seventh MOS tube is connected with the drain electrode of the tenth MOS tube;
the source electrode of the eighth MOS tube is grounded;
the source electrode of the ninth MOS tube is grounded;
and the source electrode of the tenth MOS tube is connected with the power supply end.
3. The low-power CMOS ultra-wide temperature range transient enhancement LDO circuit of claim 2, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the eighth MOS transistor, the ninth MOS transistor are NMOS transistors, and the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the tenth MOS transistor are PMOS transistors.
4. The low power CMOS ultra wide temperature range transient enhanced LDO circuit of claim 1, wherein the eleventh MOS transistor is an NMOS transistor.
5. The low power CMOS ultra wide temperature range transient enhanced LDO circuit of claim 1, wherein the twelfth MOS transistor is a PMOS transistor.
6. The low power CMOS ultra wide temperature range transient enhancement LDO circuit of claim 1, wherein the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor are NMOS transistors, and the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor are PMOS transistors.
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| CN202111619211.XA CN114356016B (en) | 2021-12-28 | 2021-12-28 | Low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit |
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