CN108021169A - A kind of LDO circuit - Google Patents
A kind of LDO circuit Download PDFInfo
- Publication number
- CN108021169A CN108021169A CN201610943943.7A CN201610943943A CN108021169A CN 108021169 A CN108021169 A CN 108021169A CN 201610943943 A CN201610943943 A CN 201610943943A CN 108021169 A CN108021169 A CN 108021169A
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- ldo
- source
- grid
- drain electrode
- nmos tube
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The present invention provides a kind of LDO circuit, the LDO circuit includes a reference source, difference amplifier, LDO output stages.The a reference source provides a reference voltage and a reference current bias voltage；The reference voltage of the first input end connection a reference source output of the difference amplifier, the second input terminal connect the output voltage of the LDO, and the output terminal of the difference amplifier is connected to the grid of the LDO output powers pipe.Difference amplifier and LDO output stages form closed circuit, make output voltage stabilization to reference voltage.The LDO output stages of the present invention include a tail current source NM6, can reduce the fluctuation of output voltage.LDO circuit is simple in structure, relatively low to technological requirement, reduces the complexity of chip design.
Description
Technical field
The present invention relates to chip power management domain, more particularly to a kind of low-power consumption linear voltage regulator (Low Drop-
Out, LDO) circuit.
Background technology
In recent years, with the continuous development of technology of Internet of things, many equipment are required for using battery powered.Set to extend
How standby usage time, reduce the power consumption of chip as the important topic in chip design.In chip in use, many feelings
Chip can be in low-power consumption standby state under condition.Just the LDO circuit of a low-power consumption is needed to provide power supply for chip at this time.
Traditional LDO circuit is made of bandgap reference circuit, the part such as difference amplifier and resistance pressure-dividing network, its structure
As shown in Figure 1.The reference voltage VREF that LDO circuit is produced according to band-gap reference produces output voltage VO UT, output voltage VO UT
There is provided feedback voltage V FB by the noninverting input after feedback resistance R11 and R12 partial pressure for difference amplifier A1, it is described instead
The expression formula of feedthrough voltage VFB is：
VFB=(R12 ÷ (R11+R12)) × VOUT；
Reference voltage VREF and feedback voltage V FB are compared to obtain difference DELTA V and by difference DELTA V by difference amplifier A1
Vdrive is obtained after amplification, Vdrive is used for the grid for driving the power output PMOS transistor M1, passes through work(so as to change
The electric current of rate output PMOS transistor M1 so that feedback voltage V FB and reference voltage VREF approximately equals, so that output electricity
The magnitude of voltage of pressure VOUT tends to be constant.
In traditional LDO circuit structure, bandgap reference circuit and difference amplifier are required to consumption power consumption, therefore reduce and pass
There is limitation in the LDO circuit power consumption for structure of uniting.
Chip operation required electric current meeting very little in holding state, if in this case using tradition LDO electricity
Lu Weiqi powers, it is possible that the quiescent current that LDO circuit consumes in itself is more than the situation that chip consumes electric current in itself.
In addition traditional LDO circuit structure also needs to compensate to ensure the stability of loop, so that circuit
Design complexities increase.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of LDO circuit, can reduce the power consumption of circuit and answering for realization
Miscellaneous degree, and reduce the fluctuation of supply voltage.
The technical solution adopted by the present invention is as follows：A kind of LDO circuit, including be linked in sequence a reference source, difference amplifier
With LDO output stages；
The a reference source is used to provide reference voltage to difference amplifier, there is provided reference current bias voltage to differential amplification
Device and LDO output stages；
The differential amplifier circuit is used to carry out the potential difference between the output voltage and reference voltage of LDO output stages
Amplify and export to LDO output stages, reference current bias voltage and the bias voltage of tail current source is provided for differential amplifier circuit；
The difference amplifier includes Differential Input to pipe, current mirror, tail current source；Differential Input is to pipe and current mirror, tail current source
Connection, is also connected with a reference source, LDO output stages；
The LDO output stages receive reference current bias voltage, and LDO is exported based on the output of differential amplifier circuit
The output voltage of level is controlled.
The a reference source includes PMOS tube PM1 and NMOS tube NM1；The source electrode connection current source of the PM1, it is also defeated with difference
Enter and pipe is connected, grid is connected with drain electrode, and the drain electrode with NM1 that drains, grid are connected, and are also connected with tail current source, source electrode ground connection.
The Differential Input includes NMOS tube NM2 and NMOS tube NM3 to pipe；The source electrode of NM2 and NM3 connects with tail current source
Connect, the drain electrode of NM2 is connected with power supply, and the drain electrode of NM3 is connected with current mirror；The grid of NM2 is connected with the source electrode of a reference source PM1,
The grid of NM3 is connected with LDO output stages.
The current mirror includes PMOS tube PM2 and PMOS tube PM3；The source electrode of the PM2 and PM3 are connected with power supply, grid
Interconnection；The drain electrode of PM2 is connected with grid, is also connected with drain electrode of the Differential Input to the NM3 of pipe；The drain electrode of PM3 and tail current source
Connected with LDO output stages.
The tail current source includes NMOS tube NM4 and NMOS tube MN5；The grid of the NM4, the grid of NM5 and a reference source
The grid of NM1, the connection of LDO output stages, the source electrode ground connection of the source electrode of NM4 and NM5, the drain electrode of NM4 is with Differential Input to pipe NM2
Source electrode, NM3 source electrode connection；The drain electrode of NM5 and the drain electrode of the PM3 of current mirror connect.
The LDO output stages include PMOS tube PM4 and NMOS tube NM6；The source electrode of PM4 is connected with power supply, grid and electric current
The drain electrode connection of the PM3 of mirror, drain electrode are connected as output terminal for output voltage VO UT to power source loads, and with the drain electrode of NM6；
The grid of the NM1 of the source electrode ground connection of NM6, grid and a reference source connects.
The breadth length ratio of the NMOS tube NM1, NMOS tube NM5 and NMOS tube NM6 are equal.
The breadth length ratio of the NMOS tube NM4 is twice of NMOS tube NM1.
The breadth length ratio of the NMOS tube NM2 and NMOS tube NM3 are equal.
The breadth length ratio of the PMOS tube PM2 and PMOS tube PM3 are equal.
Beneficial effects of the present invention and advantage：
1. the LDO circuit of the present invention only needs the electric current of na level just to work normally, the power consumption of circuit can be reduced.
2. the LDO output stages of the present invention include a tail current source NM6, the fluctuation of output voltage can be reduced.
3. the LDO circuit of the present invention is simple in structure, relatively low to technological requirement, the complexity of chip design is reduced.
Brief description of the drawings
Fig. 1 is traditional LDO circuit schematic diagram.
Fig. 2 is the structure diagram of the LDO circuit of the embodiment of the present invention.
Embodiment
LDO circuit proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
LDO circuit provided by the invention includes a reference source, difference amplifier, LDO output stages.The a reference source provides one
Reference voltage and a reference current bias voltage；The benchmark of the first input end connection a reference source output of the difference amplifier
Voltage, the second input terminal connect the output voltage of LDO, and output terminal is connected to the grid of the LDO output powers pipe, and tail current is inclined
Put the reference current bias voltage that voltage is all connected with a reference source output.
The a reference source includes the first PMOS tube, the first NMOS tube.
The source electrode connection input current source of first PMOS tube, the reference voltage of formation a reference source output, described first
The drain electrode of PMOS tube connects the grid of first PMOS tube.The drain electrode of first NMOS tube connects first NMOS tube
The drain electrode of grid and first PMOS tube, forms reference current bias voltage, the source electrode ground connection of first NMOS tube.
The difference amplifier includes a pair of of Differential Input pipe, a pair of of current mirror and two tail current sources.The difference is defeated
Entering pipe includes the second NMOS tube and the 3rd NMOS tube, and the current mirror includes the second PMOS tube and the 3rd PMOS tube, the tail electricity
Stream source includes the 4th NMOS tube and the 5th NMOS tube.The drain electrode connection supply voltage of second NMOS tube, the 2nd NMOS
The grid of pipe connects the source electrode of first PMOS tube, and the source electrode of second NMOS tube connects the leakage of the 4th NMOS tube
Pole.The drain electrode of 3rd NMOS tube connects the drain electrode of second PMOS tube, the grid connection LDO's of the 3rd NMOS tube
Output voltage, the source electrode of the 3rd NMOS tube connect the drain electrode of the 4th NMOS tube.The drain electrode of second PMOS tube connects
Connect the grid of second PMOS tube, the source electrode connection supply voltage of second PMOS tube.The drain electrode of 3rd PMOS tube
The drain electrode of the 5th NMOS tube is connected, forms the output terminal of difference amplifier, described in the grid connection of the 3rd PMOS tube
The grid of second PMOS tube, the source electrode connection supply voltage of the 3rd PMOS tube.4th NMOS tube and the 5th NMOS tube
Grid be all connected with the grid of first NMOS tube, the source grounding of the 4th NMOS tube and the 5th NMOS tube.
The LDO output stages include referring to the 4th PMOS tube, the 6th NMOS tube.The source electrode connection power supply of 4th PMOS tube
Voltage, the 4th PMOS tube grid connection difference amplifier output terminal, the 4th PMOS tube drain electrode connection described in
The drain electrode of 6th NMOS tube, forms the output voltage of the LDO.The grid of 6th NMOS tube connects first NMOS tube
Grid, the 6th NMOS tube source electrode ground connection.
Preferably, in the LDO circuit, the ruler of first NMOS tube, the 5th NMOS tube and the 6th NMOS tube
It is very little to be equal.
Preferably, in the LDO circuit, the breadth length ratio of the 4th NMOS tube is twice of the first NMOS tube.
Preferably, in the LDO circuit, second NMOS tube and the 3rd NMOS tube it is equal sized.
Preferably, in the LDO circuit, second PMOS tube and the 3rd PMOS tube it is equal sized.
Please refer to Fig.2, it is the structure diagram of the LDO circuit of the embodiment of the present invention.As shown in Fig. 2, the LDO circuit
Including a reference source, difference amplifier, LDO output stages.Wherein, a reference source includes the first PMOS tube PM1 and the first NMOS tube
NM1；The difference amplifier includes the Differential Input of the second NMOS tube NM2 and the 3rd NMOS tube NM3 compositions to pipe, the 2nd PMOS
The current mirror of pipe PM2 and the 3rd PMOS tube PM3 compositions, and two tails of the 4th NMOS tube NM4 and the 5th NMOS tube NM5 compositions
Current source.The LDO output stages include the LDO output adjustments pipe of the 4th PMOS tube PM4 compositions, the 6th NMOS tube NM6 is formed
Tail current source.
Specifically, the source electrode ground connection of the first NMOS tube NM1 described in a reference source, the drain and gate of the NM1 connect
Connect, form diode connection, the grid of the NM1 produces reference current bias voltage, the reference current bias voltage connection
The grid of described tail current source NM4, NM5 and NM6.The source electrode connection input current source of the PM1, the grid of PM1 and drain electrode connect
Connect, form diode connection.The one NMOS tube NM1 and a PMOS tube using diode connection using diode connection
PM1 produces reference voltage V REF, about Vgsn+ | Vgsp |, Vgsn, Vgsp are respectively the first NMOS tube NM1 and the first PMOS tube
The gate source voltage of PM1.
The Differential Input of the difference amplifier connects the source electrode of pipe NM2 and NM3 the leakage of the tail current source NM4 at the same time
Pole, the drain electrode of the drain electrode connection supply voltage VCC, the NM3 of the NM2 connect the current mirror input terminal PM2 grid and
Drain electrode, and the grid of PM3.The source electrode of the current mirror PM2 and PM3 is all connected with supply voltage VCC.The current mirror outputs
The drain electrode of the drain electrode connection tail current source NM5 of PM3, forms the output of difference amplifier.The grid of the NM2 forms the difference
The negative input of amplifier, the grid of the NM3 form the positive input of the difference amplifier.
The grid that the source electrode of the LDO output adjustments pipe PM4 meets supply voltage VCC, the PM4 connects the defeated of difference amplifier
Outlet, the drain electrode of the PM4 are connected with the drain electrode of tail current source NM6, form the output voltage VO UT of the LDO.
The size of described tail current source NM5, NM6 are identical with the size of NM1, the bias current of tail current source NM5, NM6
Equal to IB.The breadth length ratio of the tail current source NM4 is two times of the breadth length ratio of NM1, and the bias current of tail current source NM4 is equal to
2IB。
The positive input of the difference amplifier connects the output voltage VO UT of the LDO, the difference amplifier
Negative input connects the reference voltage V REF.When the LDO output voltage VOs UT is less than the reference voltage V REF, institute
The output end voltage for stating difference amplifier is lower, and the drain potential of the LDO output adjustments pipe PM4 becomes higher, and is correspondingly improved institute
State LDO output voltage VOs UT.When the LDO output voltage VOs UT is higher than the reference voltage V REF, the difference amplifier
Output end voltage become higher, the drain potential of the LDO output adjustments pipe PM4 is lower, and reduces the LDO output voltages accordingly
VOUT.Under the equilibrium state of the LDO circuit, the LDO output voltage VOs UT is equal to the reference voltage V REF.The LDO
Circuit can provide stable voltage output.
The reference voltage V REF, about Vgsn+ | Vgsp |, it is about 1.7V-1.8V under general technology, can meets chip
Supply voltage requirement under holding state.In the case of identical bias current, the first NMOS tube NM1 and first is adjusted
The breadth length ratio of PMOS tube PM1, can obtain different VREF so that the output voltage of the LDO circuit is adjustable.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims.
Claims (10)
1. a kind of LDO circuit, it is characterised in that including a reference source, difference amplifier and the LDO output stages being linked in sequence；
The a reference source be used for provide reference voltage to difference amplifier, there is provided reference current bias voltage to difference amplifier and
LDO output stages；
The differential amplifier circuit is used to be amplified the potential difference between the output voltage and reference voltage of LDO output stages
And export to LDO output stages, reference current bias voltage and the bias voltage of tail current source is provided for differential amplifier circuit；It is described
Difference amplifier includes Differential Input to pipe, current mirror, tail current source；Differential Input is connected pipe with current mirror, tail current source,
Also it is connected with a reference source, LDO output stages；
The LDO output stages receive reference current bias voltage, and based on the output of differential amplifier circuit to LDO output stages
Output voltage is controlled.
2. a kind of LDO circuit according to claim 1, it is characterised in that a reference source includes PMOS tube PM1 and NMOS
Pipe NM1；The source electrode connection current source of the PM1, is also connected pipe with Differential Input, and grid is connected with drain electrode, and drain electrode is with NM1's
Drain electrode, grid connection, are also connected with tail current source, source electrode ground connection.
3. a kind of LDO circuit according to claim 1, it is characterised in that the Differential Input includes NMOS tube NM2 to pipe
With NMOS tube NM3；The source electrode of NM2 and NM3 is connected with tail current source, and the drain electrode of NM2 is connected with power supply, the drain electrode of NM3 and electric current
Mirror connects；The grid of NM2 is connected with the source electrode of a reference source PM1, and the grid of NM3 is connected with LDO output stages.
4. a kind of LDO circuit according to claim 1, it is characterised in that the current mirror includes PMOS tube PM2 and PMOS
Pipe PM3；The source electrode of the PM2 and PM3 are connected with power supply, gate interconnection；The drain electrode of PM2 is connected with grid, and also and Differential Input
Drain electrode to the NM3 of pipe connects；The drain electrode of PM3 is connected with tail current source and LDO output stages.
A kind of 5. LDO circuit according to claim 1, it is characterised in that the tail current source include NMOS tube NM4 and
NMOS tube MN5；The grid of the NM1 of the grid of the NM4, the grid of NM5 and a reference source, the connection of LDO output stages, the source electrode of NM4
It is grounded with the source electrode of NM5, the drain electrode of NM4 is connected the source electrode of pipe NM2, the source electrode of NM3 with Differential Input；The drain electrode of NM5 and electricity
Flow the drain electrode connection of the PM3 of mirror.
A kind of 6. LDO circuit according to claim 1, it is characterised in that the LDO output stages include PMOS tube PM4 and
NMOS tube NM6；The source electrode of PM4 is connected with power supply, and the drain electrode connection of the PM3 of grid and current mirror, drains and be used for as output terminal
Output voltage VO UT is connected to power source loads, and with the drain electrode of NM6；The grid of the NM1 of the source electrode ground connection of NM6, grid and a reference source
Pole connects.
7. a kind of LDO circuit according to claim 2, it is characterised in that the NMOS tube NM1, NMOS tube NM5 and NMOS
The breadth length ratio of pipe NM6 is equal.
8. a kind of LDO circuit according to claim 5, it is characterised in that the breadth length ratio of the NMOS tube NM4 is NMOS tube
Twice of NM1.
9. according to claim 3 in the LDO circuit, it is characterised in that the width of the NMOS tube NM2 and NMOS tube NM3 are long
Than equal.
10. according to claim 4 in the LDO circuit, it is characterised in that the width of the PMOS tube PM2 and PMOS tube PM3
Length is than equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610943943.7A CN108021169A (en) | 2016-11-02 | 2016-11-02 | A kind of LDO circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610943943.7A CN108021169A (en) | 2016-11-02 | 2016-11-02 | A kind of LDO circuit |
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| Publication Number | Publication Date |
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| CN108021169A true CN108021169A (en) | 2018-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610943943.7A Pending CN108021169A (en) | 2016-11-02 | 2016-11-02 | A kind of LDO circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112034924A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
| CN114167938A (en) * | 2021-10-12 | 2022-03-11 | 广东赛微微电子股份有限公司 | Power management chip, linear voltage stabilizing circuit and bias current compensation method thereof |
| CN114356016A (en) * | 2021-12-28 | 2022-04-15 | 上海兴赛电子科技有限公司 | Low-power-consumption CMOS ultra-wide temperature range transient enhanced LDO circuit |
| CN114442717A (en) * | 2022-01-21 | 2022-05-06 | 星宸科技股份有限公司 | Low dropout regulator with bidirectional current regulation |
| CN114489209A (en) * | 2022-01-12 | 2022-05-13 | 普冉半导体(上海)股份有限公司 | Low-power-supply-voltage accurate voltage following circuit and voltage following method |
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
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| JP2000138576A (en) * | 1998-10-29 | 2000-05-16 | Fujitsu Ltd | Differential amplifier circuit |
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| US20130307622A1 (en) * | 2012-05-15 | 2013-11-21 | Elpida Memory, Inc. | Differential amplifier circuit having plural current mirror circuits |
| CN104317345A (en) * | 2014-10-28 | 2015-01-28 | 长沙景嘉微电子股份有限公司 | Low dropout regulator on basis of active feedback network |
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| JPH1064261A (en) * | 1996-08-27 | 1998-03-06 | Hitachi Ltd | Semiconductor integrated circuit |
| US6259316B1 (en) * | 1998-05-29 | 2001-07-10 | Texas Instruments Incorporated | Low voltage buffer amplifier for high speed sample and hold applications |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112034924A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Self-adaptive fast response LDO (low dropout regulator) circuit and chip thereof |
| CN114167938A (en) * | 2021-10-12 | 2022-03-11 | 广东赛微微电子股份有限公司 | Power management chip, linear voltage stabilizing circuit and bias current compensation method thereof |
| CN114356016A (en) * | 2021-12-28 | 2022-04-15 | 上海兴赛电子科技有限公司 | Low-power-consumption CMOS ultra-wide temperature range transient enhanced LDO circuit |
| CN114356016B (en) * | 2021-12-28 | 2024-02-09 | 上海兴赛电子科技有限公司 | Low-power consumption CMOS ultra-wide temperature range transient enhanced LDO circuit |
| CN114489209A (en) * | 2022-01-12 | 2022-05-13 | 普冉半导体(上海)股份有限公司 | Low-power-supply-voltage accurate voltage following circuit and voltage following method |
| CN114489209B (en) * | 2022-01-12 | 2024-01-19 | 普冉半导体(上海)股份有限公司 | Low-power-supply-voltage accurate voltage following circuit and voltage following method |
| CN114442717A (en) * | 2022-01-21 | 2022-05-06 | 星宸科技股份有限公司 | Low dropout regulator with bidirectional current regulation |
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
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