CN116149419A - High power supply rejection ratio LDO circuit applicable to medium and high frequencies - Google Patents
High power supply rejection ratio LDO circuit applicable to medium and high frequencies Download PDFInfo
- Publication number
- CN116149419A CN116149419A CN202310409345.1A CN202310409345A CN116149419A CN 116149419 A CN116149419 A CN 116149419A CN 202310409345 A CN202310409345 A CN 202310409345A CN 116149419 A CN116149419 A CN 116149419A
- Authority
- CN
- China
- Prior art keywords
- transistor
- output
- terminal
- circuit
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to a high power supply rejection ratio LDO circuit applicable to medium and high frequencies, wherein the input end of a current source is connected with the input end of an adjusting tube MP to supply power, and the output end of the current source is connected with the power input end of a buffer circuit and the power input end of a reference circuit; the output end of the reference circuit is connected with the non-inverting input end of the buffer circuit, the inverting input end of the buffer circuit is connected with the output end of the buffer circuit, the output end of the buffer circuit is connected with the positive electrode end of the capacitor Ch and the inverting input end of the error amplifier, and the negative electrode end of the capacitor Ch is connected with the grounding end; the output end of the error amplifier is connected with the regulating tube MP and the input end of the output current sampling circuit, the output end of the output current sampling circuit is connected with the dynamic bias input end of the error amplifier, the regulating tube MP is connected with the non-inverting input end of the error amplifier through the resistance feedback circuit, and the common end of the regulating tube MP and the feedback circuit is used as the output end of the low-dropout linear regulator circuit.
Description
Technical Field
The invention relates to the technical field of voltage regulators, in particular to a high power supply rejection ratio LDO circuit applicable to medium and high frequencies.
Background
The low-dropout linear voltage regulator has the advantages of small output noise, simple circuit structure, small occupied chip area, small voltage ripple and the like, and becomes an important circuit in a power management chip. Particularly in mobile devices, the ultra-low static power consumption of the low dropout linear regulator is more advantageous. The ultra-low static power consumption can prolong the service time, the service life and the like of the battery. Therefore, the low power consumption design is also an important index in the low dropout linear regulator design. However, low quiescent current affects other parameters of the low dropout linear regulator, such as: load transient response, power Supply Rejection Ratio (PSRR), output noise, etc.
Among them, low static power consumption and Power Supply Rejection Ratio (PSRR) are key performance indicators of linear regulators. While the supply rejection ratio is often dependent on the supply rejection ratio of the bandgap reference and the open loop gain of the linear regulator error amplifier loop. In general, in order to obtain a higher power supply rejection ratio, a linear voltage regulator adopts a larger open loop gain of an error amplifier or increases a coupling capacitance of an output terminal. The adoption of a larger open loop gain of an error amplifier, such as a multi-stage operational amplifier, not only increases the power consumption and the area of a chip, but also brings great challenges to circuit design. The mode of increasing the coupling capacitance of the output end increases the area of a chip and increases the production cost, and at the same time, the method can lead to the bandwidth reduction of the linear voltage stabilizer, along with the development of technology, people start to adopt an error amplifier with dynamic tail current by sampling load current to ensure that the bandwidth of the error amplifier is widened on the premise of not obviously damaging the gain of the error amplifier, and the power supply rejection ratio of the linear voltage stabilizer can be improved to a certain extent at medium and high frequencies, but the effect is still not quite obvious.
With the increase of the requirements of users on the power ripple suppression capability, the linear voltage stabilizer with low power consumption and high power supply suppression ratio still has the power supply suppression ratio of more than 60dB at a higher frequency band. This is also a challenge for low power circuit designs, because the quiescent current of the circuit is low and the bandwidth of the overall system will be reduced, and thus the power supply rejection ratio of the high frequency band will be limited.
In the conventional method, the inverting input end of the error amplifier is directly connected with the output end of the reference circuit, and as the effect of the error amplifier EA is to compare the feedback voltage with the reference voltage Vref generated by the reference circuit to generate an error signal, the error signal is amplified to regulate the regulating tube Mp, so that the output voltage of the whole circuit is finally stable; therefore, the performance of the error amplifier EA directly affects various performance parameters of the whole circuit, such as the power supply rejection ratio, the load adjustment ratio, the linear adjustment ratio, etc., and the power supply rejection ratio of the reference circuit generating the reference voltage Vref is equally important in order to achieve a higher power supply rejection ratio in the middle-high frequency band and to achieve a very small power supply noise carried by the reference voltage Vref input to the error amplifier in the middle-high frequency band, from the index of the power supply rejection ratio alone. In view of this, it is generally required that the error amplifier EA has a higher gain in a wider frequency band, and is implemented by using a dynamic current bias error amplifier, but under the loaded condition, since the bias current in the circuit increases with the load current, a low-resistance channel from the power supply to the EA input terminal is formed in the EA under the middle-high frequency application condition, if the output terminal of the reference circuit is directly connected to the input terminal of the error amplifier, the output terminal of the reference circuit is in a high-resistance state, which will cause the power supply rejection performance of the reference circuit to be greatly reduced, so that the power supply rejection ratio of the low-dropout linear voltage regulator circuit simply adopting such a structure in the middle-high frequency band is not very obvious.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a high power supply rejection ratio LDO circuit applicable to medium and high frequencies, which aims to solve the problem that the power supply rejection ratio of the traditional low-dropout linear voltage regulator circuit in the medium and high frequency ranges is not obviously improved.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the high power supply rejection ratio LDO circuit comprises a power supply, a current source, a reference circuit, a buffer circuit, an error amplifier with dynamic current bias, an output current sampling circuit, an adjusting tube MP and a resistance feedback circuit; the input end of the current source is connected with the power supply, and the output end of the current source is connected with the power supply input end of the buffer circuit and the power supply input end of the reference circuit; the output end of the reference circuit is connected with the non-inverting input end of the buffer circuitThe output end of the buffer circuit is connected with the positive electrode end of a capacitor Ch and the inverting input end of the error amplifier, and the negative electrode end of the capacitor Ch is connected with the grounding end; the output end of the error amplifier is connected with the control end of the adjusting tube MP and the input end of the output current sampling circuit, the output end of the output current sampling circuit is connected with the dynamic bias input end of the error amplifier, and the output end of the adjusting tube MP is connected with the non-inverting input end of the error amplifier through the resistance feedback circuit; the input end of the adjusting tube MP is connected with the power supply, and the common end of the adjusting tube MP and the feedback circuit is used as the output end of the low-dropout linear voltage regulator circuit; the error amplifier outputs a feedback voltage V from the feedback circuit FB With the output voltage V of the buffer circuit REF-buff The comparison produces an error signal which is amplified and thus regulated by the regulator tube MP.
As a preferred embodiment, the error amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor 12, a thirteenth transistor M13, and a parasitic capacitance C1; an input terminal of the eleventh transistor M11 is connected with the power supply, and a control terminal of the eleventh transistor M11 is connected with the bias voltage V b4 An output terminal of the eleventh transistor M11 is connected to the input terminal of the first transistor M1 and the input terminal of the second transistor M2, respectively; the control end of the first transistor M1 is used as the inverting input end of the error amplifier to be connected with the output voltage V of the buffer circuit REF-buff The input end of the first transistor M1 is connected to the positive end of the parasitic capacitor C1, the control end of the first transistor M1 is connected to the negative end of the parasitic capacitor C1, and the second transistor M2 is used as the non-inverting input end of the error amplifier; the input end of the third transistor M3 and the input end of the fourth transistor M4 are connectedThe output end and the control end of the third transistor M3 are connected with the control end of the fourth transistor M4; an input terminal of the fifth transistor M5 is connected to an output terminal of the third transistor M3, a control terminal of the fifth transistor M5 is connected to a control terminal of the sixth transistor M6, and a common terminal of the two control terminals is connected to a first bias voltage V b1 An input end of the sixth transistor M6 is connected to an output end of the fourth transistor M4; an input terminal of the seventh transistor M7 is connected to the output terminal of the fifth transistor M5, a control terminal of the seventh transistor M7 is connected to the control terminal of the eighth transistor M8, and a common terminal of the two control terminals is connected to the second bias voltage V b2 An input terminal of the eighth transistor M8 is connected to an output terminal of the sixth transistor M6, wherein a common terminal of the eighth transistor M8 and the sixth transistor M6 is connected to a control terminal of the twelfth transistor M12; an input terminal of the ninth transistor M9 is connected with the output terminal of the seventh transistor M7, an input terminal of the ninth transistor M9 is connected with the output terminal of the first transistor M1, an output terminal of the ninth transistor M9 is connected with a ground terminal, a control terminal of the ninth transistor M9 is connected with a control terminal of the tenth transistor M10, and a common terminal of the two control terminals is connected with a third bias voltage V b3 An input end of the tenth transistor M10 is connected to an output end of the eighth transistor M8, an input end of the tenth transistor M10 is connected to an output end of the second transistor M2 and a control end of the thirteenth transistor M13, and an output end of the tenth transistor M10 is connected to a ground end; the input end of the twelfth transistor M12 is connected to the power supply, the output end of the thirteenth transistor M13 is connected to the ground, and the output end of the twelfth transistor M12 is connected to the input end of the thirteenth transistor M13, wherein the common end of the twelfth transistor M12 and the thirteenth transistor M13 is used as the output end of the error amplifier.
Preferably, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 are PMOS transistors; the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 are NMOS transistors.
As a preferred aspect, the buffer circuit includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; the input end of the seventeenth transistor M17 and the input end of the eighteenth transistor M18 are both connected to the power supply, the output end of the eighteenth transistor M18 is connected to the input end of the fourteenth transistor M14, the control end of the eighteenth transistor M18 is connected to the control end of the seventeenth transistor M17, the common end of the two control ends is connected to the input end of the fourteenth transistor M14, the output end of the seventeenth transistor M17 is connected to the input end of the fifteenth transistor M15, and the output end of the seventeenth transistor M17 and the input end of the fifteenth transistor M15 are used as the output ends of the buffer circuit; the control end of the fourteenth transistor M14 is used as the non-inverting input end of the buffer circuit to be connected with a reference voltage source V REF An output terminal of the fourteenth transistor M14 is connected to an output terminal of the fifteenth transistor M15, a common terminal of the two output terminals is connected to an input terminal of the sixteenth transistor M16, and the fifteenth transistor M15 is connected to an anode terminal of the capacitor Ch as an output terminal of the buffer circuit; an output terminal of the sixteenth transistor M16 is connected to the ground terminal, and a control terminal of the sixteenth transistor M16 is connected to the fifth bias voltage V b5 。
As a preferable solution, the seventeenth transistor M17 and the eighteenth transistor M18 are PMOS transistors; the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are NMOS transistors.
As a preferred solution, the output current sampling circuit includes a nineteenth transistor M19, a twentieth transistor M20, and a twenty first transistor M21; an input end of the nineteenth transistor M19 is connected to the power supply, a control end of the nineteenth transistor M19 is used as an input end of the output current sampling circuit and is connected to an output end of the error amplifier and a control end of the adjusting transistor MP, and an output end of the nineteenth transistor M19 is connected to an input end of the twenty first transistor M21; an input end of the twentieth transistor M20 is used as an output end of the output current sampling circuit and is connected with a dynamic bias input end of the error amplifier, a control end of the twentieth transistor M20 is connected with a control end of the twenty-first transistor M21, and a common end of the two control ends is connected with an output end of the nineteenth transistor M19; the output terminal of the twentieth transistor M20 and the output terminal of the twenty-first transistor M21 are both connected to the ground terminal.
Preferably, the nineteenth transistor M19 is a PMOS transistor, and the twentieth transistor M20 and the twenty first transistor M21 are NMOS transistors.
Preferably, the resistor feedback circuit comprises a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the output end of the regulator MP, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the ground end and the negative end of the capacitor Ch, and the common end of the first resistor R1 and the second resistor R2 is used as the output end of the resistor feedback circuit to be connected to the non-inverting input end of the error amplifier.
The high power supply rejection ratio LDO circuit capable of being applied to medium and high frequencies has the beneficial effects that:
the power supply input ends of the reference circuit and the buffer circuit are connected with the output ends of the current sources, so that the connection with a power supply is completed, and the current sources can preprocess power supply noise in the connection mode of adding the current sources, so that the power supply rejection ratio of the reference circuit and the buffer circuit is further improved. The output current sampling circuit feeds back the sampling load current to the bias current in the error amplifier, and the dynamic bias current distribution circuit is adopted to improve the gain and bandwidth of the error amplifier at the middle-high frequency working frequency. By introducing the buffer circuit with high power supply rejection ratio, the characteristics of high input impedance and low output impedance of the buffer circuit are utilized to isolate the reference circuit from the error amplifier circuit, so that the interference of power supply noise to the output of the reference circuit through a low-resistance channel formed by an error amplifier with a load current sampling feedback technology under the condition of medium and high frequency is effectively solved, the load current sampling technology is ensured to improve the gain of the medium and high frequency, the bandwidth is increased, the adverse effect of the medium and high frequency on the power supply rejection ratio of the LDO caused by the technology is eliminated, the power supply rejection ratio of the LDO loop at the medium and high frequency is further increased, the power supply rejection ratio of the medium and low frequency is not influenced by the dynamic current of the error amplifier, a higher level is still maintained, meanwhile, the capacitor Ch under the condition of the medium and high frequency is connected, the influence of the power supply noise from the internal channel of the error amplifier on the output end of the buffer circuit is greatly reduced, and the power supply rejection ratio of the LDO at the medium and high frequency is ensured.
Drawings
FIG. 1 is one of the circuit blocks of a high power rejection ratio LDO circuit applicable to medium and high frequencies of the present invention;
FIG. 2 is a circuit block diagram of a buffer circuit of the present invention coupled to an error amplifier;
FIG. 3 is a circuit block diagram of a buffer circuit of the present invention;
FIG. 4 is a second circuit block diagram of a high power rejection ratio LDO circuit applicable to medium and high frequencies of the present invention;
FIG. 5 is a circuit block diagram of a conventional reference circuit directly connected to an error amplifier;
FIG. 6 is a graph comparing the power rejection ratio of a conventional high power rejection ratio LDO circuit (curve one) with that of the present invention applicable to medium and high frequencies.
Detailed Description
The invention will be further described with reference to the drawings and the specific embodiments.
As shown in FIG. 1, the high power supply rejection ratio LDO circuit applicable to medium and high frequencies comprises a power supply, a current source, a reference circuit, a buffer circuit, an error amplifier with dynamic current bias and an output current sampling circuitThe circuit, the adjusting tube MP and the resistance feedback circuit. The input end of the current source is connected with a power supply, and the output end of the current source is connected with the power supply input end of the buffer circuit and the power supply input end of the reference circuit; the output end of the reference circuit is connected with the non-inverting input end of the buffer circuit, the inverting input end of the buffer circuit is connected with the output end of the buffer circuit, the output end of the buffer circuit is connected with the positive electrode end of the capacitor Ch and the inverting input end of the error amplifier, and the negative electrode end of the capacitor Ch is connected with the grounding end; the output end of the error amplifier is connected with the control end of the adjusting tube MP and the input end of the output current sampling circuit, the output end of the output current sampling circuit is connected with the dynamic bias input end of the error amplifier, and the output end of the adjusting tube MP is connected with the non-inverting input end of the error amplifier through the resistor feedback circuit; the input end of the adjusting tube MP is connected with a power supply, and the common end of the adjusting tube MP and the feedback circuit is used as the output end of the low-dropout linear voltage regulator circuit; the error amplifier outputs the feedback voltage V from the feedback circuit FB Output voltage V of buffer circuit REF-buff The comparison produces an error signal which is amplified and thus adjusts the regulator tube MP.
The power supply input ends of the reference circuit and the buffer circuit are connected with the output ends of the current sources, so that the connection with a power supply is completed, and the current sources can preprocess power supply noise in the connection mode of adding the current sources, so that the power supply rejection ratio of the reference circuit and the buffer circuit is further improved. The output current sampling circuit feeds back the sampling load current to the bias current in the error amplifier, and the dynamic bias current distribution circuit is adopted to improve the gain and bandwidth of the error amplifier at the middle-high frequency working frequency. By introducing the buffer circuit with high power supply rejection ratio, the characteristics of high input impedance and low output impedance of the buffer circuit are utilized to isolate the reference circuit from the error amplifier circuit, so that the interference of power supply noise to the output of the reference circuit through a low-resistance channel formed by an error amplifier with a load current sampling feedback technology under the condition of medium and high frequency is effectively solved, the load current sampling technology is ensured to improve the gain of the medium and high frequency, the bandwidth is increased, the adverse effect of the medium and high frequency on the power supply rejection ratio of the LDO caused by the technology is eliminated, the power supply rejection ratio of the LDO loop at the medium and high frequency is further increased, the power supply rejection ratio of the medium and low frequency is not influenced by the dynamic current of the error amplifier, a higher level is still maintained, meanwhile, the capacitor Ch under the condition of the medium and high frequency is connected, the influence of the power supply noise from the internal channel of the error amplifier on the output end of the buffer circuit is greatly reduced, and the power supply rejection ratio of the LDO at the medium and high frequency is ensured.
As shown in fig. 2, the error amplifier includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor 12, a thirteenth transistor M13, and a parasitic capacitance C1; an input terminal of the eleventh transistor M11 is connected with a power supply, and a control terminal of the eleventh transistor M11 is connected with a bias voltage V b4 The output end of the eleventh transistor M11 is respectively connected with the input end of the first transistor M1 and the input end of the second transistor M2; the control end of the first transistor M1 is used as the inverting input end of the error amplifier to be connected with the output voltage V of the buffer circuit REF-buff The input end of the first transistor M1 is connected with the positive electrode end of the parasitic capacitor C1, the control end of the first transistor M1 is connected with the negative electrode end of the parasitic capacitor C1, and the second transistor M2 is used as the positive phase input end of the error amplifier; the input end of the third transistor M3 is connected with the input end of the fourth transistor M4, and the output end and the control end of the third transistor M3 are connected with the control end of the fourth transistor M4; an input terminal of the fifth transistor M5 is connected to the output terminal of the third transistor M3, a control terminal of the fifth transistor M5 is connected to the control terminal of the sixth transistor M6, and a common terminal of the two control terminals is connected to the first bias voltage V b1 An input end of the sixth transistor M6 is connected with an output end of the fourth transistor M4; an input terminal of the seventh transistor M7 is connected to the output terminal of the fifth transistor M5, and a control terminal of the seventh transistor M7 is connected to the control terminal of the eighth transistor M8 and is controlled by twoThe common terminal of the system terminal is connected with the second bias voltage V b2 An input end of the eighth transistor M8 is connected to an output end of the sixth transistor M6, wherein a common end of the eighth transistor M8 and the sixth transistor M6 is connected to a control end of the twelfth transistor M12; an input terminal of the ninth transistor M9 is connected to the output terminal of the seventh transistor M7, an input terminal of the ninth transistor M9 is connected to the output terminal of the first transistor M1, an output terminal of the ninth transistor M9 is connected to the ground terminal, a control terminal of the ninth transistor M9 is connected to the control terminal of the tenth transistor M10, and a common terminal of the two control terminals is connected to the third bias voltage V b3 An input end of the tenth transistor M10 is connected to an output end of the eighth transistor M8, and an input end of the tenth transistor M10 is connected to an output end of the second transistor M2 and a control end of the thirteenth transistor M13, and an output end of the tenth transistor M10 is connected to a ground end; an input end of the twelfth transistor M12 is connected to the power supply, an output end of the thirteenth transistor M13 is connected to the ground, and an output end of the twelfth transistor M12 is connected to the input end of the thirteenth transistor M13, wherein a common end of the twelfth transistor M12 and the thirteenth transistor M13 serves as an output end of the error amplifier.
Note that, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are PMOS transistors; the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 are NMOS transistors.
As can be seen from fig. 2, the input pair of the error amplifier is a PMOS tube, so that the error amplifier can still work normally when the input is at a lower voltage, and three bias voltages in the sleeve structure provide dc bias points for the op amp.
As shown in fig. 3, the buffer circuit includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; the input end of the seventeenth transistor M17 and the input end of the eighteenth transistor M18 are both connected with a power supply, the output end of the eighteenth transistor M18 is connected with the input end of the fourteenth transistor M14, and the control end of the eighteenth transistor M18 is connected withThe control end of the seventeenth transistor M17 is connected, the common end of the two control ends is connected with the input end of the fourteenth transistor M14, the output end of the seventeenth transistor M17 is connected with the input end of the fifteenth transistor M15, and the output end of the seventeenth transistor M17 and the input end of the fifteenth transistor M15 serve as output ends of the buffer circuit; the control terminal of the fourteenth transistor M14 is connected to the reference voltage source V as the non-inverting input terminal of the buffer circuit REF The output end of the fourteenth transistor M14 is connected to the output end of the fifteenth transistor M15, the common end of the two output ends is connected to the input end of the sixteenth transistor M16, and the fifteenth transistor M15 is connected to the positive end of the capacitor Ch as the output end of the buffer circuit; an output terminal of the sixteenth transistor M16 is connected to the ground terminal, and a control terminal of the sixteenth transistor M16 is connected to the fifth bias voltage V b5 。
Note that, the seventeenth transistor M17 and the eighteenth transistor M18 are PMOS transistors; the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are NMOS transistors.
As can be seen from fig. 3, the input pair of the buffer circuit is a PMOS transistor, so that the buffer circuit can still work normally when the input is at a lower voltage.
As shown in fig. 4, the output current sampling circuit includes a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21; an input end of the nineteenth transistor M19 is connected with a power supply, a control end of the nineteenth transistor M19 is used as an input end of an output current sampling circuit to be connected with an output end of an error amplifier and a control end of an adjusting tube MP, and an output end of the nineteenth transistor M19 is connected with an input end of a twenty-first transistor M21; the input end of the twentieth transistor M20 is used as the output end of the output current sampling circuit to be connected with the dynamic bias input end of the error amplifier, the control end of the twentieth transistor M20 is connected with the control end of the twenty-first transistor M21, and the common end of the two control ends is connected with the output end of the nineteenth transistor M19; the output terminal of the twentieth transistor M20 and the output terminal of the twenty-first transistor M21 are both connected to the ground terminal.
Note that, the nineteenth transistor M19 is a PMOS transistor, and the twentieth transistor M20 and the twenty first transistor M21 are NMOS transistors.
As shown in fig. 1, the resistor feedback circuit includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected with the output end of the adjusting tube MP, the other end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the grounding end and the negative end of the capacitor Ch, and the common end of the first resistor R1 and the second resistor R2 is used as the output end of the resistor feedback circuit to be connected with the non-inverting input end of the error amplifier.
The inventor simulates a traditional conventional LDO circuit with high power supply rejection ratio and the LDO circuit with high power supply rejection ratio, which can be applied to medium and high frequencies, through the spray simulation software, and checks the magnitude of an alternating current signal of an output point by adding an AC alternating current small signal to a power supply, the simulation software can be automatically converted into an alternating current signal with the unit of db, and a specific simulation result is shown in figure 5. The curve I is a power supply rejection ratio curve of a traditional conventional high power supply rejection ratio LDO circuit, and the curve II is a power supply rejection ratio curve of the high power supply rejection ratio LDO circuit applicable to medium and high frequencies.
Referring to FIG. 6, when the operating frequencies of the conventional high power rejection ratio LDO circuit and the high power rejection ratio LDO circuit applicable to medium and high frequencies are 10.1404KHz, the power rejection ratio (PSRR) of the conventional high power rejection ratio LDO circuit is-44.7663 dB, and the power rejection ratio (PSRR) applicable to medium and high frequencies is-65.745 dB. Compared with the conventional high power supply rejection ratio LDO circuit, the power supply rejection ratio of the LDO circuit is obviously improved, so that the performance of the LDO circuit at medium and high frequencies is improved, and the power supply rejection ratio of the LDO circuit at medium and high frequency ranges is improved.
Fig. 5 is a schematic diagram of a circuit structure in which a reference circuit and an error amplifier are directly connected in a conventional LDO circuit with a high power supply rejection ratio, and in the circuit structure of fig. 4, when the operating frequency is in a middle-high frequency band, a power supply noise path is formed from an output resistor r11 of M11 to an output resistor equivalent resistor Rj of the reference circuit through a parasitic capacitor C1 of M1, as shown by a dashed line with an arrow in the figure:
at medium-high frequency, the impedance R of C1 c Decreasing with increasing frequency:
the total resistance of the power supply noise path of the error amplifier is: re=r11+rc, it can be seen that Re also decreases with increasing frequency;
the power supply noise Vs at the reference output point under the influence of the error amplifier EA is:
in the direct current case, due to R C Is infinite, vs is approximately equal to zero, and R is due to the high resistance state of the reference circuit output as the frequency increases j Has very large resistance value, R C Decreasing Re, re ≪ R at medium and high frequencies j The value of Vs is caused to approach 1 more and more, that is, a significant portion of the power supply noise is conducted to the input of the error amplifier, destroying the power supply rejection ratio of the reference circuit, and causing the power supply rejection ratio of the LDO to become worse in the mid-high frequency band.
FIG. 2 is a schematic diagram of a circuit structure in which a reference circuit and an error amplifier are directly connected in a high power rejection ratio LDO circuit applicable to medium and high frequencies, wherein in the circuit structure of FIG. 2, when the operating frequency is in a medium and high frequency band, an output resistance equivalent resistor R from an output resistor R11 of M11 to a buffer circuit is formed in the error amplifier EA through a parasitic capacitor C1 of M1 h As indicated by the dashed lines with arrows in the figure:
at medium-high frequency, the impedance R of C1 c Decreasing with increasing frequency:
the total resistance of the power supply noise path of the error amplifier is: re=r11+rc, it can be seen that Re also decreases with increasing frequency;
the power supply noise Vs at the reference output point under the influence of the error amplifier EA is:
in the direct current case, vs in FIG. 4 and FIG. 2 are both 0 due to Rc being infinite, R in FIG. 4 at the same very high frequency j In a high resistance state, with R C Is smaller, in the limit case Vs in FIG. 4 is approximately equal to R j /R j =1. R is shown in FIG. 2 C Is smaller and Re is also decreased, in the limit due to R h Also small, and since the buffer circuit is typically constructed using a follower-connected transport amplifier, this connection results in an output resistance R of the buffer circuit according to the negative feedback theory h Is very small, so that Re ≫ R h Vs in FIG. 2 is approximately equal to R h Because Vs is still a value much smaller than 1, vs in fig. 2 does not change significantly compared with Vs in fig. 4, but the output point of the reference circuit still has a higher power supply rejection ratio under the middle-high frequency condition under the protection of the buffer circuit with a high voltage rejection ratio, so that the power supply rejection ratio of the LDO can still perform well in the middle-high frequency band.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the technical scope of the present invention, so that any minor modifications, equivalent changes and modifications made to the above embodiments according to the technical principles of the present invention still fall within the scope of the technical solutions of the present invention.
Claims (8)
1. The high power supply rejection ratio LDO circuit is characterized by comprising a power supply, a current source, a reference circuit, a buffer circuit, an error amplifier with dynamic current bias, an output current sampling circuit, an adjusting tube MP and a resistor feedback circuit; the input end of the current source is connected with the power supply, and the currentThe output end of the source is connected with the power input end of the buffer circuit and the power input end of the reference circuit; the output end of the reference circuit is connected with the non-inverting input end of the buffer circuit, the inverting input of the buffer circuit is connected with the output end of the buffer circuit, the output end of the buffer circuit is connected with the positive electrode end of the capacitor Ch and the inverting input end of the error amplifier, and the negative electrode end of the capacitor Ch is connected with the grounding end; the output end of the error amplifier is connected with the control end of the adjusting tube MP and the input end of the output current sampling circuit, the output end of the output current sampling circuit is connected with the dynamic bias input end of the error amplifier, and the output end of the adjusting tube MP is connected with the non-inverting input end of the error amplifier through the resistance feedback circuit; the input end of the adjusting tube MP is connected with the power supply, and the common end of the adjusting tube MP and the feedback circuit is used as the output end of the low-dropout linear voltage regulator circuit; the error amplifier outputs a feedback voltage V from the feedback circuit FB With the output voltage V of the buffer circuit REF-buff The comparison produces an error signal which is amplified and thus regulated by the regulator tube MP.
2. The LDO circuit of claim 1, wherein the error amplifier comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor 12, a thirteenth transistor M13, and a parasitic capacitance C1; an input terminal of the eleventh transistor M11 is connected with the power supply, and a control terminal of the eleventh transistor M11 is connected with the bias voltage V b4 An output terminal of the eleventh transistor M11 is connected to the input terminal of the first transistor M1 and the input terminal of the second transistor M2, respectively; the control end of the first transistor M1 is used as the inverting input end of the error amplifier to be connected with the output end of the buffer circuitOutput voltage V REF-buff The input end of the first transistor M1 is connected to the positive end of the parasitic capacitor C1, the control end of the first transistor M1 is connected to the negative end of the parasitic capacitor C1, and the second transistor M2 is used as the non-inverting input end of the error amplifier; the input end of the third transistor M3 is connected with the input end of the fourth transistor M4, and the output end and the control end of the third transistor M3 are connected with the control end of the fourth transistor M4; an input terminal of the fifth transistor M5 is connected to an output terminal of the third transistor M3, a control terminal of the fifth transistor M5 is connected to a control terminal of the sixth transistor M6, and a common terminal of the two control terminals is connected to a first bias voltage V b1 An input end of the sixth transistor M6 is connected to an output end of the fourth transistor M4; an input terminal of the seventh transistor M7 is connected to the output terminal of the fifth transistor M5, a control terminal of the seventh transistor M7 is connected to the control terminal of the eighth transistor M8, and a common terminal of the two control terminals is connected to the second bias voltage V b2 An input terminal of the eighth transistor M8 is connected to an output terminal of the sixth transistor M6, wherein a common terminal of the eighth transistor M8 and the sixth transistor M6 is connected to a control terminal of the twelfth transistor M12; an input terminal of the ninth transistor M9 is connected with the output terminal of the seventh transistor M7, an input terminal of the ninth transistor M9 is connected with the output terminal of the first transistor M1, an output terminal of the ninth transistor M9 is connected with a ground terminal, a control terminal of the ninth transistor M9 is connected with a control terminal of the tenth transistor M10, and a common terminal of the two control terminals is connected with a third bias voltage V b3 An input end of the tenth transistor M10 is connected to an output end of the eighth transistor M8, an input end of the tenth transistor M10 is connected to an output end of the second transistor M2 and a control end of the thirteenth transistor M13, and an output end of the tenth transistor M10 is connected to a ground end; an input terminal of the twelfth transistor M12 is connected with the power supply, an output terminal of the thirteenth transistor M13 is connected with the ground terminal, and an output terminal of the twelfth transistor M12 is connected with the input terminal of the thirteenth transistor M13, wherein the twelfth transistor M12 and the thirteenth transistor M13 as an output of the error amplifier.
3. The LDO circuit according to claim 2, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 are PMOS transistors; the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 are NMOS transistors.
4. The LDO circuit of claim 1, wherein the buffer circuit comprises a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; the input end of the seventeenth transistor M17 and the input end of the eighteenth transistor M18 are both connected to the power supply, the output end of the eighteenth transistor M18 is connected to the input end of the fourteenth transistor M14, the control end of the eighteenth transistor M18 is connected to the control end of the seventeenth transistor M17, the common end of the two control ends is connected to the input end of the fourteenth transistor M14, the output end of the seventeenth transistor M17 is connected to the input end of the fifteenth transistor M15, and the output end of the seventeenth transistor M17 and the input end of the fifteenth transistor M15 are used as the output ends of the buffer circuit; the control end of the fourteenth transistor M14 is used as the non-inverting input end of the buffer circuit to be connected with a reference voltage source V REF An output terminal of the fourteenth transistor M14 is connected to an output terminal of the fifteenth transistor M15, a common terminal of the two output terminals is connected to an input terminal of the sixteenth transistor M16, and the fifteenth transistor M15 is connected to an anode terminal of the capacitor Ch as an output terminal of the buffer circuit; an output terminal of the sixteenth transistor M16 is connected to the ground terminal, and a control terminal of the sixteenth transistor M16 is connected to the fifth biasVoltage V b5 。
5. The LDO circuit of claim 4, wherein the seventeenth transistor M17 and the eighteenth transistor M18 are PMOS transistors; the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are NMOS transistors.
6. The LDO circuit of claim 1, wherein the output current sampling circuit comprises a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21; an input end of the nineteenth transistor M19 is connected to the power supply, a control end of the nineteenth transistor M19 is used as an input end of the output current sampling circuit and is connected to an output end of the error amplifier and a control end of the adjusting transistor MP, and an output end of the nineteenth transistor M19 is connected to an input end of the twenty first transistor M21; an input end of the twentieth transistor M20 is used as an output end of the output current sampling circuit and is connected with a dynamic bias input end of the error amplifier, a control end of the twentieth transistor M20 is connected with a control end of the twenty-first transistor M21, and a common end of the two control ends is connected with an output end of the nineteenth transistor M19; the output terminal of the twentieth transistor M20 and the output terminal of the twenty-first transistor M21 are both connected to the ground terminal.
7. The LDO circuit of claim 6, wherein the nineteenth transistor M19 is a PMOS transistor, and the twentieth transistor M20 and the twenty-first transistor M21 are NMOS transistors.
8. The high power rejection ratio LDO circuit applicable to medium and high frequencies according to claim 1, wherein the resistive feedback circuit comprises a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to the output end of the regulator MP, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the ground end and the negative end of the capacitor Ch, and the common end of the first resistor R1 and the second resistor R2 is used as the output end of the resistor feedback circuit to be connected to the non-inverting input end of the error amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310409345.1A CN116149419B (en) | 2023-04-18 | 2023-04-18 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310409345.1A CN116149419B (en) | 2023-04-18 | 2023-04-18 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116149419A true CN116149419A (en) | 2023-05-23 |
| CN116149419B CN116149419B (en) | 2023-07-04 |
Family
ID=86362130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310409345.1A Active CN116149419B (en) | 2023-04-18 | 2023-04-18 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116149419B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202257346U (en) * | 2011-09-30 | 2012-05-30 | 电子科技大学 | Low dropout regulator integrated with slew rate enhancing circuit |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| US9746864B1 (en) * | 2016-08-11 | 2017-08-29 | Xilinx, Inc. | Fast transient low drop-out voltage regulator for a voltage-mode driver |
| CN107102665A (en) * | 2016-02-22 | 2017-08-29 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator |
| CN108021169A (en) * | 2016-11-02 | 2018-05-11 | 中国科学院沈阳自动化研究所 | A kind of LDO circuit |
| KR20200012434A (en) * | 2018-07-27 | 2020-02-05 | 주식회사 실리콘마이터스 | Buffer circuit, amplifier and regulator with high stability and fast response |
| CN113064460A (en) * | 2021-03-24 | 2021-07-02 | 成都瓴科微电子有限责任公司 | Low dropout regulator circuit with high power supply rejection ratio |
| CN114924606A (en) * | 2022-06-02 | 2022-08-19 | 泉芯电子技术(深圳)有限公司 | LDO circuit with low power consumption and high power supply rejection ratio |
| CN115542988A (en) * | 2022-09-19 | 2022-12-30 | 泉芯电子技术(深圳)有限公司 | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm |
-
2023
- 2023-04-18 CN CN202310409345.1A patent/CN116149419B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202257346U (en) * | 2011-09-30 | 2012-05-30 | 电子科技大学 | Low dropout regulator integrated with slew rate enhancing circuit |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| CN107102665A (en) * | 2016-02-22 | 2017-08-29 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator |
| US9746864B1 (en) * | 2016-08-11 | 2017-08-29 | Xilinx, Inc. | Fast transient low drop-out voltage regulator for a voltage-mode driver |
| CN108021169A (en) * | 2016-11-02 | 2018-05-11 | 中国科学院沈阳自动化研究所 | A kind of LDO circuit |
| KR20200012434A (en) * | 2018-07-27 | 2020-02-05 | 주식회사 실리콘마이터스 | Buffer circuit, amplifier and regulator with high stability and fast response |
| CN113064460A (en) * | 2021-03-24 | 2021-07-02 | 成都瓴科微电子有限责任公司 | Low dropout regulator circuit with high power supply rejection ratio |
| CN114924606A (en) * | 2022-06-02 | 2022-08-19 | 泉芯电子技术(深圳)有限公司 | LDO circuit with low power consumption and high power supply rejection ratio |
| CN115542988A (en) * | 2022-09-19 | 2022-12-30 | 泉芯电子技术(深圳)有限公司 | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116149419B (en) | 2023-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108235744B (en) | Low dropout linear voltage stabilizing circuit | |
| KR101238173B1 (en) | A Low Dropout Regulator with High Slew Rate Current and High Unity-Gain Bandwidth | |
| CN104679088A (en) | Low dropout linear regulator and frequency compensating circuit thereof | |
| CN213069627U (en) | Low quiescent current LDO circuit based on buffer impedance attenuation | |
| CN111190453A (en) | High power supply rejection ratio reference circuit | |
| CN113467559B (en) | Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator) | |
| CN115328254B (en) | High transient response LDO circuit based on multiple frequency compensation modes | |
| CN104298291A (en) | Low dropout voltage regulator | |
| CN114546025B (en) | LDO circuit and chip with low static power consumption and rapid transient response | |
| CN113760031B (en) | Low quiescent current NMOS type full-integrated LDO circuit | |
| CN117155123B (en) | Transient jump overshoot suppression circuit suitable for LDO and control method thereof | |
| CN110928350A (en) | Power supply with wide input voltage | |
| CN111522390A (en) | Method for effectively improving transient response speed | |
| CN114756083A (en) | Low-dropout linear voltage stabilizing circuit and electronic equipment | |
| CN113778158A (en) | Area compact's self-adaptation biasing NMOS type LDO circuit | |
| CN112732000A (en) | Novel transient response enhanced LDO | |
| CN116560446A (en) | Full-integrated LDO circuit for high-current application and working method thereof | |
| CN116149419B (en) | High power supply rejection ratio LDO circuit applicable to medium and high frequencies | |
| CN110879629A (en) | Low dropout linear voltage stabilizing circuit | |
| CN115542988A (en) | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm | |
| CN116027838A (en) | Low dropout linear voltage regulator, voltage stabilizing system and dynamic compensation method of pole of voltage stabilizing system | |
| CN211827060U (en) | Buffer and voltage stabilizer | |
| CN115857604B (en) | Self-adaptive current jump circuit suitable for low dropout linear voltage regulator | |
| Liu et al. | A High PSR and Fast Transient Response Output-Capacitorless LDO using Gm-Boosting and Capacitive Bulk-Driven Feed-Forward Technique in 22nm CMOS | |
| CN115167603B (en) | Loop high-stability LDO circuit and method based on dynamic zero point following compensation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |