CN115542988A - Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm - Google Patents
Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm Download PDFInfo
- Publication number
- CN115542988A CN115542988A CN202211137078.9A CN202211137078A CN115542988A CN 115542988 A CN115542988 A CN 115542988A CN 202211137078 A CN202211137078 A CN 202211137078A CN 115542988 A CN115542988 A CN 115542988A
- Authority
- CN
- China
- Prior art keywords
- transistor
- error amplifier
- circuit
- power supply
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention relates to a low-power consumption high-power supply rejection ratio LDO circuit with a sampling load current technology and an algorithm. An output current dynamic sampling circuit in the circuit is connected with a dynamic bias input end of an error amplifier; inverting input of error amplifier and reference voltage source V REF The output end of the error amplifier is connected with the control ends of the adjusting tube and the sampling tube, and the adjusting tube is connected with the positive phase input end of the error amplifier through a resistance feedback circuit; the input end of the adjusting tube is connected with a power supply, and the common end of the adjusting tube and the resistance feedback circuit is used as the output end of the low dropout linear regulator circuit; the error amplifier outputs a feedback voltage V to the resistor feedback circuit FB And a reference voltage V REF Comparing to generate an error signal, and adjusting an adjusting tube by amplifying the error signal; the gain of the medium-high frequency error amplifier is improved and the bandwidth of the error amplifier is also increased by feeding back the sampling load current to the bias current distribution circuit of the error amplifier.
Description
Technical Field
The invention belongs to the technical field of voltage regulators, and particularly relates to a low-power consumption high-power supply rejection ratio LDO circuit with a load current sampling technology and an algorithm.
Background
The low dropout regulator has the advantages of low output noise, simple circuit structure, small occupied chip area, small voltage ripple and the like, and becomes an important circuit in a power management chip. Especially in mobile devices, the ultralow static power consumption of the low dropout linear regulator is more advantageous. The ultra-low static power consumption can prolong the service life and the service life of the battery. Therefore, the low power consumption design becomes a key index in the low dropout linear regulator design. However, the low quiescent current affects other parameters of the low dropout regulator, such as: load transient response, power Supply Rejection Ratio (PSRR), output noise, etc.
Among them, low static power consumption and Power Supply Rejection Ratio (PSRR) are key performance indicators of the linear regulator. And the power supply rejection ratio tends to depend on the accuracy of the bandgap reference and the open loop gain of the linear regulator error amplifier loop. Generally, in order to obtain a high power supply rejection ratio, a linear regulator uses a large open-loop gain of an error amplifier, or increases a coupling capacitance at an output terminal. The use of a larger open-loop gain of the error amplifier, such as a multi-stage operational amplifier, not only increases the power consumption and area of the chip, but also brings a larger challenge to the circuit design. The way of increasing the output end coupling capacitance increases the area of the chip and increases the production cost, and at the same time, such a way will cause the bandwidth of the linear voltage regulator to decrease, so that a higher power supply rejection ratio cannot be obtained in the middle and high frequency bands.
With the increasing requirement of users on the power supply ripple rejection capability, the linear voltage regulator with low power consumption and high power supply rejection ratio still has a good power supply rejection ratio of 60dB at 100 kHz. This is also a challenge for low power circuit design, because if the quiescent current of the circuit is low, the bandwidth of the whole system will be reduced, and thus the power supply rejection ratio of the high frequency band will be limited.
Under the requirements of low power consumption and low cost, the LDO power supply rejection ratio curve chart adopting the conventional error amplifier is shown as a curve I in figure 3, the LDO power supply rejection ratio curve chart is reduced at a rate of 20dB/10dec at a lower frequency point, and the LDO power supply rejection ratio of the LDO circuit under the constraint of the open loop gain and the bandwidth which are contradictory points is not ideal in high-frequency section.
According to the related theory, the bandwidth of the error amplifier is proportional to the gm value of the input pair transistor, and gm increases with the increase of the current flowing through the input pair transistor, a dynamic bias current can be injected into the error amplifier by using a load current sampling feedback technology without increasing static power consumption, and gm of the input pair transistor can be dynamically increased under the condition of the load of the LDO, but the current design mode is to directly inject the sampled bias current into the bias circuit of the error amplifier, and such a dynamic current injection mode increases the bias current of the input pair transistor, thereby partially increasing gm of the differential input pair transistor, widening the bandwidth of the error amplifier, but also increasing the bias current flowing through the load circuit, and correspondingly and obviously reducing the output resistance of the error amplifier, according to the gain formula Av = gm Rout of the error amplifier, the gain of the error amplifier is correspondingly reduced, thereby causing the power supply rejection ratio to decrease when the LDO is in low frequency, as shown in curve two of fig. 3, as compared with the curve of fig. 3, it can be found: although the power supply rejection ratio in a high frequency band is improved due to the increase of the bandwidth, the power supply rejection ratio in a medium and low frequency band is also obviously reduced due to the reduction of the direct current gain, and the improvement effect of the design mode on the power supply rejection ratio is not outstanding.
Disclosure of Invention
In order to solve the low power consumption and high power supply rejection ratio indexes of the low dropout linear regulator, the invention aims to provide a bias circuit which is fed back to an error amplifier through sampling load current, and a novel bias current distribution circuit is adopted, so that the gain of a medium-high frequency error amplifier is improved, and meanwhile, the bandwidth of the error amplifier is increased. Another objective of the present invention is to provide a low power consumption and high power supply rejection ratio LDO circuit and algorithm with sampled load current technology, which feed back the sampled current to the error amplifier by sampling the output current, and increase the bandwidth of the error amplifier by overlapping the fixed bias current of the error amplifier with a novel bias current distribution circuit, improve the gain of the high frequency band of the error amplifier, and keep the low cost while realizing the power supply rejection ratio of the high frequency band. The invention further aims to provide a low-power consumption high-power-rejection-ratio LDO circuit and an algorithm of a low-dropout linear regulator with a sampling load current technology, which are used for carrying out high-efficiency dynamic bias on an error amplifier by sampling output current, improving the power supply rejection ratio of a high frequency band, keeping ultralow power consumption under the condition of no load and realizing ultralow static power consumption and high power supply rejection ratio.
The technical scheme of the invention is that the LDO circuit with low power consumption and high power supply rejection ratio and the sampling load current technology is characterized by comprising the following components: the dynamic current bias error amplifier, the adjusting tube MP, the resistance feedback circuit, the reference circuit and the output current dynamic sampling circuit are driven: the output current dynamic sampling circuit is connected with the dynamic bias input end of the error amplifier; the inverting input of the error amplifier is connected with a reference voltage source VREF, the output end of the error amplifier is connected with the control ends of the adjusting tube MP and the sampling tube MS, and the adjusting tube MP is connected with the non-inverting input end of the error amplifier through the resistance feedback circuit; the input end of the adjusting tube is connected with a power supply, and the common end of the adjusting tube MP and the resistance feedback circuit is used as the output end of the low dropout linear regulator circuit; the error amplifier feeds back the feedback voltage V output by the resistance feedback circuit FB And a reference voltage V REF Comparing to generate an error signal, and adjusting the adjusting tube MP by amplifying the error signal; by sampling the bias current fed back to the error amplifier by the load current and adopting the bias current distribution circuit, the gain of the medium-high frequency error amplifier is improved, and meanwhile, the bandwidth of the error amplifier is also increased.
Preferably, the method comprises the following steps: the output current dynamic sampling circuit comprises a first transistor M 1 A second transistor M 2 Eighteenth body tube M S (ii) a The eighteenth body tube M S Is connected to a power supply, the eighteenth transistor M S Is connected to the first transistor M 1 Output terminal and first transistor M 1 And a second transistor M 2 The control terminal of the second transistor M, the second transistor M 2 The output end is connected with the dynamic bias input end of the error amplifier, and the first transistor M 1 And a second transistor M 2 The input terminal of the switch is connected with the ground terminal.
Preferably, the method comprises the following steps: the error amplifier includes: thirdTransistor M 3 A fourth transistor M 4 The fifth transistor M 5 And a sixth transistor M 6 The seventh transistor M 7 An eighth transistor M 8 The ninth transistor M 9 The tenth transistor M 10 Eleventh transistor M 11 And a twelfth transistor M 12 Thirteenth transistor M 13 And a fourteenth transistor M 14 Fifteenth transistor M 15 Sixteenth transistor M 16 And a seventeenth transistor M 17 (ii) a The fifth transistor M 5 Is connected to the power supply, the fifth transistor M 5 Is connected with a fourth bias voltage V b4 Said fifth transistor M 5 Are respectively connected with the sixth transistor M 6 And said seventh transistor M 7 An input terminal of (1); the sixth transistor M 6 As the non-inverting input terminal of the error amplifier, a seventh transistor M 7 The control end of the error amplifier is used as the inverting input end of the error amplifier and is connected with the reference voltage source VREF; the sixteenth transistor M 16 And the seventeenth transistor M 17 The input ends of the first and second transistors are connected with the power supply, and the sixteenth transistor M is connected with the power supply 16 And a control terminal and the seventeenth transistor M 17 The control end of the controller is connected; the fourteenth transistor M 14 Is connected to the sixteenth transistor M 16 The fourteenth transistor M 14 And the fifteenth transistor M 15 And a common terminal of the two control terminals is connected with a first bias voltage V b1 The fifteenth transistor M 15 Is connected to the seventeenth transistor M 17 An output terminal of (a); the twelfth transistor M 12 Is connected to the fourteenth transistor M 14 The twelfth transistor M 12 Is connected with the thirteenth transistor M 13 And a common terminal of the two control terminals is connected with a second bias voltage V b2 The thirteenth transistor M 13 Is connected to the fifteenth input terminalTransistor M 15 Wherein the thirteenth transistor M 13 And the fifteenth transistor M 15 As an output terminal of the error amplifier; the tenth transistor M 10 Is connected to the twelfth transistor M 12 And the tenth transistor M, and 10 is connected to the sixth transistor M 6 The tenth transistor M 10 Is connected to the ground terminal, the tenth transistor M 10 Is connected with the eleventh transistor M 11 And a common terminal of the two control terminals is connected with a third bias voltage V b3 The eleventh transistor M 11 Is connected to the thirteenth transistor M 13 And the thirteenth transistor M 13 Is connected to the seventh transistor M 7 The thirteenth transistor M 13 The output end of the switch is connected with a grounding end; the third transistor M 3 And said fourth transistor M 4 Is connected to the power supply, the third transistor M 3 Is connected to the second transistor M 2 An output terminal, the third transistor M 3 Is connected to the fourth transistor M 4 And a common terminal of the two control terminals is connected with the second transistor M 2 An output terminal, the fourth transistor M 4 Are connected with the sixth transistor M respectively 6 And said seventh transistor M 7 An input terminal of (1); the eighth transistor M 8 And said ninth transistor M 9 Are all connected to the ground terminal, the eighth transistor M 8 A control terminal is connected with the ninth transistor M 9 A control terminal and a common terminal of the two control terminals are connected with the eighteenth transistor M S An output terminal of the eighth transistor M 8 Is connected to the twelfth transistor M 12 The ninth transistor M, the ninth transistor M 9 Is connected to the thirteenth transistor M 13 To the output terminal of (a).
Preferably, the method comprises the following steps: the first mentionedThree transistors M 3 The fourth transistor M 4 The fifth transistor M 5 The sixth transistor M 6 The seventh transistor M 7 The twelfth transistor M 12 The thirteenth transistor M 13 The fourteenth transistor M 14 The fifteenth transistor M 15 The sixteenth transistor M 16 And the thirteenth transistor M 13 Is a PMOS tube; the eighth transistor M 8 The ninth transistor M 9 The tenth transistor M 10 And the eleventh transistor M 11 Is an NMOS tube.
Preferably, the method comprises the following steps: the resistance feedback circuit includes: a first resistor R 1 And a second resistor R 2 (ii) a The first resistor R 1 One end of the first resistor R is connected with the output end of the adjusting tube MP 1 Through said second resistor R 2 Connected to ground, the first resistor R 1 And said second resistance R 2 The output end of the common end serving as a feedback resistor is connected with the non-inverting input end of the error amplifier.
Another technical solution of the present invention is an algorithm with low power consumption and high power supply rejection ratio of the sampled load current technique, which is characterized by comprising:
increasing the loop gain of the LDO to improve the power supply noise rejection characteristics of the LDO:
in the formula, A EA Is the gain of the error amplifier, beta is the feedback coefficient of the feedback circuit, A POW For gain of the power stage, PSR EA And PSR POW The power supply rejection ratios of the error amplifier and the power stage are respectively independent, and the formula shows that the gain of the error amplifier is increased, so that the power supply noise rejection characteristic of the LDO can be improved;
to improve the power noise suppression characteristics of the LDO at medium and high frequencies, the gain of the error amplifier at medium and high frequency bands is increased, and for the error amplifier:
A EA ＝g m *R out (2)
R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5)
in the formula, g m Representing the transconductance, r, of the input tube of the error amplifier m15 、r m17 、r m13 、r m7 、r m11 Respectively, a fifteenth transistor M in the error amplifier sleeve structure 10 Seventeenth transistor M 17 Thirteenth transistor M 13 The seventh transistor M 7 Eleventh transistor M 11 Output resistance of g m15 、g m13 Are thirteenth transistors M respectively 13 And a fifteenth transistor M 15 Transconductance of (3), R out Representing the output resistance of the error amplifier, GBW EA Is the gain-bandwidth product of the error amplifier, C POW Load capacitance of the output stage of the error amplifier, I D Is the drain-source current flowing through the input tube;
from the above formula: bandwidth of error amplifier and g of input pair tube m The value is proportional, and g m With current I flowing through the input pair D Increasing the current by a fixed bias current distribution ratio designed according to the original error amplifierThe differential input pair tubes and the sleeve structure are respectively distributed:
case where no dynamic bias current is injected:
case of injecting dynamic bias current:
with following
Injection of bias current I through differential input pair D Increases in (2) increase gm of the differential input pair transistors, and correspondingly broaden the bandwidth of the error amplifier, but with I' 2 The injection of (A) also correspondingly and obviously reduces the output resistance r of each transistor in the sleeve structure o The output resistance R of the error amplifier is correspondingly reduced OUT According to the formula (2), the gain of the error amplifier is correspondingly reduced, thereby causing the power supply rejection ratio of the LDO to be reduced at low frequencies.
Preferably, the method comprises the following steps: to further increase the power supply rejection ratio of LDO, M 4 Providing dynamic bias current I for amplifier input pair B1 ，M 7 And M 8 Providing a dynamic bias current I for a cascode circuit B2 And I B3 Wherein the dynamic bias current:
case of no injected dynamic bias current:
case of injecting dynamic bias current:
design of
Then I' 2 ＝0
Due to l' 1 And l' 2 Is zero, flows through the twelfth transistor M 12 Thirteenth transistor M 13 Fourteenth transistor M 14 Fifteenth transistor M 15 Sixteenth transistor M 16 Seventeenth transistor M 17 The current of (d) is the same as the current without dynamic bias, g is determined according to the equations (4) and (6) m15 、g m13 、r m15 、r m17 、r m13 The values of the input current and the output resistance of the error amplifier are the same as those before the dynamic bias current is not injected, the output resistance of the error amplifier cannot be obviously reduced due to the addition of the dynamic bias current according to a formula (5), the injected dynamic bias current is completely injected into the differential input pair transistor, the gm of the input pair transistor is obviously improved, according to a formula (2) and a formula (3), the injection mode improves the open-loop gain and widens the bandwidth of the error amplifier, and the gain A of the error amplifier is also increased EA According to the formula (1), the power supply rejection ratio of the LDO is obviously improved
Compared with the prior art, the invention has the beneficial effects that:
(1) The invention utilizes the load current sampling feedback technology, and the bias current of partial key modules of the error amplifier is increased in a targeted manner through a novel dynamic bias circuit modulation module, so that the transconductance Gm of the error amplifier is obviously improved, meanwhile, the resistance value change of the output resistance of the error amplifier is slowed down, the gain of medium and high frequencies is improved, and further, the loop bandwidth is increased, the power supply rejection ratio of the LDO loop at high frequencies is still larger, and the power supply rejection ratio of the medium and low frequencies is not influenced by newly added dynamic current and still keeps a higher level. From the above, it can be seen that: the LDO circuit with low power consumption and high power supply rejection ratio realizes the high power supply rejection ratio of a high frequency band while keeping low cost.
(2) The invention carries out high-efficiency dynamic current bias on the error amplifier by sampling the output current, maintains the high-gain characteristic of the error amplifier and widens the bandwidth of the error amplifier, thereby improving the power supply rejection ratio of the LDO high frequency band and simultaneously keeping the ultra-low power consumption under the no-load condition.
(3) The invention samples the output current, feeds the sampled current back to the error amplifier, and adopts the novel bias current distribution circuit to be superposed with the fixed bias current of the error amplifier, thereby increasing the bandwidth of the error amplifier and improving the power supply rejection ratio of the high frequency band of the error amplifier.
(4) The LDO power supply rejection ratio using the sampling circuit and the dynamic bias adjusting error amplifier of the present invention is shown by the dashed line in curve two of fig. 4. Comparing with curve one of fig. 4 (LDO power supply rejection ratio plot with error amplifier without dynamic bias adjustment), it can be found that: the power supply rejection ratio of the medium and high frequency bands is greatly improved, and the power supply rejection ratio of the medium and low frequency bands also keeps a higher level.
Drawings
FIG. 1 is a block diagram of a low dropout linear regulator with low power consumption and high power supply rejection ratio according to the present invention;
FIG. 2 is a block diagram of the present invention with a dynamic sampling current bias circuit error amplifier;
FIG. 3 is a graph comparing power supply rejection ratio of LDOs incorporating conventional dynamic bias error amplifiers and with conventional error amplifiers;
FIG. 4 is a comparison of the power supply rejection ratio of the LDO with the conventional error amplifier with the novel dynamic bias error amplifier.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings:
referring to fig. 1, the low dropout regulator circuit of the present invention includes: the device comprises a reference circuit, an error amplifier with an on-state current bias, an adjusting tube MP, an output current sampling circuit and a feedback circuit. Wherein:
the inverting input end of the error amplifier is connected with a reference voltage source VREF, the output end of the error amplifier is connected with the control end of the adjusting tube MP, the output end of the adjusting tube MP is connected with the non-inverting input end of the error amplifier through a feedback circuit, the input end of the output current sampling circuit is connected with the output end of the error amplifier, and the output end of the output current sampling circuit is connected with the dynamic current input end of the error amplifier;
the error amplifier is used for comparing the feedback voltage with the reference voltage Vref to generate an error signal, and the adjustment tube Mp is adjusted by amplifying the error signal to finally stabilize the output voltage of the whole circuit, so that the performance of the error amplifier directly influences various performance parameters of the whole circuit, such as power supply rejection ratio, load adjustment rate, linear adjustment rate and the like. In order to achieve a high power supply rejection ratio in a wide frequency band, the error amplifier is generally required to have a high gain in the wide frequency band, and therefore, the error amplifier generally adopts a folded cascode amplifier or a two-stage operational amplifier structure. Because two poles can be generated by the two-stage operational amplifier, a zero needs to be generated by additionally designing a compensation circuit to offset one pole, which undoubtedly increases the design difficulty of the whole circuit compensation network, while the folding cascode amplifier is a single-stage operational amplifier which can reduce the compensation difficulty, and can also provide larger gain and larger loop bandwidth. Therefore, the present invention employs a folded cascode based driver state current offset error amplifier.
Referring to fig. 2, a band-state current offset error amplifier according to an embodiment of the present invention includes: third switch tube M 3 The fourth switch tube M 4 The fifth switch tube M 5 The sixth switching tube M 6 Seventh switch tube M 7 The eighth switching tube M 8 The ninth switch tube M 9 The tenth switch tube M 10 Eleventh switching tube M 11 And the twelfth switching tube M 12 Thirteenth switch tube M 13 Fourteenth switch tube M 14 Fifteenth switch tube M 15 Sixteenth switching tube M 16 And seventeenth switching tube M 17 ；
Wherein: the fifth transistor M 5 Is connected to the supply voltage VDD, the fifth transistor M 5 Is connected with a fourth bias voltage M 4 Said fifth transistor M 5 Are respectively connected with the sixth transistor M 6 And said seventh transistor M 7 An input terminal of (1);
the sixth transistor M 6 As the non-inverting input terminal of the error amplifier, is connected to the feedback circuit (feedback power supply V) FB ) Said, seventh transistor M 7 Is used as the inverting input end of the error amplifier and is connected with the reference voltage source V REF ；
The sixteenth transistor M 16 And the seventeenth transistor M 17 Are all connected with the power supply V DD The sixteenth transistor M 16 And a control terminal and the seventeenth transistor M 17 The control end of the controller is connected;
the fourteenth transistor M 14 Is connected to the sixteenth transistor M 16 The fourteenth transistor M 14 And the fifteenth transistor M 15 And a common terminal of the two control terminals is connected with a first bias voltage, the fifteenth transistor M 15 Is connected to the seventeenth transistor M 17 An output terminal of (a);
the twelfth transistor M 12 Is connected to the fourteenth transistor M 14 The twelfth transistor M 12 Is connected with the thirteenth transistor M 13 And a common terminal of the two control terminals is connected with a second bias voltage, the thirteenth transistor M 13 Is connected to the fifteenth transistor M 15 Wherein the thirteenth transistor M 13 And the fifteenth transistor M 15 As an output terminal of the error amplifier;
the tenth transistor M 10 Is connected to the twelfth transistor M 12 And the tenth transistor M, and 10 is connected to the sixth transistor M 6 The tenth transistor M 10 Is connected to the ground terminal GND, the tenth transistor M 10 Is connected with the eleventh transistor M 11 And a common terminal of the two control terminals is connected with a third bias voltage, the eleventh transistor M 11 Is connected to the thirteenth transistor M 13 And the thirteenth transistor M 13 Is connected to the seventh transistor M 7 The thirteenth transistor M 13 The output end of the switch is connected with a ground end GND;
the third transistor M 3 And said fourth transistor M 4 Are all connected with the power supply V DD The third transistor M 3 Is connected to the second transistor M 2 An output terminal of the third transistor M 3 Is connected to the fourth transistor M 4 And a common terminal of the two control terminals is connected with the second transistor M 2 An output terminal of the fourth transistor M 4 Are connected with the sixth transistor M respectively 6 And said seventh transistor M 7 An input terminal of (1);
the eighth transistor M 8 And said ninth transistor M 9 Are all connected to the ground terminal, the eighth transistor M 8 A control terminal is connected with the ninth transistor M 9 A control terminal and a common terminal of the two control terminals are connected with the eighteenth transistor M S An output terminal of the eighth transistor M 8 Is connected to the twelfth transistor M 12 The ninth transistor M, the ninth transistor M 9 Is connected to the thirteenth transistor M 13 An output terminal of (a);
in the error amplifier, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the thirteenth transistor are PMOS transistors;
the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are NMOS transistors.
It can be seen from the figure that the input pair transistor of the error amplifier is a PMOS transistor, so that the error amplifier can still work normally when a lower voltage is input, and three bias voltages in the sleeve structure provide direct current bias points for the operational amplifier.
For further explaining that the low dropout regulator circuit provided by the invention can obviously improve the power supply rejection ratio, the following analysis and calculation are carried out on the error amplifier with dynamic current bias, and according to the relevant theory, the increase of the loop gain of the LDO is beneficial to improving the power supply noise rejection characteristic of the LDO:
wherein A is EA Is the gain of the error amplifier, beta is the feedback coefficient of the feedback circuit, A pow For gain of the power stage, PSR EA And PSR pow The power supply rejection ratios of the error amplifier and the power stage which exist independently respectively can be seen from the formula, the gain of the error amplifier is increased, and the power supply noise rejection characteristic of the LDO can be improved.
From this, it can be seen that, in order to improve the power supply noise suppression characteristics of the LDO at medium and high frequencies, the gain of the error amplifier at medium and high frequency bands can be increased, and for the error amplifier:
A EA ＝g m *R out (2)
R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5)
in the formula, g m Representing the transconductance, r, of the input tube of the error amplifier m15 、r m17 、r m13 、r m7 、r m11 The output resistances g of the fifteenth transistor, the seventeenth transistor, the thirteenth transistor, the seventh transistor and the eleventh transistor in the sleeve structure of the error amplifier m15 、g m13 Transconductances, R, of a thirteenth transistor and a fifteenth transistor, respectively out Representing the output resistance, GBW, of the error amplifier EA Is the gain-bandwidth product, C, of the error amplifier pow Is the load capacitance of the output stage of the error amplifier, I D Is the drain-source current flowing through the input tube;
from the above formula: bandwidth of error amplifier and g of input pair tube m The values are directly proportional, and g m With current I flowing through the input pair D If the dynamic current bias circuit of the load current sampling feedback technology is utilized, the sampled bias current is directly injected into the bias circuit of the error amplifier, and the dynamic current is respectively distributed to the differential input pair transistors and the sleeve structure according to the distribution proportion of the fixed bias current designed by the original error amplifier:
case where no dynamic bias current is injected:
case of injecting dynamic bias current:
with following
Injection of bias current I through differential input pair D Increases of (2) increases gm of the differential input pair transistors, correspondingly also widens the bandwidth of the error amplifier, but with l' 2 The injection of (2) also correspondingly and obviously reduces the output resistance r of each transistor in the sleeve structure o The output resistance R of the error amplifier is correspondingly reduced OUT According to the second formula, the gain of the error amplifier is correspondingly reduced, so that the power supply rejection ratio of the LDO is reduced at low frequency, as shown in fig. 3, curve one is the LDO power supply rejection ratio curve without the dynamic bias circuit, curve two is the LDO power supply rejection ratio curve with the dynamic bias circuit, and the comparison shows: albeit due to g m The LDO power supply rejection ratio in the high frequency band is improved along with the increase of the bias current, but the R of the error amplifier is increased along with the increase of the bias circuit out Become smaller, A EA The power supply rejection ratio of the medium and low frequency is also reduced, and the design goal is not met.
In order to reasonably broaden the bandwidth of the error amplifier, improve the high-frequency open-loop gain in the error amplifier and further improve the power supply rejection ratio of the LDO, the invention adopts a novel dynamic sampling current bias circuit module in the error amplifier, as shown in fig. 2. Where Isense is the sampling current, M 1 And M 2 、M 3 And M 4 Respectively constitute a current mirror, M 4 Providing dynamic bias current I for amplifier input pair tube B1 ，M 7 And M 8 Providing a dynamic bias current I for a cascode circuit B2 And I B3 Wherein the dynamic bias current:
case where no dynamic bias current is injected:
case of injecting dynamic bias current:
design of
Then I' 2 ＝0
Due to I' 1 And I' 2 Is zero, and g is generated according to the formula IV and the formula VI as the current flowing through the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor and the seventeenth transistor is the same as the case of not adding the dynamic bias current m15 、g m13 、r m15 、r m17 、r m13 The values of the input signals are the same as those before the dynamic bias current is not injected, the output resistance of the error amplifier cannot be obviously reduced due to the addition of the dynamic bias current according to a formula five, the injected dynamic bias current is completely injected into the differential input pair transistors, the gm of the input pair transistors can be obviously improved, according to a formula two and a formula three, the injection mode can greatly improve the open-loop gain and widen the bandwidth of the error amplifier, and the gain A of the error amplifier is also increased EA The power supply rejection ratio of the LDO is obviously improved according to the formula (1), and the power supply rejection ratio of the LDO using the sampling circuit and the dynamic bias adjusting error amplifier in the embodiment of the present invention is shown by a dashed line in curve two of fig. 4. Comparing with curve one of fig. 4 (LDO power supply rejection ratio graph with error amplifier without dynamic bias adjustment), it can be seen that: the power supply rejection ratio in the middle and high frequency ranges is greatly improved, and the power supply rejection ratio in the middle and low frequency ranges also keeps a higher level.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.
Claims (7)
1. A low-power consumption high power supply rejection ratio LDO circuit with a sampling load current technology is characterized by comprising: the dynamic current bias error amplifier, the adjusting tube MP, the resistance feedback circuit, the reference circuit and the output current dynamic sampling circuit are driven: the output current dynamic sampling circuit is connected with the dynamic bias input end of the error amplifier; the inverting input of the error amplifier is connected with a reference voltage source VREF, the output end of the error amplifier is connected with the control ends of the adjusting tube MP and the sampling tube MS, and the adjusting tube MP is connected with the non-inverting input end of the error amplifier through the resistance feedback circuit; the input end of the adjusting tube is connected with a power supply, and the common end of the adjusting tube MP and the resistance feedback circuit is used as the output end of the low dropout linear regulator circuit; the error amplifier outputs a feedback voltage V output by the resistance feedback circuit FB And a reference voltage V REF Comparing to generate an error signal, and adjusting the adjusting tube MP by amplifying the error signal; by sampling the bias current fed back to the error amplifier by the load current and adopting the bias current distribution circuit, the gain of the medium-high frequency error amplifier is improved, and meanwhile, the bandwidth of the error amplifier is also increased.
2. The LDO circuit with low power consumption and high power supply rejection ratio of claim 1, wherein the output current dynamic sampling circuit comprises a first transistor M 1 A second transistor M 2 Eighteenth body tube M S (ii) a The eighteenth body tube M S Is connected to a power supply, the eighteenth transistor M S Is connected to the first transistor M 1 Output terminal and first transistor M 1 And a second transistor M 2 The second transistor M, the second transistor M 2 Output end is connected withThe first transistor M is connected with the dynamic bias input end of the error amplifier 1 And a second transistor M 2 The input terminal of the switch is connected with the ground terminal.
3. The LDO circuit with low power consumption and high power supply rejection ratio of claim 1, wherein the error amplifier comprises: third transistor M 3 A fourth transistor M 4 A fifth transistor M 5 And a sixth transistor M 6 The seventh transistor M 7 The eighth transistor M 8 The ninth transistor M 9 The tenth transistor M 10 Eleventh transistor M 11 The twelfth transistor M 12 Thirteenth transistor M 13 Fourteenth transistor M 14 Fifteenth transistor M 15 Sixteenth transistor M 16 And a seventeenth transistor M 17 (ii) a The fifth transistor M 5 Is connected to the power supply, the fifth transistor M 5 Is connected with a fourth bias voltage V b4 Said fifth transistor M 5 Are respectively connected with the sixth transistor M 6 And said seventh transistor M 7 An input terminal of (a); the sixth transistor M 6 As the non-inverting input terminal of the error amplifier, a seventh transistor M 7 The control end of the error amplifier is used as the inverting input end of the error amplifier and is connected with the reference voltage source VREF; the sixteenth transistor M 16 And the seventeenth transistor M 17 The input ends of the first and second transistors are connected with the power supply, and the sixteenth transistor M is connected with the power supply 16 And a control terminal and the seventeenth transistor M 17 The control end of the controller is connected; the fourteenth transistor M 14 Is connected to the sixteenth transistor M 16 The fourteenth transistor M 14 And the fifteenth transistor M 15 And the common end of the two control ends is connected with a first bias voltage V b1 The fifteenth transistor M 15 Is connected to the seventeenth transistor M 17 An output terminal of (a); the twelfth transistor M 12 Is connected to the fourteenth transistor M 14 Of the twelfth transistor M 12 Is connected with the thirteenth transistor M 13 And a common terminal of the two control terminals is connected with a second bias voltage V b2 The thirteenth transistor M 13 Is connected to the fifteenth transistor M 15 Wherein the thirteenth transistor M 13 And the fifteenth transistor M 15 As an output terminal of the error amplifier; the tenth transistor M 10 Is connected to the twelfth transistor M 12 And the tenth transistor M, and 10 is connected to the sixth transistor M 6 The tenth transistor M 10 Is connected to the ground terminal, the tenth transistor M 10 Is connected with the eleventh transistor M 11 And a common terminal of the two control terminals is connected with a third bias voltage V b3 The eleventh transistor M 11 Is connected to the thirteenth transistor M 13 And the thirteenth transistor M 13 Is connected to the seventh transistor M 7 The thirteenth transistor M 13 The output end of the switch is connected with a grounding end; the third transistor M 3 And said fourth transistor M 4 Are all connected to the supply voltage, the third transistor M 3 Is connected to the second transistor M 2 An output terminal, the third transistor M 3 Is connected to the fourth transistor M 4 And a common terminal of the two control terminals is connected with the second transistor M 2 An output terminal, the fourth transistor M 4 Are connected with the sixth transistor M respectively 6 And said seventh transistor M 7 An input terminal of (1); the eighth transistor M 8 And said ninth transistor M 9 Are all connected to the ground terminal, the eighth transistor M 8 A control terminal connected with the ninth transistorM 9 A control end and a common end of the two control ends are connected with the eighteenth transistor M S An output terminal, the eighth transistor M 8 Is connected to the twelfth transistor M 12 The ninth transistor M, the ninth transistor M 9 Is connected to the thirteenth transistor M 13 To the output terminal of (a).
4. The LDO circuit with low power consumption and high power supply rejection ratio of claim 3, wherein the third transistor M is configured to be connected to the load current sampling circuit 3 The fourth transistor M 4 The fifth transistor M 5 The sixth transistor M 6 The seventh transistor M 7 The twelfth transistor M 12 The thirteenth transistor M 13 The fourteenth transistor M 14 The fifteenth transistor M 15 The sixteenth transistor M 16 And the thirteenth transistor M 13 Is a PMOS tube; the eighth transistor M 8 The ninth transistor M 9 The tenth transistor M 10 And the eleventh transistor M 11 Is an NMOS tube.
5. The LDO circuit with low power consumption and high power supply rejection ratio of sampled load current technique of claim 1, wherein said resistive feedback circuit comprises: a first resistor R 1 And a second resistor R 2 (ii) a The first resistor R 1 One end of the first resistor R is connected with the output end of the adjusting tube MP 1 Is passed through said second resistor R 2 Connected to ground, the first resistor R 1 And said second resistance R 2 The common terminal of the first resistor is used as the output terminal of the feedback resistor and is connected with the non-inverting input terminal of the error amplifier.
6. An algorithm with low power consumption and high power supply rejection ratio of a sampled load current technology is characterized by comprising the following steps:
increasing the loop gain of the LDO to improve the power supply noise rejection characteristics of the LDO:
in the formula, A EA Is the gain of the error amplifier, beta is the feedback coefficient of the feedback circuit, A POW For gain of the power stage, PSR EA And PSR POW The power supply rejection ratios of the error amplifier and the power stage are respectively independent, and the formula shows that the gain of the error amplifier is increased, so that the power supply noise rejection characteristic of the LDO can be improved;
to improve the power noise suppression characteristics of the LDO at medium and high frequencies, the gain of the error amplifier at medium and high frequency bands is increased, and for the error amplifier:
A EA ＝g m *R out (2)
R OUT ≈g m15 r m15 r m17 ||g m13 r m13 (r m7 ||r m11 ) (5)
in the formula, g m Representing the transconductance, r, of the input tube of the error amplifier m15 、r m17 、r m13 、r m7 、r m11 Respectively, a fifteenth transistor M in the sleeve structure of the error amplifier 10 Seventeenth transistor M 17 Thirteenth transistor M 13 The seventh transistor M 7 Eleventh transistor M 11 Output resistance of g m15 、g m13 Are thirteenth transistors M respectively 13 And a fifteenth transistor M 15 Transconductance of (3), R out Representing the output resistance of the error amplifier, GBW EA Is the gain-bandwidth product of the error amplifier, C POW Load capacitance of the output stage of the error amplifier, I D Is the drain-source current flowing through the input tube;
from the above formula, it can be seen that: bandwidth of error amplifier and g of input pair tube m The value is proportional, and g m With current I flowing through the input pair D Increasing and increasing, directly injecting the sampled bias current into the bias circuit of the error amplifier by using a dynamic current bias circuit of a load current sampling feedback technology, and distributing the dynamic current to the differential input pair transistors and the sleeve structure respectively according to the fixed bias current distribution proportion designed by the original error amplifier:
case where no dynamic bias current is injected:
case of injecting dynamic bias current:
with following
Injection of bias current I through differential input pair D Increases in (2) increase gm of the differential input pair transistors, and correspondingly broaden the bandwidth of the error amplifier, but with I' 2 The injection of (2) also correspondingly and obviously reduces the output resistance r of each transistor in the sleeve structure o The output resistance R of the error amplifier is correspondingly reduced OUT The gain of the error amplifier is also reduced accordingly according to equation (2), resulting in LDOThe power supply rejection ratio decreases at low frequencies.
7. The algorithm of claim 6, wherein M is a power supply rejection ratio of LDO for further improving the power supply rejection ratio 4 Providing dynamic bias current I for amplifier input pair B1 ,M 7 And M 8 Providing a dynamic bias current I for a cascode circuit B2 And I B3 Wherein the dynamic bias current:
case of no injected dynamic bias current:
case of injecting dynamic bias current:
design of
Then I' 2 ＝0
Due to I' 1 And I' 2 Is zero, flows through the twelfth transistor M 12 Thirteenth transistor M 13 And a fourteenth transistor M 14 Fifteenth transistor M 15 Sixteenth transistor M 16 Seventeenth transistor M 17 The current of (d) is the same as the current without dynamic bias, g is determined according to the equations (4) and (6) m15 、g m13 、r m15 、r m17 、r m13 The values of the two are the same as before the dynamic bias current is not injected, and the output resistance of the error amplifier is not influenced according to the formula (5)In order to obviously reduce the addition of the dynamic bias current, the injected dynamic bias current is totally injected into the differential input pair tube to obviously improve gm of the input pair tube, and according to the formula (2) and the formula (3), the injection mode is used for improving open loop gain and widening bandwidth of the error amplifier, and the same follows the gain A of the error amplifier EA The power supply rejection ratio of the LDO is obviously improved according to the formula (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211137078.9A CN115542988A (en) | 2022-09-19 | 2022-09-19 | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211137078.9A CN115542988A (en) | 2022-09-19 | 2022-09-19 | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115542988A true CN115542988A (en) | 2022-12-30 |
Family
ID=84727436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211137078.9A Pending CN115542988A (en) | 2022-09-19 | 2022-09-19 | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115542988A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
-
2022
- 2022-09-19 CN CN202211137078.9A patent/CN115542988A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7218087B2 (en) | Low-dropout voltage regulator | |
| US7218082B2 (en) | Compensation technique providing stability over broad range of output capacitor values | |
| US20190004553A1 (en) | Ripple pre-amplification based fully integrated low dropout regulator | |
| US7719241B2 (en) | AC-coupled equivalent series resistance | |
| CN114253330A (en) | Quick transient response's no off-chip capacitance low dropout linear voltage regulator | |
| KR101238173B1 (en) | A Low Dropout Regulator with High Slew Rate Current and High Unity-Gain Bandwidth | |
| CN111273724B (en) | Stability-compensated linear voltage regulator and design method thereof | |
| JP2003084843A (en) | Linear regulator | |
| CN101105696A (en) | Voltage buffer circuit for linear potentiostat | |
| CN111522389A (en) | Wide-input low-dropout linear voltage stabilizing circuit | |
| CN104679088A (en) | Low dropout linear regulator and frequency compensating circuit thereof | |
| CN110320963A (en) | Low-dropout linear voltage-regulating circuit | |
| CN115328254B (en) | High transient response LDO circuit based on multiple frequency compensation modes | |
| CN108052153A (en) | The LDO linear voltage regulators of New-type CMOS structure | |
| CN207731181U (en) | The LDO linear voltage regulators of New-type CMOS structure | |
| CN115981408B (en) | Extra-low voltage difference output transient enhanced off-chip capacitor LDO circuit | |
| CN110808720B (en) | Anti-saturation radio frequency power amplifier | |
| CN211878488U (en) | Wide-input low-dropout linear voltage stabilizing circuit | |
| CN115542988A (en) | Low-power-consumption high-power-supply-rejection-ratio LDO (Low dropout regulator) circuit with sampling load current technology and algorithm | |
| CN113672019B (en) | Dynamic bias high PSRR low dropout regulator | |
| Tang et al. | A Low-Power Fast-Transient Output-Capacitorless LDO | |
| CN115268550B (en) | Quick-response low-dropout linear voltage stabilizing circuit | |
| CN106155155A (en) | One single-transistor low dropout voltage regulator | |
| CN116149419B (en) | High power supply rejection ratio LDO circuit applicable to medium and high frequencies | |
| CN219143338U (en) | Linear voltage stabilizer and system on chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |