CN115981408B - Extra-low voltage difference output transient enhanced off-chip capacitor LDO circuit - Google Patents
Extra-low voltage difference output transient enhanced off-chip capacitor LDO circuit Download PDFInfo
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Abstract
The invention belongs to the technical field of analog integrated circuits, and particularly provides an ultra-low voltage differential output transient enhanced off-chip capacitor LDO circuit which is used for solving the problems that in the prior art, the transient response is poor and the low voltage differential output under low-voltage operation cannot be realized in a voltage feedback mode. The invention comprises the following steps: the first-stage error amplifier, the power tube, the frequency compensation module, the feedback module and the second-stage error amplifier, wherein the feedback module generates a first feedback signal and a second feedback signal which are respectively input into the first-stage error amplifier and the second-stage error amplifier to form a double-loop feedback structure; the invention also provides a corresponding current feedback mode, the ultralow differential pressure output under the working conditions of low input and low output voltage is realized through current feedback, and the transient response performance is improved through a double loop feedback structure; finally, the invention realizes ultra-low differential pressure output, ensures loop gain performance, realizes rapid transient response when output load jumps, and meets the index requirement of higher precision.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly provides an off-chip voltage regulator (LDO) circuit with enhanced transient response of ultralow voltage difference output.
Background
As shown in FIG. 1, the conventional off-chip capacitor LDO circuit mainly comprises an error amplifier, a power tube (M P ) Voltage feedback module (feedback resistor R) F1 And R is F2 ) Frequency compensation module (C) m ) Constructing; input voltage V dd Connected to the power tube M P Source electrode of power tube M P Is output voltage signal V by the drain electrode of (2) out Resistance R F1 And R is F2 Sampling the output voltage in series, sampling the voltage and the reference voltage V ref The difference value of (2) is amplified by an operational amplifier and then fed back to the power tube M P To the grid electrode of the power tube M P The on-resistance of the voltage regulator is regulated, so that the stability of an output voltage signal is realized; wherein R is 1 And C 1 Equivalent resistance and equivalent capacitance of the output node of the error amplifier, R L And C P The output load resistance and the output node parasitic capacitance of the circuit respectively. Power tube M P The branch is the main branch of LDO, resistor R F1 And R is F2 Realizing the accuracy ofOutputting a voltage signal and a feedback voltage signal; power tube M working in saturation region P Can be regarded as a variable resistor, when the input voltage or the output load changes, the output voltage correspondingly changes, and the change generates a feedback signal by the feedback resistor and is transmitted into the power tube M through a negative feedback loop P Is a gate electrode of (2): the gate capacitor is charged and discharged, so that the resistance value of the variable resistor is adjusted, and the output voltage is ensured to be quickly stabilized after being changed in a very small range.
The output capacitance of the traditional off-chip capacitor LDO circuit mainly comes from the parasitic capacitance of the PCB layout, and the value of the output capacitance is very small; when the switching (transient change) is fast under different working conditions, a certain time is needed in the loop feedback signal adjusting process, and the output voltage signal is easy to generate larger transient fluctuation, so that the load is greatly influenced. Meanwhile, the reference voltage V in the conventional off-chip capacitor LDO circuit ref As shown in FIG. 2, due to the reference voltage V ref Determined by the forbidden band width of silicon, is generally not less than 1.12V, and the input voltage V dd Is the reference voltage V ref Adding a drain-source voltage of the MOS tube and a gate-source voltage of the MOS tube, wherein the drain-source voltage and the gate-source voltage of the MOS tube are generally not less than 1.5V; when the power supply voltage required by the load is significantly lower than 1.5V, the LDO cannot realize the output of the reference voltage, namely the voltage feedback mode in the traditional off-chip capacitor LDO circuit cannot realize the low-voltage difference output under the low-voltage operation.
Disclosure of Invention
The invention aims to provide an ultra-low voltage difference output transient enhanced off-chip capacitor LDO circuit, which is used for solving the problems that the transient response of the traditional off-chip capacitor LDO circuit is poor and the low voltage difference output under low-voltage operation cannot be realized in a voltage feedback mode; the invention provides a double-loop feedback structure and a current feedback mode, wherein the ultralow differential pressure output under the working conditions of low input and low output voltage is realized through current feedback, and the transient response performance is improved and more stable output voltage is provided through the double-loop feedback structure; finally, the invention realizes ultra-low differential pressure output, ensures loop gain performance, realizes rapid transient response when output load jumps, and meets the index requirement of higher precision.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an ultra-low dropout output transient enhanced off-chip capacitor LDO circuit comprising: the device comprises a current reference module, a first-stage error amplifier, a power tube, a frequency compensation module and a feedback module; characterized by further comprising: the second-stage error amplifier, the current reference module outputs reference current I ref To the negative input end of the first-stage error amplifier, the first-stage error amplifier is cascaded with the second-stage error amplifier, and the output end of the second-stage error amplifier is connected with the power tube M P Grid electrode of power tube M P The drain electrode series feedback module generates a first feedback signal and a second feedback signal, and the first feedback signal and the second feedback signal are respectively input to the positive input end of the first-stage error amplifier and the feedback end of the second-stage error amplifier to form a closed loop.
Further, the second-stage error amplifier is formed by an MOS tube M 23 ～M 28 Constitute, wherein, MOS pipe M 23 And M is as follows 24 The sources of (a) are connected with the power supply voltage V dd MOS tube M 23 A grid electrode of the MOS transistor M is used as a positive input end and connected with a positive output end of the first-stage error amplifier 24 The grid electrode of the first-stage error amplifier is used as a negative input end and is connected with a negative output end of the first-stage error amplifier; MOS tube M 23 Drain electrode of (d) and MOS transistor M 25 Drain electrode of (d), MOS transistor M 25 Gate electrode of (d), MOS tube M 26 The grid electrodes of the MOS tube M are connected 24 Drain electrode of (d) and MOS transistor M 26 The drain electrode of the transistor is connected with the connecting point as an output end; MOS tube M 25 Source electrode of (d) and MOS transistor M 27 Drain electrode of (d), MOS transistor M 27 Gate electrode of (d), MOS tube M 28 The grid electrodes of the MOS tube M are connected 26 Source electrode of (d) and MOS transistor M 28 Is connected with the drain electrode of the transistor; MOS tube M 27 And M is as follows 28 The source electrodes of the MOS tube M are all grounded 26 Source electrode of (d) and MOS transistor M 28 Is connected to the drain of the transistor and the connection point is used as a feedback terminal.
Further, the feedback module is formed by a MOS tube M 29 And M is as follows 30 Resistance R 2 Capacitance C 2 Constitute, MOS tube M 29 And M is as follows 30 The drain electrodes of (C) are connected to form a series resistor R 2 To power tube M P Drain electrode of MOS tube M 29 And M is as follows 30 Source electrode of MOS tube M is grounded 30 Is connected with bias voltage V N MOS tube M 29 A first feedback signal is outputted by the grid electrode of the capacitor C 2 And then forming a second feedback signal.
Furthermore, the first-stage error amplifier adopts an operational amplifier with an NCM structure and is of a double-end input and double-end output structure.
Further, the frequency compensation module is a capacitor C 1 Capacitance C 1 And the positive output end of the first-stage error amplifier is connected in a bridging manner.
Based on the technical scheme, the invention has the beneficial effects that:
the invention provides an ultra-low voltage difference output transient enhanced off-chip capacitor LDO circuit which adopts a current feedback mode to solve the problem that a voltage feedback mode cannot generate a stable reference voltage signal irrelevant to a power supply and temperature under low-voltage operation; meanwhile, the double negative feedback loops are adopted for adjustment, the large loop realizes high gain, the small loop improves response speed, the double loops are mutually nested and work simultaneously, and voltage signals are stably output; finally, compared with the traditional LDO circuit structure without the off-chip capacitor, the LDO circuit structure has the advantages of low working voltage, stable signal response, high speed and the like.
Drawings
FIG. 1 is a schematic diagram of a conventional off-chip capacitor LDO circuit.
Fig. 2 is a schematic diagram of a common voltage bandgap reference.
FIG. 3 is a schematic diagram of an ultra-low dropout output transient enhancement (ULDO) circuit according to the present invention.
FIG. 4 is a schematic circuit diagram of an ultra-low dropout output transient enhanced off-chip capacitor LDO circuit according to the present invention.
FIG. 5 is a schematic diagram of an ultra-low dropout LDO circuit with transient enhancement in the present invention, wherein (a) is a first loop and (b) is a second loop.
FIG. 6 is a transient response curve of an ultra-low dropout output transient enhanced off-chip capacitor LDO circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples.
The embodiment provides an ultra-low dropout output transient enhanced off-chip capacitor LDO circuit, the structure of which is shown in FIG. 3, comprising: the device comprises a current reference module, a first-stage error amplifier, a second-stage error amplifier, a power tube, a frequency compensation module and a feedback module; the current reference module outputs reference current I ref To the negative input end of the first-stage error amplifier, the first-stage error amplifier is cascaded with the second-stage error amplifier, and the output end of the second-stage error amplifier is connected with the power tube M P Grid electrode of power tube M P The drain electrode series feedback module generates a first feedback signal and a second feedback signal, and the first feedback signal and the second feedback signal are respectively input to the positive input end of the first-stage error amplifier and the feedback end of the second-stage error amplifier to form a closed loop.
Further, a schematic diagram of the ultra-low dropout output transient enhanced off-chip capacitor LDO circuit is shown in fig. 4, and is specifically as follows:
the current reference module adopts a MOS tube M 1 ～M 4 And resistance R 1 Constituted with supply voltage V dd Independent reference circuit for generating reference current signal I ref The method comprises the steps of carrying out a first treatment on the surface of the The specific structure is prior art in the field, and is not described herein;
the first-stage error amplifier adopts an operational amplifier with an NCM structure and has a structure of double-end input (positive input end and negative input end) and double-end output (positive output end and negative output end), and is specifically composed of an MOS tube M 5 ～M 22 Constructing; the specific structure is prior art in the field, and is not described herein;
the second-stage error amplifier is formed by an MOS tube M 23 ～M 28 The structure is composed of a double-ended input (a positive input end and a negative input end) and a single-ended output; MOS tube M 23 And M is as follows 24 The sources of (a) are connected with the power supply voltage V dd MOS tube M 23 A grid electrode of the MOS transistor M is used as a positive input end and connected with a positive output end of the first-stage error amplifier 24 The grid electrode of the first stage error amplifier is used as a positive input end and is connected with a negative output end of the first stage error amplifier; MOS tube M 23 Drain electrode of (d) and MOS transistor M 25 Drain electrode of (d), MOS transistor M 25 Gate electrode of (d), MOS tube M 26 The grid electrodes of the MOS tube M are connected 24 Drain electrode of (d) and MOS transistor M 26 The drain electrode of the transistor is connected with the connecting point as an output end; MOS tube M 25 Source electrode of (d) and MOS transistor M 27 Drain electrode of (d), MOS transistor M 27 Gate electrode of (d), MOS tube M 28 The grid electrodes of the MOS tube M are connected 26 Source electrode of (d) and MOS transistor M 28 Is connected with the drain electrode of the transistor; MOS tube M 27 And M is as follows 28 The source electrodes of the MOS tube M are all grounded 26 Source electrode of (d) and MOS transistor M 28 The drain electrode of the transistor is connected with the connecting point as a feedback end;
the frequency compensation module is a capacitor C 1 Capacitance C 1 The positive output end of the first-stage error amplifier is connected with the output end of the circuit in a bridging way;
the feedback module is composed of an MOS tube M 29 And M is as follows 30 Resistance R 2 Capacitance C 2 Constitute, MOS tube M 29 And M is as follows 30 The drain electrodes of (C) are connected to form a series resistor R 2 To power tube M P Drain electrode of MOS tube M 29 And M is as follows 30 Source electrode of MOS tube M is grounded 30 Is connected with bias voltage V N MOS tube M 29 The grid electrode of the first stage error amplifier outputs a first feedback signal to the positive input end of the first stage error amplifier, and the first feedback signal passes through the capacitor C 2 And then forming a second feedback signal and feeding the second feedback signal back to the feedback end of the second-stage error amplifier.
In terms of working principle:
the embodiment proposes an ultra-low dropout output transient enhanced off-chip capacitor LDO circuit, which comprises two loops, as shown in FIG. 5; wherein:
the first loop is composed of a first error amplifier, a second error amplifier, and a power tube M P Is composed of a feedback module, a first error amplifier with two ends input,A double-end output connected to the second-stage error amplifier, and a single-end output of the second-stage error amplifier is connected to the power tube M P Grid electrode of power tube M P The drain output of (a) to the feedback module as shown in fig. 5 (a); the second loop is routed to the second stage error amplifier and the power tube M P The feedback end of the second-stage error amplifier is used as a second input point, the input tube of the second-stage error amplifier is originally used as a load tube, and the output end of the second-stage error amplifier is output to the power tube M P Grid electrode of power tube M P The drain output of (a) to the feedback module as shown in (b) of fig. 5; thus realizing the operational amplifier structure with the double loops nested with each other.
The feedback module simultaneously samples output voltage and current signals, and the MOS tube M adopting a diode connection mode is adopted 29 The grid electrode of the first loop is connected with the input end (the positive input end of the first-stage error amplifier) to form a current feedback network, and the current feedback network is connected with the input end of the first loop through a small capacitor C 2 And the input end of the second loop (the feedback end of the second-stage error amplifier) is connected to form a voltage feedback network. The first loop is a current feedback mode, and MOS tube M in the feedback module 29 And M 30 Sampling the output current; wherein, MOS tube M 29 Adopt diode connection mode, MOS pipe M 30 The reference source current is duplicated in proportion, the drains of the two MOS tubes are connected, and the feedback current only samples the current flowing through the MOS tube M 29 The current of the feedback module is subtracted from the current flowing through the feedback module to the MOS tube M 30 Is set to be a current of (a); therefore, the feedback module samples the output current which is reduced according to a certain proportion, and the reduction proportion can improve the loop gain of the first loop and realize high loop gain and certain loop bandwidth. The second loop is a voltage feedback mode, and in order to prevent the two loops from interfering with each other and prevent the accuracy of current sampling from being affected, the second loop needs to be connected with the MOS tube M 29 The voltage signal is led out and simultaneously passes through a small capacitor C 2 Isolating current and inputting the isolated current into a second loop; thereby, the second loop can realize a fast feedback function.
In order to analyze loop stability, the transfer function H(s) is found as:
A＝G ma1 R oa1 G ma2 R oa2 G mp R L (2)
f≈f b1 ≈f b2 (3)
the loop of the present invention is found to contain two zeros and three poles according to the transfer function:
wherein A is the DC gain of the operational amplifier, comprising: a first stage error amplifier and a second stage error amplifier; f is the feedback coefficient of the loop, f b1 For the feedback coefficient of the first loop, f b2 Feedback coefficients for the second loop; g ma 、C oa 、R oa Transconductance, output capacitance, output resistance (subscript 1, corresponding to first stage error amplifier, subscript 2, corresponding to second stage error amplifier) of the error amplifier, respectively, G mp Is the transconductance of the power tube.
It can be seen that the present embodiment proposes the operation of the ultra-low dropout output transient enhanced off-chip capacitor LDO circuitThe process is as follows: when the external working condition changes, the output current changes correspondingly, and the MOS tube M of the feedback module 29 Sampling output current, feeding back signal change to the positive input end of the first-stage error amplifier, converting the current signal into a voltage signal, and feeding the feedback signal into a first loop, wherein a two-stage full-differential operational amplifier structure (the first-stage error amplifier and the second-stage error amplifier) provides high gain and better loop stability, and reduces voltage jitter and response time in the output self-adjustment process; meanwhile, the MOS tube M of the feedback module 29 And capacitor C 2 Sampling the output voltage, sending the feedback signal into a second loop, and directly transmitting to the power tube M P A gate electrode of (a); the signal transmission path is short, has larger bandwidth and can achieve the effect of quick adjustment.
Finally, simulation test is performed on the ultra-low voltage differential output transient enhanced off-chip capacitor LDO circuit provided by the embodiment, and a transient response curve is shown in FIG. 6; as can be seen, the on-chip compensation capacitor C 1 When the input voltage is 3pF and is 1.25V, the ultra-low voltage difference output of 1.2V can be realized; when the output load resistor jumps from 50Ω to 2mΩ within 1 μs, 5.4 μs is required to stabilize the output voltage, and the overshoot voltage is 80mV; when the output load resistor jumps from 2MΩ to 50Ω within 1 μs, 8 μs of adjustment time is required, and the undershoot voltage drop is 73mV; compared with the conventional structure (single loop structure), the response time is reduced by more than 50%, the undershoot voltage is reduced by about 330mV, the undershoot voltage is reduced by 82%, and the performance is greatly improved.
In summary, the invention provides an ultra-low voltage differential output transient enhanced off-chip capacitor LDO circuit, which adopts a double-loop feedback structure and a current feedback mode, realizes ultra-low voltage differential output, ensures loop gain performance, realizes rapid transient response when an output load jumps, and meets the index requirement of higher precision.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (3)
1. An ultra-low dropout output transient enhanced off-chip capacitor LDO circuit comprising: current reference module, first-stage error amplifier and power tube M P The frequency compensation module and the feedback module; characterized by further comprising: the second-stage error amplifier, the current reference module outputs reference current I ref To the negative input end of the first-stage error amplifier, the first-stage error amplifier is cascaded with the second-stage error amplifier, and the output end of the second-stage error amplifier is connected with the power tube M P Grid electrode of power tube M P The drain electrode serial feedback module of the first-stage error amplifier generates a first feedback signal and a second feedback signal, the first feedback signal is input to the positive input end of the first-stage error amplifier, and the second feedback signal is input to the feedback end of the second-stage error amplifier to form a closed loop;
the second-stage error amplifier is formed by an MOS tube M 23 ~M 28 Constitute, wherein, MOS pipe M 23 And M is as follows 24 The sources of (a) are connected with the power supply voltage V dd MOS tube M 23 A grid electrode of the MOS transistor M is used as a positive input end and connected with a positive output end of the first-stage error amplifier 24 The grid electrode of the first-stage error amplifier is used as a negative input end and is connected with a negative output end of the first-stage error amplifier; MOS tube M 23 Drain electrode of (d) and MOS transistor M 25 Drain electrode of (d), MOS transistor M 25 Gate electrode of (d), MOS tube M 26 The grid electrodes of the MOS tube M are connected 24 Drain electrode of (d) and MOS transistor M 26 The drain electrode of the transistor is connected with the connecting point as an output end; MOS tube M 25 Source electrode of (d) and MOS transistor M 27 Drain electrode of (d), MOS transistor M 27 Gate electrode of (d), MOS tube M 28 The grid electrodes of the MOS tube M are connected 26 Source electrode of (d) and MOS transistor M 28 Is connected with the drain electrode of the transistor; MOS tube M 27 And M is as follows 28 The source electrodes of the MOS tube M are all grounded 26 Source electrode of (d) and MOS transistor M 28 The drain electrode of the transistor is connected with the connecting point as a feedback end;
the feedback module is composed of an MOS tube M 29 And M is as follows 30 Resistance R 3 Capacitance C 2 Constitute, MOS tube M 29 And M is as follows 30 The drain electrodes of (C) are connected to form a series resistor R 3 To power tube M P Drain electrode of MOS tube M 29 And M is as follows 30 Source electrode of MOS tube M is grounded 30 Is connected with bias voltage V N MOS tube M 29 A first feedback signal is outputted by the grid electrode of the capacitor C 2 And then forming a second feedback signal.
2. The ultra-low dropout output transient enhanced off-chip capacitor LDO circuit of claim 1, wherein said first stage error amplifier is an operational amplifier of NCM configuration, which is of a dual input, dual output configuration.
3. The ultra-low dropout output transient enhanced off-chip capacitor LDO circuit of claim 1, wherein said frequency compensation module is a capacitor C 1 Capacitance C 1 Across power tube M P Between the drain of the first stage error amplifier and the positive output of the first stage error amplifier.
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| CN116629186B (en) * | 2023-05-23 | 2024-02-06 | 广东匠芯创科技有限公司 | Layout design method and layout structure of two-stage fully differential operational amplifier |
| CN117348667A (en) * | 2023-11-07 | 2024-01-05 | 无锡盛景微电子股份有限公司 | Load switching transient enhanced ultralow static power consumption LDO circuit and working method |
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| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114546025A (en) * | 2022-02-28 | 2022-05-27 | 上海先楫半导体科技有限公司 | LDO circuit and chip with low static power consumption and rapid transient response |
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| TWI560538B (en) * | 2015-06-30 | 2016-12-01 | Univ Nat Tsing Hua | Feedback type voltage regulator |
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| CN105116955A (en) * | 2015-10-09 | 2015-12-02 | 东南大学 | Transient enhancement circuit applied to full-integration LDO |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114546025A (en) * | 2022-02-28 | 2022-05-27 | 上海先楫半导体科技有限公司 | LDO circuit and chip with low static power consumption and rapid transient response |
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