CN113064460A - Low dropout regulator circuit with high power supply rejection ratio - Google Patents
Low dropout regulator circuit with high power supply rejection ratio Download PDFInfo
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- CN113064460A CN113064460A CN202110315254.2A CN202110315254A CN113064460A CN 113064460 A CN113064460 A CN 113064460A CN 202110315254 A CN202110315254 A CN 202110315254A CN 113064460 A CN113064460 A CN 113064460A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a low dropout linear regulator circuit with high power supply rejection ratio, which comprises an input buffer stage circuit and an output regulation stage circuit, wherein the input buffer stage circuit consists of an amplifier AMP1, a power tube M1 and a capacitor C1, and the output regulation stage circuit consists of an amplifier AMP2, a power tube M2, voltage division resistors R1 and R2, an output capacitor C2 and a load resistor Rload; the input buffer stage circuit processes the ripple or noise signal of the input voltage VIN once, thereby effectively increasing the noise suppression effect of VIN to VOUT. The invention changes the condition that the traditional linear voltage stabilizer is only connected with an input capacitor to inhibit useless signals such as noise of an input stage, and the like, can effectively increase the noise inhibition effect from VIN to VOUT by adding an input buffer stage circuit, improves the power supply inhibition ratio, and can also effectively reduce the noise of the linear voltage stabilizer.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a low dropout regulator circuit with a high power supply rejection ratio.
Background
With the wider and more complex applications of communication products, the requirements of different kinds of electronic products are also higher and higher. These communication systems rely on high performance data processing chips, radio frequency chips. The power supply of the devices can not be disconnected, and the linear voltage stabilizer has high performance, low noise and high power supply rejection ratio.
In a power supply system, a power supply of a high-performance processing chip in an electronic product is converted into a voltage value of 5V, 3.3V, 1.8V or lower through a DCDC processing chip, but a switching power supply has the characteristics of large ripple and high noise, and cannot directly supply power to the high-performance data processing chip and a data conversion chip or a radio frequency chip, so that a low-dropout linear voltage regulator is required for energy transition or conversion. Therefore, the power supply rejection ratio of the low dropout linear regulator also directly influences high-performance data processing or whether the power supply of the radio frequency chip is pure or not.
The traditional linear voltage regulator has no input buffer stage part, the input voltage VIN is directly connected to the source stage of the PMOS power tube M2, and due to the structural limitation of the traditional linear voltage regulator, the power supply rejection ratio of the traditional structure in both a low frequency band and a high frequency band cannot be very high, and the traditional linear voltage regulator can not meet the requirement for supplying power to a precision control or operation chip with higher and higher power supply rejection requirements.
Disclosure of Invention
In order to solve the above problems, the present invention provides a low dropout regulator circuit with high power supply rejection ratio, comprising an input buffer stage circuit and an output regulation stage circuit, the power supply of the input buffer stage circuit is connected with an input voltage VIN, the output end of the input buffer stage circuit is connected with the input end of the output regulating stage circuit, the output end of the output regulation stage circuit is connected with the output voltage VOUT, the input buffer stage circuit comprises an amplifier AMP1 and a power tube M1, the negative input end of the amplifier AMP1 is connected with the reference voltage V1, the positive input end of the amplifier AMP1 is connected with the output voltage V2 end of the input buffer stage circuit, the output end of the amplifier AMP1 is connected with the grid electrode of a power tube M1, the source electrode and the substrate of the power tube M1 are connected with an input voltage VIN, and the drain electrode of the power tube M1 is connected with the output voltage V2 end of the input buffer stage circuit.
Preferably, the output regulation stage circuit includes an amplifier AMP2, a power tube M2, voltage division ratio resistors R1 and R2, an output load capacitor C2, and an output load resistor Rload of the linear regulator, a negative input terminal of the amplifier AMP2 is connected to a reference voltage VREF, a positive input terminal of the amplifier AMP2 is connected to an intermediate voltage V3 terminal, an output terminal of the amplifier AMP2 is connected to a gate of the power tube M2, a source and a substrate of the power tube M2 are connected to a voltage V2 terminal, a drain of the power tube M2 is connected to the output voltage VOUT, a first terminal of the voltage division resistor R1 is connected to the output voltage VOUT, a second terminal of the voltage division resistor R1 is connected to the intermediate voltage V3 terminal, a first terminal of the voltage division resistor R2 is connected to the intermediate voltage V3 terminal, a second terminal of the voltage division resistor R2 is grounded, a first terminal of the output load capacitor C2 is connected to the output voltage VOUT, the second end of the output load capacitor C2 is grounded, the first end of the output load resistor Rload is connected with the output voltage VOUT, and the second end of the output load resistor Rload is grounded.
Preferably, the input buffer stage circuit further comprises a bypass capacitor C1, one end of the bypass capacitor C1 is connected to the end of the output voltage V2 of the input buffer stage circuit, and the other end of the bypass capacitor C1 is grounded, so as to discharge the high-frequency noise signal of the output voltage V2 of the input buffer stage circuit to ground.
Preferably, the amplifier AMP1 is connected in a negative feedback configuration to clamp the reference voltage V1 and the input buffer stage output voltage V2 to be equal, so that the input buffer stage output voltage V2 is equal to the voltage V1.
Preferably, the amplifier AMP2 is connected in a negative feedback configuration to clamp the reference voltage VREF and the intermediate voltage V3.
Preferably, the power tube M1 and the power tube M2 are both PMOS power tubes.
The invention has the beneficial effects that: an active filtering buffer stage is added to the input stage of the traditional linear voltage regulator, so that the overall power supply suppression effect of the linear voltage regulator is greatly improved, and the power supply suppression ratio is almost doubled compared with that of the traditional framework no matter in a low frequency band or a high frequency band.
Drawings
FIG. 1 is a schematic diagram of a conventional low dropout linear regulator circuit;
FIG. 2 is a schematic diagram of the circuit structure of the present invention.
Detailed Description
Referring to fig. 1, the conventional linear regulator has no input buffer stage part, and the input voltage VIN is directly connected to the source stage of the PMOS power transistor M2, and due to the structural limitation of the conventional linear regulator, the power supply rejection ratio of the conventional linear regulator in both the low frequency band and the high frequency band is not very high, and the conventional linear regulator cannot meet the requirement for supplying power to a precision control or operation chip with higher and higher power supply rejection requirements.
To solve the above problem, referring to fig. 2, the present invention provides a low dropout regulator circuit with high power supply rejection ratio, the whole circuit is divided into two parts: an input buffer stage circuit and an output regulation stage circuit.
Furthermore, the input buffer stage circuit is used for isolating the input end VIN from the output end VOUT, and isolating ripple or noise signals at the VIN end, and the ripple or noise at the VIN end is transmitted to the VOUT end to be smaller when the power supply rejection ratio is higher.
Further, the input buffer stage circuit comprises an amplifier AMP1, a PMOS power tube M1 and a capacitor C1.
Further, in the input buffer stage circuit, a negative input terminal of the amplifier AMP1 is connected to the reference voltage V1 terminal, a positive input terminal of the amplifier AMP1 is connected to the input buffer stage circuit output voltage V2 terminal, and an output terminal of the amplifier AMP1 is connected to the gate of the PMOS power transistor M1.
Further, in the input buffer stage circuit, the source and the substrate of the PMOS power transistor M1 are connected to the input voltage VIN, the drain of the PMOS power transistor M1 is connected to the output voltage V2 terminal of the input buffer stage circuit, the upper stage plate of the capacitor C1 is connected to the output voltage V2 of the input buffer stage circuit, and the lower stage plate of the capacitor C1 is connected to GND. The amplifier AMP1 is thus connected in a negative feedback configuration to clamp the reference voltage V1 to the input buffer stage output V2 (also called the operational amplifier needs to be short) so that the voltage V2 is equal to the voltage V1 and the voltage V1 is a fixed voltage generated by the chip internal reference. Therefore, V2 is also a fixed voltage that does not change with the VIN voltage or the current flowing through M1. Wherein the capacitor C1 is a bypass capacitor of V2, the high frequency noise signal of V2 can be discharged to the ground.
Further, in the input buffer stage circuit structure, VIN is regarded as a power supply, and V2 is regarded as an output voltage. The power supply rejection ratio of VIN to V2 is about 60dB at low frequency, and the rejection ratio of high frequency power supply is about 20-30 dB.
Further, the output regulation stage circuit comprises an amplifier AMP2, a PMOS power tube M2, voltage division ratio resistors R1 and R2, an output load capacitor C2 and an output load resistor Rload of the linear voltage regulator.
Further, in the output regulation stage circuit, a negative input terminal of the amplifier AMP2 is connected to the reference voltage VREF, a positive input terminal of the amplifier AMP2 is connected to the intermediate voltage V3 between the divider proportional resistors R1 and R2, and an output terminal of the amplifier AMP2 is connected to the gate of the PMOS power transistor M2. Amplifier AMP2 is also connected in a negative feedback configuration, clamping V3 together with VREF, which is the linear regulator internal reference voltage.
Further, in the output regulation stage circuit, the gate of the PMOS power transistor M2 is connected to the output of AMP2, the source and substrate of M2 are connected to the voltage V2 terminal, and the drain of M2 is connected to the output voltage VOUT terminal. M2 is a power transistor, and the load current from VIN to VOUT will flow through M2.
Further, one end of the voltage dividing resistor R1 is connected to the VOUT terminal, the other end is connected to the positive input terminal V3 of the amplifier AMP2, one end of the voltage dividing resistor R2 is connected to the positive input terminal V3 of the amplifier AMP2, and the other end is grounded. By setting the voltage division ratio of R1 and R2, the output voltage value of VOUT can be set. The expression is VOUT = VREF (R1+ R2)/R2.
Further, an output load capacitor C2 of the linear regulator has one end connected to the output voltage VOUT and the other end connected to ground. The output load resistor Rload has one end connected to the output voltage VOUT and the other end connected to ground.
Further, the voltage V2 is the input voltage of the output regulation stage, and VOUT is the output voltage. Similar to the first input stage buffer stage, the power supply rejection ratio of the voltage V2 to VOUT is usually about 60dB at low frequency, and the high frequency power supply rejection ratio is about 20-30 dB at the same time.
Furthermore, in the overall structure, the input buffer stage circuit of the linear voltage stabilizing structure is added between the input VIN and the regulated voltage V2, so that the power supply rejection from VIN to VOUT is greatly improved compared with the traditional structure. With the structure, the power supply rejection ratio from VIN to VOUT can be about 90dB to 120dB at low frequency, and the power supply rejection ratio is improved to about 40dB to 60dB at high frequency. Compared with the traditional linear voltage regulator, the power supply rejection ratio is improved by about one time.
It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are merely illustrative of the principles of the invention, and that modifications and variations can be made by one skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. The low dropout linear regulator circuit with high power supply rejection ratio is characterized by comprising an input buffer stage circuit and an output regulation stage circuit, wherein the power supply of the input buffer stage circuit is connected with an input voltage VIN, the output end of the input buffer stage circuit is connected with the input end of the output regulation stage circuit, the output end of the output regulation stage circuit is connected with an output voltage VOUT, the input buffer stage circuit comprises an amplifier AMP1 and a power tube M1, the negative input end of the amplifier AMP1 is connected with a reference voltage V1, the positive input end of the amplifier AMP1 is connected with the output voltage V2 end of the input buffer stage circuit, the output end of the amplifier AMP1 is connected with the grid electrode of the power tube M1, the source electrode and the substrate of the power tube M1 are connected with the input voltage VIN, and the drain electrode of the power tube M1 is connected with the output voltage V2 end of the input buffer stage circuit.
2. The low dropout regulator circuit according to claim 1, wherein said output regulator stage circuit comprises an amplifier AMP2, a power transistor M2, voltage dividing proportional resistors R1 and R2, an output load capacitor C2, and an output load resistor Rload of the linear regulator, wherein a negative input terminal of said amplifier AMP2 is connected to a reference voltage VREF, a positive input terminal of said amplifier AMP2 is connected to an intermediate voltage V3 terminal, an output terminal of said amplifier AMP2 is connected to a gate of a power transistor M2, a source and a substrate of said power transistor M2 are connected to a voltage V2 terminal, a drain of said power transistor M2 is connected to an output voltage VOUT, a first terminal of said voltage dividing resistor R1 is connected to an output voltage VOUT, a second terminal of said voltage dividing resistor R1 is connected to an intermediate voltage V3 terminal, a first terminal of said voltage dividing resistor R2 is connected to an intermediate voltage V3 terminal, the second end of the voltage dividing resistor R2 is grounded, the first end of the output load capacitor C2 is connected with the output voltage VOUT, the second end of the output load capacitor C2 is grounded, the first end of the output load resistor Rload is connected with the output voltage VOUT, and the second end of the output load resistor Rload is grounded.
3. The low dropout regulator circuit according to claim 1, wherein said input buffer stage circuit further comprises a bypass capacitor C1, one end of said bypass capacitor C1 is connected to the output voltage V2 of said input buffer stage circuit, and the other end of said bypass capacitor C1 is grounded for discharging the high frequency noise signal of the output voltage V2 of said input buffer stage circuit to ground.
4. The low dropout regulator circuit of claim 1 wherein said amplifier AMP1 is connected in a negative feedback configuration to clamp the reference voltage V1 and the input buffer stage output voltage V2 to be equal, such that the input buffer stage output voltage V2 is equal to the voltage V1.
5. A high power supply rejection ratio low dropout linear regulator circuit as claimed in claim 2 wherein said amplifier AMP2 is connected in a negative feedback configuration clamping the reference voltage VREF together with the intermediate voltage V3.
6. The low dropout regulator circuit according to claim 1 or 2, wherein the power transistor M1 and the power transistor M2 are PMOS power transistors.
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| CN202110315254.2A CN113064460A (en) | 2021-03-24 | 2021-03-24 | Low dropout regulator circuit with high power supply rejection ratio |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114510109A (en) * | 2022-01-13 | 2022-05-17 | 电子科技大学 | high-PSR (power supply rejection) fast transient response dual-mode LDO (low dropout regulator) without off-chip capacitor |
| CN115268549A (en) * | 2022-09-28 | 2022-11-01 | 成都芯翼科技有限公司 | Circuit for reducing input-output voltage difference of LDO (low dropout regulator) and low dropout regulator |
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
| CN117234272A (en) * | 2023-11-16 | 2023-12-15 | 成都芯翼科技有限公司 | Noise reduction circuit and noise reduction method for low dropout linear voltage regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114510109A (en) * | 2022-01-13 | 2022-05-17 | 电子科技大学 | high-PSR (power supply rejection) fast transient response dual-mode LDO (low dropout regulator) without off-chip capacitor |
| CN115268549A (en) * | 2022-09-28 | 2022-11-01 | 成都芯翼科技有限公司 | Circuit for reducing input-output voltage difference of LDO (low dropout regulator) and low dropout regulator |
| CN115268549B (en) * | 2022-09-28 | 2023-01-17 | 成都芯翼科技有限公司 | Circuit for reducing input-output voltage difference of LDO (low dropout regulator) and low dropout regulator |
| CN116149419A (en) * | 2023-04-18 | 2023-05-23 | 泉芯电子技术(深圳)有限公司 | High power supply rejection ratio LDO circuit applicable to medium and high frequencies |
| CN117234272A (en) * | 2023-11-16 | 2023-12-15 | 成都芯翼科技有限公司 | Noise reduction circuit and noise reduction method for low dropout linear voltage regulator |
| CN117234272B (en) * | 2023-11-16 | 2024-01-30 | 成都芯翼科技有限公司 | Noise reduction circuit and noise reduction method for low dropout linear voltage regulator |
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Application publication date: 20210702 |