CN115097894B - High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor - Google Patents

High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor Download PDF

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CN115097894B
CN115097894B CN202210856009.7A CN202210856009A CN115097894B CN 115097894 B CN115097894 B CN 115097894B CN 202210856009 A CN202210856009 A CN 202210856009A CN 115097894 B CN115097894 B CN 115097894B
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power supply
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pull
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CN115097894A (en
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周波
郑恒
韩欣媛
李一凡
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Beijing Institute of Technology BIT
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention relates to a push-pull type LDO (low dropout regulator) with a high power supply rejection ratio and without an off-chip capacitor, and belongs to the technical field of power supply management. The push current mode LDO and the pull current mode LDO are combined into a whole, and the problem that the traditional LDO only has a push current mode is solved. The inclusion of a low gain fast loop with unity gain frequency exceeding 700MHz achieves high frequency power supply rejection ratio without the need for large off-chip capacitors of the μf stage. The framework has two working modes of push current and pull current; the output voltage of the push current mode is 1V, the linear adjustment rate is 0.12%/V, the load adjustment rate is 0.01mV/mA, and the power supply noise sensitive circuit can be driven; the output voltage of the pull current mode is 0.25V, the linear adjustment rate is 4.4%/V, the load adjustment rate is 0.025mV/mA, and the ground noise sensitive circuit can be driven; both modes of operation achieve a transient response below 6ns and a power supply rejection ratio below-10 dB in the frequency range 1Hz-1 GHz; and the full integration of the circuit is realized without an off-chip large capacitor.

Description

High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor
Technical Field
The invention relates to a push-pull type LDO (low dropout linear voltage regulator) with high power supply rejection ratio and without an off-chip capacitor, belonging to the technical field of power supply management.
Background
The LDO is used as a linear dc voltage regulator, and there is a minimum input voltage to ensure that the LDO maintains the output voltage within 100mV of its rated value, the voltage difference between the minimum input voltage and the rated output voltage is called a drop voltage, and the LDO can work normally only when the drop voltage must be greater than the saturation voltage of the power transistor, and the voltage fluctuation at the input terminal is attenuated and the regulated voltage is output.
The LDO function is mainly realized through a negative feedback control loop, a precise and stable reference voltage is generated by a reference voltage module, the change of output voltage is fed back to the input end of an error amplifier by a feedback network, the error amplifier amplifies the difference value between the feedback voltage and the reference voltage and outputs the difference value to the grid electrode of a power transistor, and the power transistor is driven to adjust the output current, so that the voltage output by the LDO is ensured to be stable in a rated value range.
LDOs typically use MOSFETs as power transistors, which are voltage driven and do not require current, thus greatly reducing the quiescent current consumed by the device itself. The voltage drop across the MOSFET is approximately equal to the product of the output current and the on-resistance, and because the on-resistance of the MOSFET is small, its saturation voltage is very small, and the LDO typically requires only about 200mV of voltage drop, which is much lower than about 2V of voltage drop required by conventional linear regulators. The smaller the quiescent current, the lower the drop voltage, the higher the switching efficiency of the LDO.
LDO plays an important role in the market by virtue of low cost, low voltage drop, low power consumption, low noise, simple structure and the like, and is widely applied to electronic equipment such as portable electronic equipment, communication systems, industrial equipment, medical equipment and the like which need stable power supply.
The power supply rejection ratio of the conventional LDO decreases with increasing operating frequency, so there is an upper limit to the operating frequency of circuits requiring high power supply rejection ratios. Common methods for enhancing the high-frequency power supply rejection ratio include external compensation capacitors, power tube substrate modulation technology and the like. The method of externally connecting the compensation capacitor with the chip generally needs a mu F-level capacitor, and the circuit cannot be fully integrated and applied to various miniature electronic devices, so that the method does not conform to the characteristic of increasingly miniaturized electronic devices. The power tube substrate modulation technology consumes a large amount of static current, greatly reduces the efficiency of the LDO, and is complex in circuit implementation. The traditional LDO has only a push current mode, can only be used for driving a load circuit sensitive to power supply noise, and cannot be used for driving a load circuit sensitive to ground noise.
Disclosure of Invention
The invention provides a push-pull type LDO (low dropout regulator) with a high power supply rejection ratio and without an off-chip capacitor, which aims to solve the problems that the traditional LDO needs an off-chip large capacitor to realize the high-frequency power supply rejection ratio and a load circuit sensitive to ground noise cannot be effectively driven.
The core idea of the invention is that: the power transistor, the common gate amplifier and the super source follower form a low-gain rapid loop, all nodes of the loop are low-impedance nodes, so that the stability of the loop can be ensured only by using an on-chip compensation capacitor of 220pF, the drain end of the power transistor is set as a main pole of the loop, and an off-chip large capacitor of mu F level is not needed; the low-gain fast loop has unit gain frequency exceeding 700MHz, has fast transient response speed, and can realize the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1 GHz; the common error amplifier EA, the alternative selector, the divider resistor and the inverter are used for combining the current pushing module and the current pulling module which are symmetrical in circuit structure and same in working principle, so that a load circuit sensitive to power supply noise and a load circuit sensitive to ground noise are effectively driven while not increasing too much static power consumption.
In order to achieve the above purpose, the technical implementation scheme of the invention is as follows:
the push-pull type LDO with the high power supply rejection ratio and the off-chip capacitor comprises an error amplifier EA, a selector, a compensation capacitor, a push current module, a pull current module, a divider resistor and an inverter;
the error amplifier EA adopts a differential-conversion single-folded cascode transconductance amplifier with an NMOS transistor as an input pair, provides high gain, attenuates power supply noise and ground noise to a certain extent, and outputs a relatively clean voltage to a rear-stage circuit;
the alternative selector comprises MUX-I, MUX-II and MUX-III, and is realized by adopting a digital logic circuit;
wherein the compensation capacitor comprises C P 、C N And C C A metal-insulator-metal capacitor is adopted;
the current pushing module comprises a PMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;
the current pulling module comprises an NMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;
wherein the voltage dividing resistor comprises R 1 And R is 2 A polysilicon resistor is adopted;
wherein the inverter is implemented using digital logic.
The connection relation of each module in the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio is as follows:
the output of the error amplifier EA is connected to MUX-I,channel 1 and C of MUX-I, respectively N And the pull current module is connected with the channel 0 of the MUX-I and the channel C respectively P The push current module is connected with C N Respectively connected with the channel 1 of the MUX-I and the power supply, C P Respectively connected with the channel 0 of the MUX-I and the ground, and the output ends of the pull current module and the push current module are connected with C C 、R 2 MUX-III is connected, C C Connected to MUX-II, channel 1 of MUX-II is connected to power supply, channel 0 of MUX-II is connected to ground, MUX-III is connected to R respectively 1 、R 2 And the inverting input end of the error amplifier EA is connected with the inverting input ends of the error amplifier EA, and the inverters are respectively connected with the MUX-I, MUX-II, the MUX-III, the push current module and the pull current module.
The functions of each module in the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio are as follows:
the function of the error amplifier EA is to amplify the reference voltage V REF And feedback voltage V F The difference value is output to a post-stage circuit to feed back the voltage V F Clamped at reference voltage V REF Near, high gain is provided, good linear adjustment rate and load adjustment rate are realized, and the low-frequency power supply rejection ratio is enhanced;
the function of the alternative selector is that the selection circuit works in a push current mode or a pull current mode;
the compensation capacitor has the functions of compensating the phase margin of each loop in the circuit and enhancing the stability of the system;
the current pushing module has the functions of providing a low-gain rapid loop, realizing rapid transient response and enhanced high-frequency power supply rejection ratio and outputting a clean voltage referenced to the ground;
the current drawing module has the functions of providing a low-gain rapid loop, realizing rapid transient response and enhanced high-frequency power supply rejection ratio, and outputting clean voltage of a reference power supply;
the voltage dividing resistor is connected in series between the output and the power supply to realize voltage division, and provides different output voltage values for a pull current mode and a push current mode;
the function of the inverter is to output an AND S M Voltage S of opposite level MN For controllingAnd partial transistor switches in the push current module and the pull current module are opened or closed.
The working process of the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio comprises the following steps:
step one, selecting an operation mode of the LDO, which specifically comprises the following sub-steps:
step 1.1 input a low/high control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
step 1.2 Low level/high level control Signal S M Outputs a high level/low level control signal S through an inverter MN ；
Step 1.3 high level control Signal S M And a low level control signal S MN Control signal S for controlling the push current module to work and the pull current module to be not work/low level M And a high level control signal S MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together;
at this time, the LDO operates in a push current mode/a pull current mode;
step two, stabilizing the output voltage at the rated value of the corresponding working mode, which comprises the following steps:
step 2.1 error amplifier EA amplifies reference voltage V REF And feedback voltage V F The difference value of the current is output to a push current module/a pull current module;
step 2.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
step 2.3, feeding back the output voltage regulated by the current pushing module/current pulling module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the steps 2.1, 2.2 and 2.3 in the step two are repeated until the output voltage is stabilized at the rated value of the corresponding working mode;
step three, rapidly responding to alternating current small signal fluctuation of output voltage, realizing power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz, and specifically comprising the following substeps:
step 3.1, when alternating current small signal fluctuation occurs at the power supply/ground end and the output voltage has alternating current small signal fluctuation, an error alternating voltage is generated at the drain end of the common grid amplifier in the push current module/pull current module;
step 3.2, transmitting error alternating voltage generated at the drain end of the common gate amplifier to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;
step 3.3 Gate Voltage variation of PMOS Power transistor/NMOS Power transistor leading to V GS The power transistor adjusts the change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
the push current module/pull current module is internally provided with a low-gain quick loop formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower, all nodes of the loop are low-resistance points and have very high unit gain frequency, the 3 steps can be responded quickly, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized under the condition that a mu F-level off-chip large capacitor is not needed.
Advantageous effects
Compared with the traditional LDO, the push-pull type LDO with high power supply rejection ratio and no off-chip capacitor has the following beneficial effects:
1. introducing a low-gain fast loop, and realizing fast transient response with response time lower than 6ns and power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz under the condition of not needing a mu F-level off-chip large capacitor;
2. the error amplifier adopts a differential-conversion single-folded cascode transconductance amplifier with an NMOS transistor as an input pair, provides high gain, realizes better linear adjustment rate and load adjustment rate, and enhances the low-frequency power supply rejection ratio;
3. the push current mode and the pull current mode are combined together through the common error amplifier EA, the alternative selector, the divider resistor and the inverter, so that the power supply noise sensitive circuit and the ground noise sensitive circuit can be driven, and the problem that the traditional LDO cannot drive the ground noise sensitive circuit is solved while excessive quiescent current is not increased;
4. and a mu F-level off-chip large capacitor is not needed, so that the full integration of the circuit is realized, and the cost is saved.
Drawings
FIG. 1 is a schematic diagram of a high power rejection ratio push-to-current mode circuit of a push-to-pull LDO without an off-chip capacitor;
FIG. 2 is a block diagram of a pull-current mode circuit of a high power supply rejection ratio, off-chip capacitor free push-pull LDO of the present invention;
FIG. 3 is a block diagram of the overall circuit of a high power rejection ratio, off-chip capacitor free push-pull LDO of the present invention;
FIG. 4 is a diagram showing the power rejection ratio of the push-current mode of a push-pull LDO without an off-chip capacitor with high power rejection ratio according to the present invention;
FIG. 5 is a diagram showing the power rejection ratio of the pull-current mode of a high power rejection ratio, off-chip capacitor free push-pull LDO according to the present invention;
FIG. 6 is a graph of the load transient response of a high supply rejection ratio, off-chip capacitor free push-pull LDO of the present invention;
FIG. 7 is a graph of the linear adjustment rate of the push current mode of a push-pull LDO without an off-chip capacitor with high power supply rejection ratio according to the present invention;
FIG. 8 is a graph of the linear adjustment rate of the pull-current mode of a high power supply rejection ratio, off-chip capacitor free push-pull LDO of the present invention;
FIG. 9 is a graph of the load regulation of a high power rejection ratio, off-chip capacitor free push-pull LDO of the present invention;
Detailed Description
The following describes the circuit modules and the working process of the push-pull LDO depending system without the on-chip capacitor with high power supply rejection ratio in detail by combining the embodiment with the attached drawings.
Example 1
The working process of the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio is as follows:
step A, selecting an LDO working mode, which specifically comprises the following sub-steps:
step A.1 inputs a low level/high level control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
in particular, in the present embodiment, the high level control signal S is input M 1.25V, low level control signal S M Is 0;
step A.2 Low/high control Signal S M Outputs a high level/low level control signal S through an inverter MN ；
In particular, in the present embodiment, the inverter outputs the high level control signal S MN 1.25V, low level control signal S MN Is 0;
step A.3 high level control Signal S M And a low level control signal S MN Control signal S for controlling the push current module to work and the pull current module to be not work/low level M And a high level control signal S MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together;
at this time, the LDO operates in a push current mode/a pull current mode;
in particular, in this embodiment, a load circuit in a push current mode of the LDO is connected between the output terminal and ground, and a load circuit in a pull current mode is connected between the output terminal and the power supply;
and B, stabilizing the output voltage at a rated value corresponding to the working mode, wherein the method specifically comprises the following substeps:
step B.1 error amplifier EA amplifies reference voltage V REF And feedback voltage V F The difference value of the current is output to a push current module/a pull current module;
in particular to the present embodiment, reference voltage V REF 1V;
step B.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
in particular, in the present embodiment, the output voltage of the push current mode is 1V, the output voltage of the pull current mode is 0.25V, and different output voltages pass through the voltage dividing resistor R 1 And R is R 2 The serial connection is realized;
step B.3, feeding back the output voltage regulated by the current pushing module/current pulling module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the steps B.1, B.2 and B.3 in the step B are repeated until the output voltage is stabilized at the rated value;
specifically, in this embodiment, the rated output voltage of the push current mode is 1V, and the rated output voltage of the pull current mode is 0.25V;
and C, rapidly responding to alternating current small signal fluctuation of output voltage to realize a power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz, wherein the method specifically comprises the following substeps:
step C.1, when alternating current small signal fluctuation occurs at the power supply/ground end to cause alternating current small signal fluctuation of output voltage, error alternating voltage is generated at the drain end of the common grid amplifier in the push current module/pull current module;
specifically, in this embodiment, an ac small signal with a peak value of 50mV is input at the power supply terminal in the current pushing mode, and an ac small signal with a peak value of 50mV is input at the ground terminal in the current pulling mode;
c.2, transmitting error alternating voltage generated at the drain end of the common gate amplifier to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;
step C.3 Gate Voltage variation of PMOS Power transistor/NMOS Power transistor leading to V GS The power transistor adjusts the change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
the inside of the current pushing module/current pulling module is provided with a low-gain quick loop formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower, all nodes of the loop are low-resistance points and have very high unit gain frequency, the 3 steps can be responded quickly, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized under the condition that a mu F-level off-chip large capacitor is not needed;
specifically to this embodiment, the unity gain frequency of the push/pull current mode of the LDO is 700MHz/750MHz, and both modes of operation achieve a transient response below 6ns and a power supply rejection ratio below-10 dB in the 1Hz-1GHz frequency range.
Example 2
The push-current mode schematic diagram of the push-pull LDO without the off-chip capacitor with high power supply rejection ratio is shown in fig. 1, wherein a loop-I is a low-gain fast loop formed by a PMOS power transistor, a common gate amplifier and a buffer, has unit gain frequency exceeding 700MHz, and can realize ultra-fast transient response and enhanced high-frequency power supply rejection ratio. When the alternating current small signal fluctuation occurs at the power supply end to cause the alternating current small signal fluctuation of the output voltage, an error alternating current voltage is generated at the drain end of the common gate amplifier, the error alternating current voltage is transmitted to the grid electrode of the PMOS power transistor after passing through the buffer, and the grid voltage change of the PMOS power transistor causes V GS And the change of the load current is regulated to resist the fluctuation of the output voltage, so that a better high-frequency power supply rejection ratio is realized. To ensure loop-I stability, a 220pF capacitor C is required C The main pole is set at the drain of the PMOS power transistor. The loop-II is a high-gain slow loop, which enhances the load adjustment rate, the linear adjustment rate and the low-frequency power supply rejection ratio of the LDO. To ensure loop-II stability, a 1.5pF compensation capacitor C is connected between the output of the error amplifier and ground P . The output voltage of the push current mode is 1V. In the current pushing mode, the load circuit is connected between the output end of the LDO and the ground, so that the influence of small signal voltage fluctuation of the power end on the output can be effectively reduced, and a clean driving voltage is provided for the load circuit.
The pull-current mode working principle diagram of the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio is shown in fig. 2, and the pull-current mode working principle is the same as that of the push-current mode, and also has a low-gain fast loop-I and a high-gain slow loop-II. To ensure loop-I stability, a 220pF capacitor C is required C The main pole is set at the drain of the NMOS power transistor. For the purpose ofEnsuring loop-II stability requires a 1pF compensation capacitor C between the output of the error amplifier and the power supply N . The output voltage of the pull-current mode is 0.25V. The load circuit is connected between the output end of the LDO and the power supply in the current pulling mode, so that the influence of small signal voltage fluctuation at the ground end on output can be effectively reduced, and a clean driving voltage is provided for the load circuit.
The overall circuit of the high-power supply rejection ratio off-chip-capacitor-free push-pull LDO is shown in FIG. 3, in which the push-current mode and the pull-current mode share an error amplifier EA, an inverter, one-out-of-two selectors MUX-I-MUX-III and a compensation capacitor C of 220pF C By control signal S M And S is MN One-for-two selector MUX-I, MUX-II, MUX-III and transistor switch M 11 、M 16 、M 19 、M 23 、M 25 、M 28 The control of (1) selects the working mode of LDO, when the current pushing module works, the current pulling module is closed, and when the current pulling module works, the current pushing module is closed, so that the consumed quiescent current is reduced. Through a voltage dividing resistor R 1 And R is 2 And the series connection is used for realizing different operating modes to output different voltages.
Fig. 4 and 5 show the power supply rejection ratio of LDO push current mode and pull current mode, respectively. When the device works in a push current mode, the low-frequency power supply rejection ratio is smaller than-58 dB, the power supply rejection ratio in the frequency range of 1Hz-1GHz is smaller than-10 dB, and the power supply rejection ratio at 1GHz is smaller than-15 dB. When the device works in a current pulling mode, the low-frequency power supply rejection ratio is smaller than-39 dB, the power supply rejection ratio in a frequency range of 1Hz-1GHz is smaller than-10 dB, and the power supply rejection ratio at 1GHz is smaller than-12 dB.
As shown in FIG. 6, the transient response of the LDO load is that the load current jumps between 10 mu A and 20mA, the rising/falling time is 6ns, the up-rush voltage of the push current mode is 31mV, and the down-rush voltage is 36mV; the pull-up current mode has an overshoot voltage of 43mV and an undershoot voltage of 39mV.
FIGS. 7 and 8 show the linear adjustment rates of the push current mode and the pull current mode of the LDO, respectively, wherein the rated output voltage of the push current mode is 1V, the output voltage variation amplitude is less than 0.12mV when a ripple wave with a peak value of 50mV is input at the power supply end, and the linear adjustment rate is 0.12%/V; the rated output voltage of the pull current mode is 0.25V, when the ripple wave with the peak value of 50mV is input at the ground terminal, the output voltage change amplitude is smaller than 1.1mV, and the linear adjustment rate is 4.4%/V.
As shown in FIG. 9, when the load current changes between 10 μA and 20mA, the output voltage change amplitude of the push current mode is smaller than 0.2mV, and the load change rate is 0.01mV/mA; the output voltage variation amplitude of the pull current mode is smaller than 0.5mV, and the load variation rate is 0.025mV/mA.
The foregoing is a preferred embodiment of the present invention, and the present invention should not be limited to the embodiment and the disclosure of the drawings. All equivalents and modifications that come within the spirit of the disclosure are desired to be protected.

Claims (5)

1. A push-pull LDO with high power supply rejection ratio and no off-chip capacitor comprises a push current mode and a pull current mode; the method is characterized in that: the circuit structure comprises: the error amplifier EA, the alternative selector, the compensation capacitor, the push current module, the pull current module, the divider resistor and the inverter;
wherein, the error amplifier EA, the alternative selector, the divider resistor and the inverter are shared by a push current mode and a pull current mode;
the alternative selector comprises MUX-I, MUX-II and MUX-III;
the compensation capacitor comprises C P 、C N C C ；
The voltage dividing resistor comprises R 1 R is as follows 2 ；
The current pushing module comprises a PMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;
the current pulling module comprises an NMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;
the connection relation of each module in the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio is as follows:
the output of the error amplifier EA is connected to MUX-I, channel 1 of MUX-I being simultaneously connected to C N M is as follows 27 Is connected to the gate of MUX-I channel 0 and C at the same time P M is as follows 17 Is connected with the grid electrode of C N Is connected with a power supply, C P Connected with the ground, the output end of the current pushing module is connected with C at the same time C The output end of the pull current module, R2 and the channel 0 of the MUX-III are connected, C C Connected to MUX-II, channel 1 of MUX-II is connected to a power supply, channel 0 of MUX-II is connected to ground, and channel 1 of MUX-III is simultaneously connected to R 1 R is as follows 2 Connected to M in the error amplifier EA and MUX-III 2 Is connected with the grid electrode of the phase inverter and is simultaneously connected with M 11 Gate, M of (2) 16 Gate, M of (2) 23 Gate, M of (2) 28 The grid electrode of the (D), the MUX-I, MUX-II and the MUX-III are connected, and the output end of the inverter is simultaneously connected with M 19 Gate of (c) and M 25 R2 is connected with a power supply;
the working process of the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio comprises the following steps:
step one, selecting an operation mode of the LDO, which specifically comprises the following sub-steps:
step 1.1 input a low/high control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
step 1.2 Low level/high level control Signal S M Outputs a high level/low level control signal S through an inverter MN ；
Step 1.3 high level control Signal S M And a low level control signal S MN Control signal S for controlling the push current module to work and the pull current module to be not work/low level M And a high level control signal S MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together;
at this time, the LDO operates in a push current mode/a pull current mode;
step two, stabilizing the output voltage at the rated value of the corresponding working mode, which comprises the following steps:
step 2.1 error amplificationThe reference voltage V is amplified by the EA REF And feedback voltage V F The difference value of the current is output to a push current module/a pull current module;
step 2.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
step 2.3, feeding back the output voltage regulated by the current pushing module/current pulling module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the steps 2.1, 2.2 and 2.3 in the step two are repeated until the output voltage is stabilized at the rated value of the corresponding working mode;
step three, rapidly responding to alternating current small signal fluctuation of output voltage, realizing power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz, and specifically comprising the following substeps:
step 3.1, when alternating current small signal fluctuation occurs at the power supply/ground end and the output voltage has alternating current small signal fluctuation, an error alternating voltage is generated at the drain end of the common grid amplifier in the push current module/pull current module;
step 3.2, transmitting error alternating voltage generated at the drain end of the common gate amplifier to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;
step 3.3 Gate Voltage variation of PMOS Power transistor/NMOS Power transistor leading to V GS The power transistor adjusts the change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
the push current module/pull current module is internally provided with a low-gain fast loop formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower, all nodes of the loop are low-resistance points and have unit gain frequency exceeding 700MHz, transient response lower than 6ns can be realized, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized under the condition that a mu F-level off-chip large capacitor is not needed.
2. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the push current module/pull current module is internally provided with a low-gain and rapid loop formed by a power transistor, a common gate amplifier and a super source follower, the loop has a unit gain frequency exceeding 700MHz, and the transient response of less than 6ns and the power supply rejection ratio of less than-10 dB in the frequency range of 1Hz-1GHz can be realized.
3. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the push current module/pull current module is internally provided with a low-gain and rapid loop formed by a power transistor, a common gate amplifier and a super source follower, all nodes of the loop are low-resistance points, and only the drain end of the power transistor is connected with an on-chip compensation capacitor C of 220pF C To ensure loop stability without the need for large off-chip capacitors.
4. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the LDO is provided with a push current mode and a pull current mode, wherein the push current mode is used for driving a power supply noise sensitive circuit, and a load circuit is connected between the output and the ground; the pull current mode is used for driving a ground noise sensitive circuit, and a load circuit is connected between the output and a power supply.
5. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: high level control signal S M And a low level control signal S MN The current pushing module is controlled to work together, the current pulling module is not operated, and the LDO works in a current pushing mode; low level control signal S M And a high level control signal S MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together, and the LDO is operated in a current pulling mode.
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