CN115097894B - High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor - Google Patents

Abstract

The invention relates to a push-pull LDO with high power supply rejection ratio and no external capacitor, which belongs to the technical field of power supply management. Combining the push current mode LDO and the pull current mode LDO into one solves the problem that the traditional LDO only has the push current mode. Contains a low-gain fast loop with a unity-gain frequency in excess of 700MHz, enabling high-frequency power-supply rejection ratios without the need for off-chip bulk capacitors in the µF range. The architecture has two working modes: push current and pull current; the output voltage of the push current mode is 1V, the linear regulation rate is 0.12%/V, and the load regulation rate is 0.01mV/mA, which can drive power supply noise sensitive circuits; the pull current mode The output voltage is 0.25V, the linear regulation rate is 4.4%/V, and the load regulation rate is 0.025mV/mA, which can drive ground noise sensitive circuits; both operating modes achieve a transient response below 6ns and a frequency range of 1Hz‑1GHz The internal power supply rejection ratio is lower than ‑10dB; no large off-chip capacitors are required to achieve full circuit integration.

Description

A Push-Pull LDO with High Power Supply Rejection Ratio and No Off-Chip Capacitor

technical field

The invention relates to a push-pull LDO (low-dropout linear regulator) with high power supply rejection ratio and no external capacitor, belonging to the technical field of power supply management.

Background technique

As a linear DC voltage regulator, LDO has a minimum input voltage to ensure that the LDO maintains the output voltage within 100mV of its rated value. The voltage difference between the minimum input voltage and the rated output voltage is called dropout voltage, dropout voltage The LDO can work normally when it must be greater than the saturation voltage of the power transistor, attenuate the voltage fluctuation at the input terminal and output a regulated stable voltage.

The function of the LDO is mainly realized through the negative feedback control loop. The reference voltage module generates an accurate and stable reference voltage. The feedback network feeds back the change of the output voltage to the input terminal of the error amplifier. The error amplifier amplifies the difference between the feedback voltage and the reference voltage. The value is output to the gate of the power transistor, and the power transistor is driven to adjust the output current to ensure that the voltage output by the LDO is stable within the rated value range.

LDOs usually use MOSFETs as power transistors. MOSFETs are voltage-driven and do not require current, so the quiescent current consumed by the device itself is greatly reduced. The voltage drop on the MOSFET is roughly equal to the product of the output current and the on-resistance. Since the on-resistance of the MOSFET is very small, its saturation voltage is very small. LDO usually only needs a voltage drop of about 200mV, which is much lower than that of traditional linear regulators. The drop voltage of about 2V required by the voltage regulator. The smaller the quiescent current and the lower the voltage drop, the higher the conversion efficiency of the LDO.

With the advantages of low cost, low voltage drop, low power consumption, low noise and simple structure, LDO occupies an important position in the market, and is widely used in portable electronic equipment, communication systems, industrial equipment, medical equipment and other electronic equipment that require stable power supply.

The power supply rejection ratio of a traditional LDO decreases as the operating frequency increases, so there is an upper limit to the operating frequency of circuits that require a high power supply rejection ratio. Commonly used methods to enhance the high-frequency power supply rejection ratio include off-chip compensation capacitors and power tube substrate modulation techniques. The method of connecting compensation capacitors outside the chip usually requires a μF capacitor, and the circuit cannot be fully integrated and cannot be used in various microelectronic devices, which does not meet the characteristics of the increasingly miniaturized electronic devices. The power tube substrate modulation technology needs to consume a large amount of quiescent current, which will greatly reduce the efficiency of the LDO, and the circuit implementation is complicated. Traditional LDOs only have push current mode, which can only be used to drive load circuits that are sensitive to power supply noise, and cannot be used to drive load circuits that are sensitive to ground noise.

Contents of the invention

The present invention proposes a push-pull LDO without off-chip capacitors with high power supply rejection ratio, aiming to solve the problem that traditional LDOs need large off-chip capacitors to achieve high-frequency power supply rejection ratio and cannot effectively drive load circuits sensitive to ground noise The problem.

The core idea of the present invention is: a low-gain fast loop is formed by a power transistor, a common gate amplifier and a super source follower, and all nodes of the loop are low-impedance nodes, so only a 220pF on-chip compensation capacitor is needed The stability of the loop can be guaranteed, and the drain terminal of the power transistor is set as the main pole of the loop, which does not require a large off-chip capacitor of the μF level; the low-gain fast loop has a unity gain frequency of more than 700MHz, and has a very fast instantaneous State response speed, can achieve a power supply rejection ratio lower than -10dB in the frequency range of 1Hz-1GHz; by sharing the error amplifier EA, one-two selector, voltage divider resistor and inverter, the circuit structure is symmetrical and the working principle is the same The combination of the push current module and the current pull module can effectively drive the load circuit sensitive to power supply noise and the load circuit sensitive to ground noise without increasing too much static power consumption.

To achieve the above object, the technical implementation scheme of the present invention is as follows:

The push-pull LDO with no off-chip capacitor with a high power supply rejection ratio includes an error amplifier EA, a selector, a compensation capacitor, a push current module, a pull current module, a voltage divider resistor and an inverter;

Among them, the error amplifier EA uses NMOS transistors as the input pair of differential-turn single-fold cascode transconductance amplifiers to provide high gain, and at the same time attenuate the power supply noise and ground noise to a certain extent, and output a relatively clean voltage;

Among them, the two-choice selector includes MUX-I, MUX-II, and MUX-III, which are realized by digital logic circuits;

Among them, the compensation capacitor includes C _P , C _N and C _C , and adopts metal-insulator-metal capacitance;

Among them, the current pushing module includes PMOS power transistor, common gate amplifier, super source follower, MOS transistor switch and current mirror;

Among them, the current source module includes NMOS power transistor, common gate amplifier, super source follower, MOS transistor switch and current mirror;

Wherein, the voltage dividing resistors include R ₁ and R ₂ , and polysilicon resistors are used;

Wherein, the inverter is realized by a digital logic circuit.

The connection relationship of each module in the push-pull LDO without off-chip capacitor with high power supply rejection ratio is as follows:

The output terminal of the error amplifier EA is connected to MUX-I, _{the channel 1 of MUX-I is connected to CN and the pull current module respectively, the channel 0 of MUX-I is connected to C P and} the current pushing module respectively, and _CN is connected to MUX- Channel 1 of I is connected to the power supply, C _P is connected to channel 0 of MUX-I and the ground respectively, the output terminals of the current pulling module and the current pushing module are connected to C _C , R ₂ and MUX-III, and C _C is connected to MUX-II Connected, channel 1 of MUX-II is connected to the power supply, channel 0 of MUX-II is connected to the ground, MUX-III is connected to R ₁ , R ₂ and the inverting input of the error amplifier EA respectively, and the inverters are respectively connected to MUX- I, MUX-II, MUX-III, the push current module and the pull current module are connected.

The functions of each module in the push-pull LDO without off-chip capacitors with high power supply rejection ratio are as follows:

The function of the error amplifier EA is to amplify the difference between the reference voltage V _REF and the feedback voltage V _F and output it to the subsequent circuit, clamp the feedback voltage V _F near the reference voltage V _REF , provide high gain, and achieve better Linear adjustment rate and load adjustment rate, enhanced low-frequency power supply rejection ratio;

The function of the two-choice selector is to select the circuit to work in the push current mode or the pull current mode;

The function of the compensation capacitor is to compensate the phase margin of each loop in the circuit and enhance the stability of the system;

The function of the push current module is to provide a low-gain fast loop to achieve fast transient response and enhanced high-frequency power supply rejection ratio, and output a clean voltage referenced to ground;

The function of the current source module is to provide a low-gain fast loop to achieve fast transient response and enhanced high-frequency power supply rejection ratio, and output a clean voltage of the reference power supply;

The function of the voltage divider resistor is to divide the voltage between the output and the power supply in series, and provide different output voltage values for the pull current mode and the push current mode;

The function of the inverter is to output a voltage S _MN with an opposite level to S _M , which is used to control some transistor switches in the current pushing module and the current pulling module to turn on or off.

The working process of the push-pull LDO without off-chip capacitor with high power supply rejection ratio specifically includes the following steps:

Step 1. Select the working mode of the LDO, which specifically includes the following sub-steps:

Step 1.1 Input a low level/high level control signal S _M , MUX-I, MUX-II and MUX-III all select channel 0/channel 1;

Step 1.2 The low-level/high-level control signal S _M outputs a high-level/low-level control signal S _MN through the inverter;

Step 1.3 The high-level control signal S _M and the low-level control signal S _MN jointly control the push current module to work and the pull current module does not work / the low-level control signal S _M and the high-level control signal S _MN jointly control the push current module does not work and the current source module works;

At this time, the LDO works in the push current mode/source current mode;

Step 2. Stabilize the output voltage at the rated value corresponding to the working mode, specifically including the following sub-steps:

Step 2.1 The error amplifier EA amplifies the difference between the reference voltage V _REF and the feedback voltage V _F and outputs it to the current push module/current pull module;

Step 2.2 The current push module/current pull module adjusts its own output voltage according to the amplification difference provided by the error amplifier EA;

Step 2.3 Feedback the adjusted output voltage of the push current module/source current module to the inverting input terminal of the error amplifier EA;

The error amplifier EA and the push current module/pull current module form a negative feedback loop, and repeat the steps 2.1, 2.2 and 2.3 in the above step 2 until the output voltage stabilizes at the rated value of the corresponding working mode;

Step 3. Quickly respond to the AC small signal fluctuation of the output voltage, and realize the power supply rejection ratio lower than -10dB in the frequency range of 1Hz-1GHz, specifically including the following sub-steps:

Step 3.1 When small AC signal fluctuations occur at the power supply/ground terminal, resulting in small AC signal fluctuations in the output voltage, an error AC voltage will be generated at the drain of the common-gate amplifier inside the push current module/current pull module;

Step 3.2 The error AC voltage generated at the drain terminal of the common gate amplifier is passed to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;

Step 3.3 Changes in the gate voltage of the PMOS power transistor/NMOS power transistor lead to changes in V _GS , and the power transistor adjusts the change in load current to resist output voltage fluctuations and stabilize the output voltage;

The current push module/current pull module consists of a PMOS power transistor/NMOS power transistor, a common gate amplifier and a super source follower to form a low-gain fast loop. All nodes of the loop are low-resistance points and have a high Unity gain frequency can quickly respond to the above three steps, and achieve a power supply rejection ratio lower than -10dB in the frequency range of 1Hz-1GHz without the need for large off-chip capacitors of μF level.

Beneficial effect

A push-pull LDO with no off-chip capacitor with high power supply rejection ratio, compared with traditional LDO, has the following beneficial effects:

1. Introduce a low-gain fast loop to achieve a fast transient response with a response time of less than 6ns and a power supply rejection ratio of less than -10dB in the frequency range of 1Hz-1GHz without the need for large off-chip capacitors of μF level;

2. The error amplifier uses NMOS transistors as the input pair of differential-turn single-fold cascode transconductance amplifiers to provide high gain, achieve better linear regulation and load regulation, and enhance the low-frequency power supply rejection ratio;

3. By sharing the error amplifier EA, the one-of-two selector, the voltage divider resistor and the inverter, the push current mode and the pull current mode are combined to realize the ability to drive circuits sensitive to power supply noise and ground noise Sensitive circuits solve the problem that traditional LDOs cannot drive circuits sensitive to ground noise without increasing excessive quiescent current;

4. There is no need for large off-chip capacitors of μF level, which realizes full circuit integration and saves costs.

Description of drawings

Fig. 1 is the push-current mode circuit structure diagram of the push-pull type LDO of the push-pull type LDO of a kind of high power supply rejection ratio of the present invention without off-chip;

Fig. 2 is a drawing current mode circuit structure diagram of a push-pull type LDO without off-chip capacitor with high power supply rejection ratio of the present invention;

Fig. 3 is the overall circuit structure diagram of the push-pull type LDO without off-chip capacitance of a kind of high power supply rejection ratio of the present invention;

Fig. 4 is the power supply rejection ratio figure of the push-pull type LDO of the push-pull type LDO of a kind of high power supply rejection ratio of the present invention without off-chip capacitor;

Fig. 5 is the power supply rejection ratio figure of the pulling current mode of the push-pull type LDO of the push-pull type LDO without off-chip capacitor of a kind of high power supply rejection ratio of the present invention;

Fig. 6 is a load transient response diagram of a push-pull LDO without off-chip capacitor with high power supply rejection ratio of the present invention;

Fig. 7 is the linear adjustment rate diagram of the push current mode of a push-pull LDO without off-chip capacitor with high power supply rejection ratio of the present invention;

Fig. 8 is a linear adjustment rate diagram of a pull current mode of a push-pull LDO without an off-chip capacitor with a high power supply rejection ratio of the present invention;

Fig. 9 is a load regulation diagram of a push-pull LDO without off-chip capacitor with high power supply rejection ratio of the present invention;

Detailed ways

The circuit modules and working process of a push-pull LDO-based system with high power supply rejection ratio and no off-chip capacitor according to the present invention will be further explained and described in detail below in conjunction with the embodiments and accompanying drawings.

Example 1

The working process of the push-pull LDO without off-chip capacitor with high power supply rejection ratio is as follows:

Step A, select the working mode of LDO, specifically include the following sub-steps:

Step A.1 Input a low level/high level control signal S _M , MUX-I, MUX-II and MUX-III all select channel 0/channel 1;

Specifically in this embodiment, the input high-level control signal S _M is 1.25V, and the low-level control signal S _M is 0;

Step A.2 The low-level/high-level control signal S _M outputs a high-level/low-level control signal S _MN through the inverter;

Specifically in this embodiment, the high-level control signal S _MN output by the inverter is 1.25V, and the low-level control signal S _MN is 0;

Step A.3 The high-level control signal S _M and the low-level control signal S _MN jointly control the push current module to work and the pull current module does not work / the low-level control signal S _M and the high-level control signal S _MN jointly control the push The current module does not work and the source module works;

At this time, the LDO works in the push current mode/source current mode;

Specifically in this embodiment, the load circuit of the push current mode of the LDO is connected between the output terminal and the ground, and the load circuit of the pull current mode is connected between the output terminal and the power supply;

Step B. Stabilize the output voltage at the rated value corresponding to the working mode, specifically including the following sub-steps:

Step B.1 The error amplifier EA amplifies the difference between the reference voltage V _REF and the feedback voltage V _F and outputs it to the push current module/source current module;

Specifically in this embodiment, the reference voltage V _REF is 1V;

Step B.2 The current pushing module/current pulling module adjusts its own output voltage according to the amplification difference provided by the error amplifier EA;

Specifically in this embodiment, the output voltage of the push current mode is 1V, and the output voltage of the pull current mode is 0.25V, and different output voltages are realized by connecting the voltage dividing resistors _R1 and _{R2 in} series;

Step B.3 feeds back the adjusted output voltage of the push current module/source current module to the inverting input terminal of the error amplifier EA;

The error amplifier EA and the current push module/current pull module form a negative feedback loop, and repeat the steps B.1, B.2 and B.3 in the above step B until the output voltage stabilizes at the rated value;

Specifically in this embodiment, the rated output voltage of the push current mode is 1V, and the rated output voltage of the pull current mode is 0.25V;

Step C, quickly responding to the AC small signal fluctuation of the output voltage, and realizing a power supply rejection ratio lower than -10dB in the frequency range of 1Hz-1GHz, specifically includes the following sub-steps:

Step C.1 When small AC signal fluctuations occur at the power supply/ground terminal, resulting in small AC signal fluctuations in the output voltage, an error AC voltage will be generated at the drain of the common-gate amplifier inside the push current module/current pull module;

Specifically in this embodiment, a small AC signal with a peak value of 50mV is input at the power supply terminal in the push current mode, and a small AC signal with a peak value of 50mV is input at the ground terminal in the pull current mode;

In step C.2, the error AC voltage generated at the drain terminal of the common gate amplifier is transferred to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;

Step C.3 Changes in the gate voltage of the PMOS power transistor/NMOS power transistor lead to changes in V _GS , and the power transistor adjusts the change in load current to resist output voltage fluctuations and stabilize the output voltage;

The current push module/current pull module is composed of PMOS power transistor/NMOS power transistor, common gate amplifier and super source follower to form a low-gain fast loop. All nodes of the loop are low-resistance points and have high Unity gain frequency, can quickly respond to the above three steps, and achieve a power supply rejection ratio lower than -10dB in the frequency range of 1Hz-1GHz without the need for large off-chip capacitors of μF level;

Specifically in this embodiment, the unity gain frequency of the push current mode/source current mode of the LDO is 700MHz/750MHz, and both operating modes have achieved a transient response lower than 6ns and a frequency lower than -10dB in the 1Hz-1GHz frequency range. power supply rejection ratio.

Example 2

The push-current mode schematic diagram of the push-pull LDO of the described a kind of high power supply rejection ratio without off-chip capacitor is as shown in Figure 1, loop-I is made of PMOS power transistor, common gate amplifier and buffer among the figure A low-gain fast loop with a unity-gain frequency in excess of 700MHz enables ultrafast transient response and enhanced high frequency power supply rejection. When small AC signal fluctuations occur at the power supply end, resulting in small AC signal fluctuations in the output voltage, an error AC voltage will be generated at the drain of the common gate amplifier, and the error AC voltage will be transmitted to the gate of the PMOS power transistor after passing through the buffer. The change of the gate voltage of the power transistor leads to the change of V _GS , and the change of the load current is adjusted to resist the fluctuation of the output voltage, so as to achieve a better high-frequency power supply rejection ratio. To ensure loop-I stability, a 220pF capacitor _CC is used to set the dominant pole at the drain of the PMOS power transistor. Loop-II is a high-gain slow loop that enhances the LDO's load regulation, line regulation, and low-frequency power supply rejection. In order to ensure the stability of loop-II, a compensation capacitor C _P of 1.5pF needs to be connected between the output terminal of the error amplifier and ground. The output voltage in push current mode is 1V. In push current mode, the load circuit is connected between the output terminal of the LDO and the ground, which can effectively reduce the influence of small signal voltage fluctuations at the power supply terminal on the output, and provide a clean driving voltage for the load circuit.

The working principle diagram of the pull-current mode of the push-pull LDO without off-chip capacitor with high power supply rejection ratio is shown in Figure 2. The working principle of the pull-current mode is the same as that of the push-current mode, and there is also a low-gain fast loop -I and high gain slow loop -II. To ensure loop-I stability, a 220pF capacitor C _C is required to set the dominant pole at the drain of the NMOS power transistor. In order to ensure the stability of loop-II, a 1pF compensation capacitor C _N needs to be connected between the output terminal of the error amplifier and the power supply. The output voltage in source mode is 0.25V. In the current source mode, the load circuit is connected between the output terminal of the LDO and the power supply, which can effectively reduce the influence of small signal voltage fluctuations at the ground terminal on the output, and provide a clean driving voltage for the load circuit.

The overall circuit of the push-pull LDO with high power supply rejection ratio and no off-chip capacitor is shown in Figure 3. The push-current mode and the pull-current mode share the error amplifier EA, the inverter, and the selector MUX- I～MUX-III and 220pF compensation capacitor C _C , through control signals _SM and _SMN , select one of two selectors MUX-I, MUX-II, MUX-III and transistor switches M ₁₁ , M ₁₆ , M ₁₉ , The control of M ₂₃ , M ₂₅ , and M ₂₈ is used to select the working mode of the LDO. When the current pushing module is working, the current pulling module is turned off, and when the current pulling module is working, the pushing current module is turned off, so as to reduce the quiescent current consumed. The voltage divider resistors _R1 and _R2 are connected in series to realize outputting different voltages in different working modes.

Figure 4 and Figure 5 show the power supply rejection ratio of the LDO push current mode and source current mode, respectively. When working in push current mode, the low frequency power supply rejection ratio is less than -58dB, the power supply rejection ratio in the frequency range of 1Hz-1GHz is less than -10dB, and the power supply rejection ratio at 1GHz is less than -15dB. When working in the pull current mode, the low frequency power supply rejection ratio is less than -39dB, the power supply rejection ratio in the 1Hz-1GHz frequency range is less than -10dB, and the power supply rejection ratio at 1GHz is less than -12dB.

The load transient response of the LDO is shown in Figure 6. The load current jumps between 10μA and 20mA, the rise/fall time is 6ns, the overshoot voltage of the push current mode is 31mV, and the undershoot voltage is 36mV; The overshoot voltage is 43mV and the undershoot voltage is 39mV.

Figure 7 and Figure 8 show the linear adjustment rate of LDO’s push current mode and pull current mode respectively. The rated output voltage of the push current mode is 1V. 0.12mV, the linear adjustment rate is 0.12%/V; the rated output voltage of the source current mode is 0.25V, when the peak input ripple is 50mV at the ground terminal, the output voltage change range is less than 1.1mV, and the linear adjustment rate is 4.4% /V.

The load regulation rate of the LDO is shown in Figure 9. When the load current changes between 10μA and 20mA, the output voltage change range of the push current mode is less than 0.2mV, and the load change rate is 0.01mV/mA; the output voltage of the pull current mode The change range is less than 0.5mV, and the load change rate is 0.025mV/mA.

The above description is only a preferred embodiment of the present invention, and the present invention should not be limited to the content disclosed in this embodiment and the accompanying drawings. All equivalents or modifications accomplished without departing from the disclosed spirit of the present invention fall within the protection scope of the present invention.

Claims (5)

1. A push-pull LDO with high power supply rejection ratio and no off-chip capacitor comprises a push current mode and a pull current mode; the method is characterized in that: the circuit structure comprises: the error amplifier EA, the alternative selector, the compensation capacitor, the push current module, the pull current module, the divider resistor and the inverter;

wherein, the error amplifier EA, the alternative selector, the divider resistor and the inverter are shared by a push current mode and a pull current mode;

the alternative selector comprises MUX-I, MUX-II and MUX-III;

the compensation capacitor comprises C _P 、C _N C _C ；

The voltage dividing resistor comprises R ₁ R is as follows ₂ ；

The current pushing module comprises a PMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;

the current pulling module comprises an NMOS power transistor, a common gate amplifier, a super source follower, a MOS transistor switch and a current mirror;

the connection relation of each module in the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio is as follows:

the output of the error amplifier EA is connected to MUX-I, channel 1 of MUX-I being simultaneously connected to C _N M is as follows ₂₇ Is connected to the gate of MUX-I channel 0 and C at the same time _P M is as follows ₁₇ Is connected with the grid electrode of C _N Is connected with a power supply, C _P Connected with the ground, the output end of the current pushing module is connected with C at the same time _C The output end of the pull current module, R2 and the channel 0 of the MUX-III are connected, C _C Connected to MUX-II, channel 1 of MUX-II is connected to a power supply, channel 0 of MUX-II is connected to ground, and channel 1 of MUX-III is simultaneously connected to R ₁ R is as follows ₂ Connected to M in the error amplifier EA and MUX-III ₂ Is connected with the grid electrode of the phase inverter and is simultaneously connected with M ₁₁ Gate, M of (2) ₁₆ Gate, M of (2) ₂₃ Gate, M of (2) ₂₈ The grid electrode of the (D), the MUX-I, MUX-II and the MUX-III are connected, and the output end of the inverter is simultaneously connected with M ₁₉ Gate of (c) and M ₂₅ R2 is connected with a power supply;

the working process of the push-pull type LDO without the off-chip capacitor with high power supply rejection ratio comprises the following steps:

step one, selecting an operation mode of the LDO, which specifically comprises the following sub-steps:

step 1.1 input a low/high control signal S _M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;

step 1.2 Low level/high level control Signal S _M Outputs a high level/low level control signal S through an inverter _MN ；

Step 1.3 high level control Signal S _M And a low level control signal S _MN Control signal S for controlling the push current module to work and the pull current module to be not work/low level _M And a high level control signal S _MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together;

at this time, the LDO operates in a push current mode/a pull current mode;

step two, stabilizing the output voltage at the rated value of the corresponding working mode, which comprises the following steps:

step 2.1 error amplificationThe reference voltage V is amplified by the EA _REF And feedback voltage V _F The difference value of the current is output to a push current module/a pull current module;

step 2.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;

step 2.3, feeding back the output voltage regulated by the current pushing module/current pulling module to the inverting input end of the error amplifier EA;

the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the steps 2.1, 2.2 and 2.3 in the step two are repeated until the output voltage is stabilized at the rated value of the corresponding working mode;

step three, rapidly responding to alternating current small signal fluctuation of output voltage, realizing power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz, and specifically comprising the following substeps:

step 3.1, when alternating current small signal fluctuation occurs at the power supply/ground end and the output voltage has alternating current small signal fluctuation, an error alternating voltage is generated at the drain end of the common grid amplifier in the push current module/pull current module;

step 3.2, transmitting error alternating voltage generated at the drain end of the common gate amplifier to the gate of the PMOS power transistor/NMOS power transistor after passing through the super source follower;

step 3.3 Gate Voltage variation of PMOS Power transistor/NMOS Power transistor leading to V _GS The power transistor adjusts the change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;

the push current module/pull current module is internally provided with a low-gain fast loop formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower, all nodes of the loop are low-resistance points and have unit gain frequency exceeding 700MHz, transient response lower than 6ns can be realized, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized under the condition that a mu F-level off-chip large capacitor is not needed.

2. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the push current module/pull current module is internally provided with a low-gain and rapid loop formed by a power transistor, a common gate amplifier and a super source follower, the loop has a unit gain frequency exceeding 700MHz, and the transient response of less than 6ns and the power supply rejection ratio of less than-10 dB in the frequency range of 1Hz-1GHz can be realized.

3. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the push current module/pull current module is internally provided with a low-gain and rapid loop formed by a power transistor, a common gate amplifier and a super source follower, all nodes of the loop are low-resistance points, and only the drain end of the power transistor is connected with an on-chip compensation capacitor C of 220pF _C To ensure loop stability without the need for large off-chip capacitors.

4. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: the LDO is provided with a push current mode and a pull current mode, wherein the push current mode is used for driving a power supply noise sensitive circuit, and a load circuit is connected between the output and the ground; the pull current mode is used for driving a ground noise sensitive circuit, and a load circuit is connected between the output and a power supply.

5. The high power supply rejection ratio off-chip capacitor free push-pull LDO of claim 1, wherein: high level control signal S _M And a low level control signal S _MN The current pushing module is controlled to work together, the current pulling module is not operated, and the LDO works in a current pushing mode; low level control signal S _M And a high level control signal S _MN The current pushing module is controlled to be not operated and the current pulling module is controlled to be operated together, and the LDO is operated in a current pulling mode.

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