CN115097894A - Push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor - Google Patents

Push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor Download PDF

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CN115097894A
CN115097894A CN202210856009.7A CN202210856009A CN115097894A CN 115097894 A CN115097894 A CN 115097894A CN 202210856009 A CN202210856009 A CN 202210856009A CN 115097894 A CN115097894 A CN 115097894A
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current
push
power supply
module
ldo
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CN115097894B (en
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周波
郑恒
韩欣媛
李一凡
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Beijing Institute of Technology BIT
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention relates to a push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor, belonging to the technical field of power supply management. The push current mode LDO and the pull current mode LDO are combined into a whole, and the problem that the traditional LDO only has the push current mode is solved. A low gain fast loop having a unity gain frequency in excess of 700MHz is included to achieve a high frequency power supply rejection ratio without requiring large off-chip capacitors in the μ F stage. The framework has two working modes of push current and pull current; the output voltage of the current pushing mode is 1V, the linear regulation rate is 0.12%/V, the load regulation rate is 0.01mV/mA, and a power supply noise sensitive circuit can be driven; the output voltage of the source current mode is 0.25V, the linear regulation rate is 4.4%/V, the load regulation rate is 0.025mV/mA, and a ground noise sensitive circuit can be driven; the two working modes both realize transient response lower than 6ns and power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1 GHz; and an off-chip large capacitor is not needed, and the full integration of the circuit is realized.

Description

Push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor
Technical Field
The invention relates to a push-pull type LDO (low dropout regulator) with high power supply rejection ratio and no off-chip capacitor, belonging to the technical field of power supply management.
Background
The LDO, as a linear dc regulator, has a minimum input voltage to ensure that the LDO maintains the output voltage within 100mV above or below its rated value, and the voltage difference between the minimum input voltage and the rated output voltage is called a droop voltage, and when the droop voltage must be greater than the saturation voltage of the power transistor, the LDO can normally operate, and the voltage ripple at the input end is attenuated and a regulated voltage is output.
The function of the LDO is mainly realized through a negative feedback control loop, a reference voltage module generates accurate and stable reference voltage, a feedback network feeds back the change of the output voltage to the input end of an error amplifier, the error amplifier amplifies the difference value of the feedback voltage and the reference voltage and outputs the difference value to the grid electrode of a power transistor, the power transistor is driven to adjust the output current, and the voltage output by the LDO is ensured to be stabilized within a rated value range.
LDOs typically use MOSFETs as power transistors, which are voltage driven and do not require current, thus greatly reducing the quiescent current consumed by the device itself. The voltage drop across the MOSFET is approximately equal to the product of the output current and the on-resistance, and the MOSFET has a very low saturation voltage due to its very small on-resistance, so the LDO usually only needs about 200mV of voltage drop, which is much lower than about 2V of voltage drop required by the conventional linear regulator. The lower the quiescent current and the lower the drop voltage, the higher the conversion efficiency of the LDO.
The LDO plays an important role in the market by virtue of advantages such as low cost, low voltage drop, low power consumption, low noise, and simple structure, and is widely used in portable electronic devices, communication systems, industrial devices, medical instruments, and other electronic devices requiring a stable power supply.
The power supply rejection ratio of the conventional LDO decreases with the increase of the operating frequency, so there is an upper limit to the operating frequency of the circuit requiring a high power supply rejection ratio. Common methods for enhancing the rejection ratio of a high-frequency power supply include an external compensation capacitor, a power tube substrate modulation technology and the like. The method of externally connecting the compensation capacitor usually needs a capacitor of a mu F level, the circuit can not be fully integrated, can not be applied to various miniature electronic equipment, and does not accord with the characteristic that the existing electronic equipment is more and more miniaturized. The power transistor substrate modulation technique needs to consume a large amount of static current, which can greatly reduce the efficiency of the LDO, and the circuit implementation is complex. The traditional LDO only has a push current mode, and can only be used for driving a load circuit sensitive to power supply noise and cannot be used for driving a load circuit sensitive to ground noise.
Disclosure of Invention
The invention provides a push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without an off-chip capacitor, and aims to solve the problems that the traditional LDO needs a large off-chip capacitor to realize the high-frequency power supply rejection ratio and cannot effectively drive a load circuit sensitive to ground noise.
The core idea of the invention is as follows: a power transistor, a common-gate amplifier and a super-source follower form a low-gain fast loop, all nodes of the loop are low-impedance nodes, so that the stability of the loop can be ensured only by using a 220pF on-chip compensation capacitor, and the drain terminal of the power transistor is set as the dominant pole of the loop, so that a mu F off-chip large capacitor is not needed; the low-gain fast loop has unit gain frequency exceeding 700MHz, has fast transient response speed, and can realize power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1 GHz; through sharing the error amplifier EA, the alternative selector, the divider resistor and the inverter, the push current module and the pull current module which have symmetrical circuit structures and the same working principle are combined together, and the load circuit sensitive to power supply noise and the load circuit sensitive to ground noise are effectively driven while too much static power consumption is not increased.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the push-pull LDO without off-chip capacitor with high power supply rejection ratio comprises an error amplifier EA, an alternative selector, a compensating capacitor, a push current module, a pull current module, a voltage division resistor and a phase inverter;
the error amplifier EA adopts a differential single-folded cascode transconductance amplifier with NMOS transistors as input pairs, provides high gain, attenuates power supply noise and ground noise to a certain degree, and outputs relatively clean voltage to a post-stage circuit;
the alternative selector comprises MUX-I, MUX-II and MUX-III, and is realized by adopting a digital logic circuit;
wherein the compensation capacitor comprises C P 、C N And C C A metal-insulator-metal capacitor is adopted;
the current pushing module comprises a PMOS power transistor, a common-gate amplifier, a super source follower, an MOS transistor switch and a current mirror;
the source current module comprises an NMOS power transistor, a common grid amplifier, a super source follower, an MOS transistor switch and a current mirror;
wherein the voltage dividing resistor comprises R 1 And R 2 Adopting a polysilicon resistor;
the inverter is realized by a digital logic circuit.
The connection relation of each module in the push-pull type LDO without off-chip capacitor with high power supply rejection ratio is as follows:
the output end of the error amplifier EA is connected with MUX-I, and the channels 1 of the MUX-I are respectively connected with C N And a current-drawing module connected with channel 0 of MUX-I and C P And a push current module connected to C N Respectively connected to channel 1 of MUX-I and to a power supply, C P Respectively connected with channel 0 of MUX-I and ground, and output ends of source current module and push current module and C C 、R 2 And MUX-III connected to C C Connected with MUX-II, whose channel 1 is connected with power supply, channel 0 is connected with ground, and MUX-III is respectively connected with R 1 、R 2 And the inverting input end of the error amplifier EA is connected, and the inverter is respectively connected with the MUX-I, MUX-II, the MUX-III, the push current module and the source current module.
The functions of each module in the push-pull type LDO without off-chip capacitor with high power supply rejection ratio are as follows:
the function of the error amplifier EA is to amplify the reference voltage V REF And a feedback voltage V F The difference value is output to a post-stage circuit, and the feedback voltage V is output F Clamped at a reference voltage V REF Nearby, high gain is provided, better linear adjustment rate and load adjustment rate are realized, and the low-frequency power supply rejection ratio is enhanced;
the function of the alternative selector is to select the circuit to work in a push current mode or a pull current mode;
the compensation capacitor has the function of compensating the phase margin of each loop in the circuit and enhancing the stability of the system;
the current pushing module has the functions of providing a low-gain fast loop, realizing fast transient response and enhanced high-frequency power supply rejection ratio and outputting a clean voltage of reference ground;
the current-pulling module has the functions of providing a low-gain rapid loop, realizing rapid transient response and enhanced high-frequency power supply rejection ratio and outputting clean voltage of a reference power supply;
the voltage division resistor has the function of realizing voltage division by being connected between the output and the power supply in series, and providing different output voltage values for the source current mode and the push current mode;
the function of the inverter is to output one and M voltage S of opposite level MN And the control circuit is used for controlling the opening or closing of partial transistor switches in the push current module and the pull current module.
The working process of the push-pull type LDO with high power supply rejection ratio and no off-chip capacitor specifically comprises the following steps:
step one, selecting the working mode of the LDO, and specifically comprising the following substeps:
step 1.1 input a low/high control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
step 1.2 Low/high control Signal S M Outputting a high/low control signal S through an inverter MN ；
Step 1.3 high level control signal S M And a low level control signal S MN Jointly controlling the push current module to work and the source current module not to work/low level control signal S M And a high level control signal S MN The push current module and the pull current module are controlled to work together;
at the moment, the LDO works in a push current mode/a pull current mode;
step two, stabilizing the output voltage at a rated value corresponding to the working mode, and specifically comprising the following substeps:
step 2.1 error amplifier EA amplifies reference voltage V REF And feedbackVoltage V F And the difference is output to a push current module/a pull current module;
step 2.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
step 2.3, feeding back the output voltage adjusted by the push current module/pull current module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the 3 steps are repeated until the output voltage is stabilized at a rated value corresponding to the working mode;
thirdly, rapidly responding to the small alternating-current signal fluctuation of the output voltage to realize a power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz, and specifically comprising the following substeps:
3.1, when the alternating current small signal fluctuation occurs at the power supply/ground end, so that the output voltage has alternating current small signal fluctuation, an error alternating current voltage is generated at the drain end of the common grid amplifier in the current pushing module/the current pulling module;
3.2 transmitting the error alternating-current voltage generated at the drain terminal of the common-gate amplifier to the grid of the PMOS power transistor/NMOS power transistor after passing through the super source follower;
step 3.3 Gate Voltage variation of PMOS/NMOS Power transistors leads to V GS The power transistor adjusts the size change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
a low-gain rapid loop is formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower in the push current module/source current module, all nodes of the loop are low-resistance points and have high unit gain frequency, the 3 steps can be rapidly responded, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized without a large capacitor outside a mu F stage.
Advantageous effects
Compared with the traditional LDO, the push-pull type LDO without off-chip capacitor with high power supply rejection ratio has the following beneficial effects:
1. a low-gain fast loop is introduced, so that fast transient response with response time lower than 6ns and power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz are realized under the condition of not needing a large capacitance outside a mu F level chip;
2. the error amplifier adopts a differential single-folded cascode transconductance amplifier with NMOS transistors as input pairs, provides high gain, realizes better linear regulation rate and load regulation rate, and enhances the rejection ratio of a low-frequency power supply;
3. the push current mode and the pull current mode are combined together through the shared error amplifier EA, the alternative selector, the divider resistor and the inverter, so that the circuit sensitive to power noise and the circuit sensitive to ground noise can be driven, and the problem that the traditional LDO cannot drive the circuit sensitive to ground noise is solved while excessive quiescent current is not increased;
4. and a large capacitor outside a mu F grade chip is not needed, the full integration of the circuit is realized, and the cost is saved.
Drawings
FIG. 1 is a schematic diagram of a push-current mode circuit of a push-pull LDO without an off-chip capacitor with high power rejection ratio;
FIG. 2 is a schematic diagram of a pull-mode LDO with high power rejection ratio and no off-chip capacitor according to the present invention;
FIG. 3 is a schematic diagram of the whole circuit of the push-pull LDO without off-chip capacitor with high power supply rejection ratio of the present invention;
FIG. 4 is a diagram of power supply rejection ratio of the push-pull type LDO without off-chip capacitor in the push-current mode of the present invention;
FIG. 5 is a diagram of the power supply rejection ratio of the pull-out mode of the push-pull LDO without off-chip capacitor with high power supply rejection ratio of the present invention;
FIG. 6 is a load transient response diagram of a high power rejection ratio push-pull LDO without an off-chip capacitor according to the present invention;
FIG. 7 is a graph of the linear slew rate of the push-pull LDO without off-chip capacitor of the present invention in the push-current mode;
FIG. 8 is a graph of the linear regulation rate of the pull-out mode of the pull-push LDO without off-chip capacitor with high power rejection ratio of the present invention;
FIG. 9 is a graph of the load regulation rate of a push-pull LDO without an off-chip capacitor with high power rejection ratio of the present invention;
Detailed Description
The following describes and explains each circuit module and operation process of the push-pull type LDO supporting system without off-chip capacitor with high power supply rejection ratio in detail with reference to the embodiment and the accompanying drawings.
Example 1
The working process of the push-pull type LDO without off-chip capacitor with high power supply rejection ratio is as follows:
step A, selecting the working mode of the LDO, and specifically comprising the following substeps:
step A.1 inputting a low/high control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
in particular to the embodiment, the input high level control signal S M Is 1.25V, and the low level control signal S M Is 0;
step A.2 Low/high control Signal S M Outputting a high/low control signal S through an inverter MN ；
In particular to the embodiment, the inverter outputs the high level control signal S MN Is 1.25V, and the low level control signal S MN Is 0;
step A.3 high level control signal S M And a low level control signal S MN Jointly control the push current module to work and the pull current module to not work/low level control signal S M And a high level control signal S MN The push current module and the pull current module are controlled to work together;
at the moment, the LDO works in a push current mode/a pull current mode;
specifically, in the present embodiment, the load circuit in the push current mode of the LDO is connected between the output terminal and the ground, and the load circuit in the pull current mode is connected between the output terminal and the power supply;
step B, stabilizing the output voltage at a rated value corresponding to the working mode, and specifically comprising the following substeps:
step B.1 error amplifier EA amplifies reference voltage V REF And a feedback voltage V F And the difference is output to a push current module/a pull current module;
with specific reference to the present embodiment, the reference voltage V REF Is 1V;
b.2, adjusting the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
specifically, in the embodiment, the output voltage in the push current mode is 1V, the output voltage in the pull current mode is 0.25V, and different output voltages pass through the voltage dividing resistor R 1 And R 2 Serial connection is realized;
b.3, feeding back the output voltage adjusted by the push current module/pull current module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the 3 steps are repeated until the output voltage is stabilized at a rated value;
specifically, in the present embodiment, the rated output voltage of the push current mode is 1V, and the rated output voltage of the pull current mode is 0.25V;
and step C, rapidly responding to the small alternating-current signal fluctuation of the output voltage to realize a power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz, and specifically comprising the following substeps:
step C.1, when alternating current small signal fluctuation occurs at the power supply/ground end, so that the output voltage has alternating current small signal fluctuation, an error alternating current voltage is generated at the drain end of a common grid amplifier in the current pushing module/the current pulling module;
specifically, in the present embodiment, an ac small signal with a peak value of 50mV is input at the power supply terminal in the push current mode, and an ac small signal with a peak value of 50mV is input at the ground terminal in the pull current mode;
c.2, transmitting the error alternating-current voltage generated at the drain terminal of the common-gate amplifier to the grid of the PMOS power transistor/NMOS power transistor after passing through the super source follower;
C.3PMOS power transistor/NMOS power transistor grid voltage change causes V GS The power transistor adjusts the size change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
a low-gain rapid loop is formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower in the push current module/source current module, all nodes of the loop are low-resistance points and have high unit gain frequency, the 3 steps can be rapidly responded, and the power supply rejection ratio lower than-10 dB in the frequency range of 1Hz-1GHz is realized without a large capacitor outside a mu F stage;
specifically, in the embodiment, the unit gain frequency of the push current mode/pull current mode of the LDO is 700MHz/750MHz, and both the two operation modes achieve a transient response of less than 6ns and a power supply rejection ratio of less than-10 dB in the frequency range of 1Hz to 1 GHz.
Example 2
The push-current mode schematic diagram of the push-pull type LDO without off-chip capacitor with high power supply rejection ratio is shown in FIG. 1, wherein a loop-I is a low-gain fast loop composed of a PMOS power transistor, a common-gate amplifier and a buffer, has a unit gain frequency exceeding 700MHz, and can realize ultra-fast transient response and enhanced high-frequency power supply rejection ratio. When alternating current small signal fluctuation occurs at a power supply end to cause the output voltage to have alternating current small signal fluctuation, an error alternating voltage is generated at a drain end of the common-gate amplifier, the error alternating voltage is transmitted to a gate of the PMOS power transistor after passing through the buffer, and the grid voltage change of the PMOS power transistor causes V GS And the magnitude change of the load current is adjusted to resist the fluctuation of the output voltage, so that a better high-frequency power supply rejection ratio is realized. To ensure the stability of loop-I, a 220pF capacitor C is used C The dominant pole is placed at the drain of the PMOS power transistor. The loop-II is a high-gain slow-speed loop, and enhances the load regulation rate, the linear regulation rate and the low-frequency power supply rejection ratio of the LDO. To ensure the stability of loop-II, it is necessary to have a voltage between the output of the error amplifier and groundFollowed by a 1.5pF compensating capacitor C P . The output voltage of the push current mode is 1V. When in the current pushing mode, the load circuit is connected between the output end of the LDO and the ground, so that the influence of small signal voltage fluctuation of a power supply end on the output can be effectively reduced, and a clean driving voltage is provided for the load circuit.
The drawing of the current-pulling mode working principle of the push-pull type LDO without the off-chip capacitor with the high power supply rejection ratio is shown in FIG. 2, the working principle of the current-pulling mode is the same as that of the current-pulling mode, and the pull-pull type LDO also has a low-gain fast loop-I and a high-gain slow loop-II. To ensure the stability of loop-I, a 220pF capacitor C is used C The dominant pole is placed at the drain of the NMOS power transistor. In order to ensure the stability of loop-II, a 1pF compensation capacitor C is connected between the output of the error amplifier and the power supply N . The output voltage of the source current mode is 0.25V. When in a current pulling mode, the load circuit is connected between the output end of the LDO and the power supply, so that the influence of small signal voltage fluctuation at the ground end on the output can be effectively reduced, and a clean driving voltage is provided for the load circuit.
The whole circuit of the push-pull LDO without off-chip capacitor with high power supply rejection ratio is shown in FIG. 3, the push current mode and the pull current mode share an error amplifier EA, an inverter, alternative selectors MUX-I-MUX-III and a compensation capacitor C of 220pF C By means of a control signal S M And S MN For alternative selectors MUX-I, MUX-II, MUX-III and transistor switch M 11 、M 16 、M 19 、M 23 、M 25 、M 28 The pull-out current module is closed when the pull-out current module works, and the pull-out current module is closed when the pull-out current module works, so that consumed quiescent current is reduced. Through a voltage-dividing resistor R 1 And R 2 The series connection realizes that different working modes output different voltages.
Fig. 4 and 5 show the power supply rejection ratio of the LDO push current mode and pull current mode, respectively. When the power supply works in a current pushing mode, the low-frequency power supply rejection ratio is smaller than-58 dB, the power supply rejection ratio in the frequency range of 1Hz to 1GHz is smaller than-10 dB, and the power supply rejection ratio at the 1GHz is smaller than-15 dB. When the power supply works in a source current mode, the low-frequency power supply rejection ratio is smaller than minus 39dB, the power supply rejection ratio in the frequency range of 1Hz to 1GHz is smaller than minus 10dB, and the power supply rejection ratio at the 1GHz position is smaller than minus 12 dB.
Load transient response of the LDO is shown in FIG. 6, a load current jumps between 10 μ A and 20mA, the rising/falling time is 6ns, the overshoot voltage in the push current mode is 31mV, and the undershoot voltage is 36 mV; the up-rush voltage of the source current mode is 43mV, and the down-rush voltage is 39 mV.
Fig. 7 and 8 show the linear regulation rates of the push current mode and the pull current mode of the LDO, respectively, where the rated output voltage of the push current mode is 1V, when a ripple with a peak value of 50mV is input at the power supply terminal, the output voltage variation amplitude is less than 0.12mV, and the linear regulation rate is 0.12%/V; the rated output voltage of the source current mode is 0.25V, when ripple waves with the peak value of 50mV are input at the ground end, the variation amplitude of the output voltage is less than 1.1mV, and the linear regulation rate is 4.4%/V.
The load regulation rate of the LDO is shown in fig. 9, when the load current varies between 10 μ a and 20mA, the output voltage variation amplitude of the push current mode is less than 0.2mV, and the load variation rate is 0.01 mV/mA; the output voltage variation amplitude of the source current mode is less than 0.5mV, and the load variation rate is 0.025 mV/mA.
While the foregoing is directed to the preferred embodiment of the present invention, it is not intended that the invention be limited to the embodiment and the drawings disclosed herein. It is intended that all equivalents and modifications which do not depart from the spirit of the invention disclosed herein are deemed to be within the scope of the invention.

Claims (6)

1. A push-pull type LDO without off-chip capacitor with high power supply rejection ratio comprises a push current mode and a pull current mode; the method is characterized in that: the circuit structure includes: the circuit comprises an error amplifier EA, an alternative selector, a compensating capacitor, a push current module, a source current module, a divider resistor and a phase inverter;
the error amplifier EA, the alternative selector, the divider resistor and the inverter are shared by a push current mode and a pull current mode;
the alternative selector comprises MUX-I, MUX-II and MUX-III;
the compensation capacitor comprises C P 、C N And C C ；
The voltage-dividing resistor includes R 1 And R 2 ；
The current pushing module comprises a PMOS power transistor, a common-gate amplifier, a super source follower, an MOS transistor switch and a current mirror;
the source current module comprises an NMOS power transistor, a common grid amplifier, a super source follower, an MOS transistor switch and a current mirror;
the connection relation of each module in the push-pull type LDO without the off-chip capacitor with the high power supply rejection ratio is as follows:
the output end of the error amplifier EA is connected with MUX-I, and the channels 1 of the MUX-I are respectively connected with C N And a current-drawing module connected with channel 0 of MUX-I and C P And a push current module connected to C N Respectively connected to channel 1 of MUX-I and to a power supply, C P Respectively connected with channel 0 of MUX-I and ground, and output ends of source current module and push current module and C C 、R 2 And MUX-III connected, C C Connected with MUX-II, whose channel 1 is connected with power supply, channel 0 is connected with ground, and MUX-III is respectively connected with R 1 、R 2 The inverting input end of the error amplifier EA is connected, and the inverter is respectively connected with the MUX-I, MUX-II, the MUX-III, the push current module and the source current module;
the working process of the push-pull type LDO with high power supply rejection ratio and no off-chip capacitor specifically comprises the following steps:
step one, selecting the working mode of the LDO, and specifically comprising the following substeps:
step 1.1 input a low/high control signal S M MUX-I, MUX-II and MUX-III both gate channel 0/channel 1;
step 1.2 Low/high control Signal S M Outputting a high/low control signal S through an inverter MN ；
Step 1.3 high level control Signal S M And a low level control signal S MN Jointly controlling the push current module to work and the source current module not to work/low level control signal S M And a high level control signal S MN The push current module and the pull current module are controlled to work together;
at the moment, the LDO works in a push current mode/a pull current mode;
step two, stabilizing the output voltage at a rated value corresponding to the working mode, and specifically comprising the following substeps:
step 2.1 error amplifier EA amplifies reference voltage V REF And a feedback voltage V F And the difference is output to a push current module/a pull current module;
step 2.2, the current pushing module/current pulling module adjusts the output voltage of the current pushing module/current pulling module according to the amplification difference value provided by the error amplifier EA;
step 2.3, feeding back the output voltage adjusted by the push current module/pull current module to the inverting input end of the error amplifier EA;
the error amplifier EA and the current pushing module/current pulling module form a negative feedback loop, and the 3 steps are repeated until the output voltage is stabilized at a rated value corresponding to the working mode;
and step three, rapidly responding to the alternating current small signal fluctuation of the output voltage, and realizing a power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz, which specifically comprises the following substeps:
3.1, when the alternating current small signal fluctuation occurs at the power supply/ground end, so that the output voltage has alternating current small signal fluctuation, an error alternating current voltage is generated at the drain end of the common grid amplifier in the current pushing module/the current pulling module;
3.2, transmitting the error alternating-current voltage generated at the drain end of the common-gate amplifier to the grid electrode of the PMOS power transistor/NMOS power transistor after passing through the super source electrode follower;
step 3.3 Gate Voltage variations of PMOS/NMOS Power transistors leads to V GS The power transistor adjusts the size change of the load current to resist the fluctuation of the output voltage and stabilize the output voltage;
a low-gain rapid loop is formed by a PMOS power transistor/NMOS power transistor, a common grid amplifier and a super source follower in the push current module/source current module, all nodes of the loop are low-resistance points and have unit gain frequency exceeding 700MHz, transient response lower than 6ns can be realized, and power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1GHz is realized under the condition that a large capacitor outside a mu F stage is not needed.
2. The push-pull type LDO without off-chip capacitor having high power supply rejection ratio as claimed in claim 1, wherein: a low-gain fast loop is formed by a power transistor, a common-gate amplifier and a super-source follower, has a unit gain frequency exceeding 700MHz, and can realize transient response lower than 6ns and a power supply rejection ratio lower than-10 dB in a frequency range of 1Hz-1 GHz.
3. The push-pull type LDO without off-chip capacitor having high power supply rejection ratio as claimed in claim 1, wherein: a low-gain fast loop is formed by a power transistor, a common-gate amplifier and a super-source follower, all nodes of the loop are low-resistance points, and only a 220pF on-chip compensating capacitor C is connected to the drain terminal of the power transistor C To ensure loop stability without requiring large off-chip capacitors.
4. The push-pull type LDO without off-chip capacitor having high power supply rejection ratio as claimed in claim 1, wherein: the LDO has a push current mode and a pull current mode, the push current mode is used for driving a power supply noise sensitive circuit, and the load circuit is connected between the output and the ground; the source current mode is used for driving a ground noise sensitive circuit, and the load circuit is connected between the output and the power supply.
5. The push-pull type LDO without off-chip capacitor having high power supply rejection ratio as claimed in claim 1, wherein: the push current mode and the pull current mode share the error amplifier EA, the alternative selector, the divider resistor and the inverter.
6. Root of herbaceous plantsThe push-pull type LDO without off-chip capacitor having high power supply rejection ratio as claimed in claim 1, wherein: high level control signal S M And a low level control signal S MN The push current module and the pull current module are controlled to work together, the LDO works in a push current mode; low level control signal S M And a high level control signal S MN The push current module and the source current module are controlled to work together, and the LDO works in a source current mode.
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