CN114356008A - Low dropout regulator - Google Patents
Low dropout regulator Download PDFInfo
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- CN114356008A CN114356008A CN202111544463.0A CN202111544463A CN114356008A CN 114356008 A CN114356008 A CN 114356008A CN 202111544463 A CN202111544463 A CN 202111544463A CN 114356008 A CN114356008 A CN 114356008A
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- 230000004044 response Effects 0.000 claims abstract description 20
- 230000001052 transient effect Effects 0.000 claims abstract description 18
- 239000003381 stabilizer Substances 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000006641 stabilisation Effects 0.000 claims 1
- 238000011105 stabilization Methods 0.000 claims 1
- 230000008859 change Effects 0.000 abstract description 7
- 230000000087 stabilizing effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The invention provides a low dropout linear regulator, which comprises a main negative feedback loop and a fast load transient response loop, wherein the main negative feedback loop comprises an error amplifier and a first PMOS (P-channel metal oxide semiconductor) tube, the inverting input end of the error amplifier is connected with the output of the regulator, the output end of the error amplifier is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the output of the regulator; the fast load transient response loop comprises a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the drain electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrodes of the second PMOS tube and the first NMOS tube are connected with the output of the linear voltage stabilizer. The low dropout regulator can quickly respond to load change, reduce the fluctuation of output voltage caused by load change and keep the stability of power supply to the maximum extent.
Description
Technical Field
The disclosure relates to the technical field of analog integrated circuits, in particular to a low dropout regulator.
Background
The low dropout regulator is an important power management module in an integrated circuit, and is responsible for converting a voltage from a higher level to a lower level, generally providing stable and reliable power supply for an analog or radio frequency circuit module sensitive to noise, and providing a certain degree of protection.
The load condition of the low dropout regulator varies widely, the load current can jump from several microamperes to tens of milliamperes within a few nanoseconds and then fall back to several microamperes, and the specific condition depends on the characteristics and the working condition of the load. Therefore, low dropout linear regulators are required to be stable over a wide range of load variations while being able to respond quickly to load variations to reduce the impact on the output voltage. Fig. 1 shows the structure of a conventional low dropout linear regulator, and generally, in order to achieve low dropout and large load capacity, the area of the power transistor MP1 is large, and therefore the gate parasitic capacitance of MP1 is large. When the output load of the low dropout linear regulator changes, firstly, the output voltage Vout changes, the output voltage Vout is fed back to one end of an error amplifier A1 through voltage dividing resistors R1 and R2, and then the output voltage Vout is amplified to the gate of MP1 through the difference between A1 and a reference voltage Vref, and MP1 acts to adjust the Vout, so that a negative feedback working loop is formed integrally. The loop response needs to pass through the capacitance of each internal node and the charge-discharge delay of the MP1, so that a certain time is needed for the Vout to recover to a steady-state value, and the load transient response is usually improved by two methods, on one hand, the charge-discharge time of the internal node is reduced by increasing the quiescent current of the low dropout linear regulator, but the problem of loop stability and static power consumption increase is brought by simply increasing the current, on the other hand, the output voltage-stabilizing capacitor C1 is added to stabilize the voltage when the loop does not respond in time, but the method usually needs a larger capacitor to achieve a better effect, and the chip area and the cost are increased.
Disclosure of Invention
In view of this, in order to solve the problems of the conventional low dropout regulator, the embodiments of the present disclosure provide a low dropout regulator that can quickly respond to load changes, reduce the fluctuation of the output voltage due to the load changes, and maintain the stability of power supply to the maximum extent.
In order to achieve the above purpose, the invention provides the following technical scheme:
a low dropout linear regulator includes a main negative feedback loop and a fast load transient response loop,
the main negative feedback loop comprises an error amplifier and a first PMOS (P-channel metal oxide semiconductor) tube, wherein the inverting input end of the error amplifier is connected with the output of the linear voltage stabilizer, the output end of the error amplifier is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the output of the linear voltage stabilizer to form the main negative feedback loop;
the fast load transient response loop comprises a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the drain electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrodes of the second PMOS tube and the first NMOS tube are connected with the output of the linear voltage stabilizer.
Further, the fast load transient response loop further comprises a first current source, a second current source and a third current source, wherein one end of the first current source and one end of the second current source are connected with the input voltage, the other end of the first current source is connected with the output of the linear voltage regulator, the other end of the second current source is connected with the drain electrode of the second NMOS transistor, one end of the third current source is connected with the drain electrode of the first PMOS transistor, and the other end of the third current source is connected with the circuit reference ground.
Further, the grid electrode of the second NMOS tube is connected to a fixed grid electrode bias voltage.
Further, the source electrode of the first NMOS tube is connected with the ground, and the source electrode of the second PMOS tube is connected with the input voltage.
Furthermore, the main negative feedback loop further comprises a first feedback resistor and a second feedback resistor, the first feedback resistor and the second feedback resistor are connected in series at the output end of the linear voltage regulator, and the common end between the first feedback resistor and the second feedback resistor is connected to the inverting input end of the error amplifier.
And one end of the voltage stabilizing capacitor is connected with the output of the linear voltage stabilizer, and the other end of the voltage stabilizing capacitor is connected with the circuit reference ground.
Further, the non-inverting input end of the error amplifier is connected with a reference voltage.
The low dropout regulator can quickly respond to the transient change of the load under the condition of not increasing too much current and area, reduce the fluctuation of the output voltage of the low dropout regulator caused by the change of the load and provide low-disturbance and high-quality power supply voltage for a rear-stage load circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a conventional low dropout linear regulator architecture of the prior art;
fig. 2 is a circuit structure of a low dropout regulator according to an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The disclosed embodiment provides a low dropout linear regulator comprising a main negative feedback loop and a fast load transient response loop.
The specific circuit implementation of the main negative feedback loop and the fast load transient response loop is as follows, as shown in fig. 2.
The main negative feedback loop and the fast load transient response loop 101 jointly form the low dropout regulator 1, which comprises a reference voltage Vref, an error amplifier a1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a gate bias voltage Vbn1, a first current source Ib1, a second current source Ib2, a third current source Ib3, a first feedback resistor R1, a second feedback resistor R2 and a voltage stabilizing capacitor C1.
The main negative feedback loop starts from an output O of the low dropout linear regulator 1, is connected in series through a first feedback resistor R1 and a second feedback resistor R2 to divide voltage and feed back to an inverting input end of an error amplifier A1, the other end of the second feedback resistor R2 is connected to a circuit reference ground gnd, a non-inverting input end of the error amplifier A1 is connected with a reference voltage Vref, an output M of the error amplifier A1 is connected with a grid electrode of a first PMOS tube MP1, and a source electrode of the first PMOS tube MP1 is connected to the output O.
The fast load transient response loop 101 also starts from the output O, and is connected to one end of the first current source Ib1 and the source of the first PMOS transistor MP1, the drain of the first PMOS transistor MP1 and one end of the third current source Ib3, the gate of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are connected, the gate of the second NMOS transistor MN2 is connected to the fixed gate bias voltage Vbn1, the drain of the second NMOS transistor MN2 is connected to one end of the second current source Ib2 and the gate of the second PMOS transistor MP2, the drains of the second PMOS transistor MP2 and the first NMOS transistor MN1 are connected to the output O, the other ends of the first current source Ib1 and the second current source Ib2 are connected to the input voltage Vin, and the other end of the third current source Ib3 is connected to the circuit reference ground gnd.
The first current source Ib1, the second current source Ib2 and the third current source Ib3 provide necessary current bias for the fast load transient response loop 101, and determine the static operating point of each node inside the loop, thereby ensuring that the loop can normally operate.
One end of the voltage stabilizing capacitor C1 is connected to the output O, and the other end is connected to the circuit reference ground gnd.
When the load current of the low dropout linear regulator is suddenly increased, the output voltage Vout is rapidly reduced, the change is transmitted to the gate of the first NMOS transistor MN1 through the cascode stage of the first PMOS transistor MP1, so that the gate voltage of the first NMOS transistor MN1 is reduced, the pull-down is weakened, and meanwhile, the signal is transmitted to the gate of the second PMOS transistor MP2 through the cascode stage of the second NMOS transistor MN2, so that the gate voltage of the second PMOS transistor MP2 is reduced, the output current capability of the second PMOS transistor MP2 is increased, and the reduction of the output voltage Vout is compensated; when the load current of the low dropout regulator suddenly decreases, it can be analyzed that the output voltage Vout rapidly increases, the gate voltage of the first NMOS transistor MN1 increases, the pull-down of the first NMOS transistor MN1 increases, and the gate voltage of the second PMOS transistor MP2 rises, so as to weaken the output current capability of the second PMOS transistor MP2 and suppress the overshoot of the output voltage Vout.
Compared with the main negative feedback loop, the fast load transient response loop has fewer nodes and shorter charge-discharge time, so that the fast load transient response loop has faster response and can restrain the change of the output voltage Vout caused by the jump of the load current. The main negative feedback loop does not need to have quick response to load change in the invention, so that the loop bandwidth does not need to be designed to be large, and meanwhile, the loop gain can be made to be high, and the regulation precision of the output voltage Vout can be improved while the power consumption is reduced. Meanwhile, due to the existence of the rapid load transient response loop, the voltage stabilizing capacitor C1 does not need to be large, the circuit area can be reduced to a certain extent, and the cost is reduced.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (7)
1. A low dropout linear regulator comprises a main negative feedback loop and a fast load transient response loop,
the main negative feedback loop comprises an error amplifier and a first PMOS (P-channel metal oxide semiconductor) tube, wherein the inverting input end of the error amplifier is connected with the output of the linear voltage stabilizer, the output end of the error amplifier is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the output of the linear voltage stabilizer to form the main negative feedback loop;
the fast load transient response loop comprises a second PMOS tube, a first NMOS tube and a second NMOS tube, wherein the drain electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the source electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube, and the drain electrodes of the second PMOS tube and the first NMOS tube are connected with the output of the linear voltage stabilizer.
2. The low dropout regulator of claim 1 wherein the fast load transient response loop further comprises a first current source, a second current source and a third current source, wherein one end of the first current source and one end of the second current source are connected to the input voltage, the other end of the first current source is connected to the output of the regulator, the other end of the second current source is connected to the drain of the second NMOS transistor, one end of the third current source is connected to the drain of the first PMOS transistor, and the other end of the third current source is connected to the circuit ground.
3. The low dropout regulator of claim 1 wherein the gate of the second NMOS transistor is coupled to a fixed gate bias voltage.
4. The LDO of claim 1, wherein the source of the first NMOS transistor is coupled to ground and the source of the second PMOS transistor is coupled to an input voltage.
5. The low dropout regulator according to any one of claims 1 to 4, wherein the main negative feedback loop further comprises a first feedback resistor and a second feedback resistor, the first feedback resistor and the second feedback resistor are connected in series at the output terminal of the linear regulator, and the common terminal between the first feedback resistor and the second feedback resistor is connected to the inverting input terminal of the error amplifier.
6. The low dropout regulator according to claim 5, further comprising a voltage stabilization capacitor having one terminal connected to the output of the linear regulator and the other terminal connected to the circuit reference ground.
7. The low dropout regulator of claim 6 wherein a non-inverting input of the error amplifier is coupled to a reference voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111544463.0A CN114356008B (en) | 2021-12-16 | 2021-12-16 | Low-dropout linear voltage regulator |
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| CN202111544463.0A CN114356008B (en) | 2021-12-16 | 2021-12-16 | Low-dropout linear voltage regulator |
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| CN114356008B CN114356008B (en) | 2023-11-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115097894A (en) * | 2022-07-08 | 2022-09-23 | 北京理工大学 | Push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor |
| CN115437443A (en) * | 2022-09-14 | 2022-12-06 | 上海富芮坤微电子有限公司 | Low dropout linear voltage stabilizing circuit and system on chip |
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2021
- 2021-12-16 CN CN202111544463.0A patent/CN114356008B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115097894A (en) * | 2022-07-08 | 2022-09-23 | 北京理工大学 | Push-pull type LDO (low dropout regulator) with high power supply rejection ratio and without off-chip capacitor |
| CN115097894B (en) * | 2022-07-08 | 2023-05-30 | 北京理工大学 | High-power supply rejection ratio push-pull type LDO (low dropout regulator) without off-chip capacitor |
| CN115437443A (en) * | 2022-09-14 | 2022-12-06 | 上海富芮坤微电子有限公司 | Low dropout linear voltage stabilizing circuit and system on chip |
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Address after: Room 201, Block C, Building 1, No. 599 Gaojing Road, Qingpu District, Shanghai, 201702 Patentee after: Shanghai chuantu Microelectronics Co.,Ltd. Address before: No.888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201306 Patentee before: Shanghai chuantu Microelectronics Co.,Ltd. |