CN116126078B - LDO stability enhancement circuit, LDO stability enhancement method and chip system - Google Patents
LDO stability enhancement circuit, LDO stability enhancement method and chip system Download PDFInfo
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Abstract
A stability enhancement circuit, a method and a chip system of an LDO, wherein the LDO comprises an error operational amplifier, a first node is arranged at the output end of the error operational amplifier, and the stability enhancement circuit is connected with the first node; the stability enhancing circuit comprises a voltage detecting element and an impedance self-adaptive adjusting element, wherein the voltage detecting element is used for detecting the voltage at the first node, the impedance self-adaptive adjusting element is used for providing a compensation resistor, and the impedance self-adaptive adjusting element is used for adaptively adjusting the resistance value of the compensation resistor provided by the impedance self-adaptive adjusting element according to the detected voltage at the first node, so that the output impedance at the first node is adaptively adjusted, and the stability of the LDO under light load is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to the field of CMOS analog integrated circuit design, and specifically relates to a stability enhancement circuit, a method and a chip system of a Low dropout-out Voltage Regulator (LDO for short) of a Low dropout linear regulator.
Background
In the current development of the integrated circuit industry, a power management chip plays an extremely important role, and can provide stable voltage for the rest circuits of the system. The low dropout linear regulator chip is LDO for short, belongs to a power management chip, and has the remarkable advantages that: the structure is simple, the response is fast, the output noise is low, the static power consumption is low, the circuit scale is small, and the like, so that the power supply is an almost necessary key power supply module in the digital-analog hybrid chip.
The working principle of the LDO is that when the output load current or the input power supply voltage is subjected to transient change, the output current of the power tube is dynamically regulated by utilizing a negative feedback technology, so that stable voltage is output.
The design of the LDO as a negative feedback system inevitably involves analysis of system stability, the stability of the LDO is affected by three variables of maximum output current, load capacitance and no-load quiescent current, and when the three variables are changed, the stability of the LDO is changed, for example:
case1, under the conditions of larger load capacitance and smaller maximum output current, the LDO has good stability under light load (smaller load current) and heavy load (larger load current);
case 2, under the conditions of small load capacitance, large maximum output current and large no-load quiescent current, the LDO has good stability under light load, but has stability problem under heavy load;
case 3, under the conditions of small load capacitance, small maximum output current and small no-load quiescent current, the LDO has good stability in heavy load, but has stability problem in light load;
case 4, under the conditions of small load capacitance, large maximum output current and small no-load quiescent current, the LDO has stability problems during light load and heavy load.
As described above, the LDO of the prior art, for example, when applied to the cases of Case 3 and Case 4 described above, has a stability problem under light load, which limits the application of the LDO, so the present application provides a stability enhancing circuit and method of the LDO, which can solve the problem of the prior art, and the improved LDO has a lower power consumption and a smaller circuit area, and ensures miniaturization and low power consumption of the chip on the basis of having good functions.
Disclosure of Invention
In order to overcome the defects of the prior art, the application provides a stability enhancing circuit, a method and a chip system of an LDO, and the technical scheme of the invention is as follows:
a stability enhancement circuit of an LDO, the LDO comprising an error op-amp, the error op-amp having a first node at an output, the stability enhancement circuit being connected to the first node; the stability enhancement circuit has only one connection point with the LDO, namely the first node; the stability enhancing circuit comprises a voltage detecting element and an impedance self-adaptive adjusting element, wherein the voltage detecting element is used for detecting the voltage at the first node, the impedance self-adaptive adjusting element is used for providing a compensation resistor, and the impedance self-adaptive adjusting element is used for adaptively adjusting the resistance value of the compensation resistor provided by the impedance self-adaptive adjusting element according to the detected voltage at the first node, so that the output impedance at the first node is adaptively adjusted, and the stability of the LDO under light load is improved.
The voltage detection element is composed of an NMOS transistor M N2 NMOS transistor M N3 NMOS transistor M N4 Realizing; the NMOS transistor M N3 Connected to a current source I B And the NMOS transistor M N2 Between them; through a current source I B For the NMOS crystalBody tube M N2 Providing a bias current to make the NMOS transistor M N2 Is equal to the voltage at the first node; the NMOS transistor M N3 For giving said NMOS transistor M N4 Providing a bias voltage; the NMOS transistor M N4 And connecting the first node.
The compensation resistor provided by the impedance adaptive adjusting element is formed by the NMOS transistor M operating in the saturation region N4 Realizing; the NMOS transistor M N4 When the voltage at the first node is detected to change, the resistance value of the compensation resistor provided by the first node is adaptively adjusted, so that the output impedance at the first node is adaptively adjusted.
The stability enhancing circuit further comprises a resistor R S1 The resistance R S1 Connected to the NMOS transistor M N4 Between the first node and the resistor R S1 For compensating errors in process manufacturing.
Resistance R of the compensation resistor C Approximately equal to
Wherein->
For the NMOS transistor M N3 And the NMOS transistor M N4 Ratio of the aspect ratio, +.>
For the NMOS transistor M N3 Is a transconductance of the first pair.
In the case of a heavy load, the stability enhancement circuit is stripped from the first node, at which time the stability enhancement circuit is not connected into the LDO circuit, without affecting the stability of the LDO circuit during the heavy load.
In the case of light load, the output impedance at the first node is reduced by the stability enhancing circuit, pushing the pole contributed at the first node to high frequency while reducing the GBW of the loop.
The error op-amp includes: PMOS transistor M P11 PMOS transistor M P12 NMOS transistor M N11 And NMOS transistor M N12 Wherein the PMOS transistor M P11 Is connected with the reference voltage V REF The PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 Is connected with the drain of the NMOS transistor M N11 The source electrode of the transistor is grounded; the PMOS transistor M P11 Source of (d) and the PMOS transistor M P12 Is connected to the source of the PMOS transistor M and is connected to the low-voltage power supply AVDD P12 Is connected to the drain of the NMOS transistor M N12 Is connected with the drain of the NMOS transistor M N12 The source electrode of the NMOS transistor M is grounded N12 Gate of (d) and the NMOS transistor M N11 Gate connection of the PMOS transistor M P12 The gate of the PMOS transistor M is connected to the feedback point of the LDO circuit P12 Is connected to the drain of the NMOS transistor M N12 A second node is arranged between the drains of the first and second transistors, and the second node is connected with the first node; the NMOS transistor M N12 Gate of (d) and the NMOS transistor M N11 A third node between the gates of the PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 A fourth node is arranged between the drains of the first and second transistors, and the third node is connected with the fourth node.
A method of enhancing the stability of an LDO, implemented with a stability enhancing circuit as described in any of the above, the method comprising:
detecting voltage information of a first node at an error operational amplifier output end of the LDO circuit;
according to the detected voltage information of the first node, the resistance value of a compensation resistor connected to the first node is adaptively adjusted, so that the output impedance of the first node is adaptively adjusted to improve the stability of the LDO circuit.
A chip system comprising an LDO comprising a stability enhancement circuit of any of the LDOs described above; or the LDO is realized by adopting any one of the stability enhancement methods of the LDO.
The stability enhancing circuit of the LDO can reduce GBW of the LDO loop, remarkably improve stability of the LDO loop under light load, and does not need to increase extra power consumption while improving the stability. The stability enhancing circuit is simple in structure, can be suitable for different LDO circuits, is favorable for realizing miniaturization of chips, greatly increases application scenes of the LDO circuits, and has other beneficial effects obtained from specific embodiments.
Drawings
For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without the need for inventive labour for a person skilled in the art;
FIG. 1 is a schematic diagram of an LDO circuit according to a first embodiment of the present disclosure;
FIG. 2 is a block diagram of an LDO circuit employing an LDO stability enhancement circuit and method according to a second embodiment of the present application;
fig. 3 is a block diagram of an LDO circuit applying a stability enhancing circuit and method of the third embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the transistor referred to in the embodiments of the present application may be a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor (may be simply referred to as a MOS transistor).
The technical scheme of the application can be applied to various subsystems or systems powered by LDO. For example, the technical solution of the present application may be applied to Radio Frequency (RF) transceivers, digital-to-Analog converters (DACs), analog-to-Digital Converter (ADCs), high-speed Digital circuits (e.g., system-on-chip SoC), phase-locked loops (PLL), and the like, which are powered by LDOs.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that: error op-amp, buffer stage, driver stage, load in the LDO circuit of the present application may also take other forms of structure besides the embodiments of the present application. For the purpose of illustrating the working principle and process of the present invention, the following discussion is based on the circuit structure of the embodiments of the present application, but those skilled in the art will recognize that the technical effects of the present application can be achieved by using error op-amps, buffer stages, driving stages, and loads with other structures as well.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an operation principle of an LDO circuit applying an LDO stability enhancing circuit and method according to a first embodiment of the present application.
As shown in fig. 1, the LDO circuit includes an error amplifier (error amplifier), a Buffer Stage (Buffer), a Driver Stage (Driver Stage), and a load. The error operational amplifier is connected with the buffer stage, the buffer stage is connected with the driving stage, and the driving stage is connected with the load.
Preferably:
the error op-amp includes an error amplifier.
The buffer stage includes a PMOS transistor M P1 And NMOS transistor M N1 。
The driving stage comprises a PMOS power tube M PWR Feedback resistor R F1 And a feedback resistor R F2 。
The input anode of the error amplifier is connected with the reference voltage V REF The input negative electrode is connected with a loop feedback signal.
The PMOS transistor M P1 Is connected with the input voltage V IN Drain is connected with the NMOS transistor M N1 The drain electrode of the PMOS power tube M is connected with the grid electrode PWR Is formed on the substrate. The NMOS transistor M N1 The source electrode of the error amplifier is grounded, and the grid electrode is connected to the output end of the error amplifier. The NMOS transistor M N1 A node A is arranged between the grid electrode of the error amplifier and the output end of the error amplifier, and a parasitic capacitance C is arranged at the node A A . The PMOS transistor M P1 Gate of (c) and the PMOS power tube M PWR Is a gate of (2)With a node B therebetween, with parasitic capacitance C at the node B B And an insertion resistor R B 。
PMOS power tube M of the driving stage PWR Is connected with the input voltage V IN The drain electrode is connected with the feedback resistor R F1 Is one end of the feedback resistor R F1 Is connected with the other end of the feedback resistor R F2 Is one end of the feedback resistor R F2 The other end of which is grounded. The feedback resistor R F1 And the feedback resistor R F2 And the input cathode of the error amplifier is connected with the feedback point F. The PMOS power tube M PWR And the drain of the feedback resistor R F1 A node O is also arranged between the one ends of the two voltage sources, and is connected with the output voltage V LDO。
The load is connected to the output voltage V LDO 。
For the LDO circuit described above, before the adaptive pole-zero compensation circuit provided herein is not set:
when the output voltage V of the output node O LDO When the voltage is higher, the voltage V at the feedback point F F And also increases, since the feedback point F is connected to the input negative electrode of the error amplifier, the output voltage V of the error amplifier is caused A Reduced so as to flow through the NMOS transistor M N1 And the PMOS transistor M P1 The PMOS power tube M is reduced in current PWR The output current of (2) is also reduced, and finally the output voltage V is obtained LDO Decreasing, returning to normal values; when the output voltage V of the output node O LDO At low level, contrary to the above situation, the negative feedback loop enables the PMOS power tube M PWR The output current of (2) increases, eventually resulting in an output voltage V LDO Rise and return to normal. Through the above process, the negative feedback loop can make the output voltage V LDO Stabilize at a fixed value, at this time, V LDO 
V REF />
（1+R F1 /R F2 ）。
When the LDO circuit is applied to the Case of Case1 mentioned in the background art, it has good stability under both light load and heavy load.
However, when it is applied to cases such as Case 3 and Case 4 mentioned in the background art, the output impedance R due to the pole and error op-amp at node a A And parasitic capacitance C at node A A Output impedance R of the correlated and error operational amplifier A Inversely proportional to the square root of the static bias current of the error op-amp, it is difficult to push the pole at node a to high frequencies without increasing power consumption. In addition, there is an insertion resistance R at node B B Also, some quiescent current needs to be consumed, so that the quiescent power consumption of the LDO cannot be further reduced. Therefore, in the application scenario of ultra-low quiescent current such as Case 3 and Case 4, the stability problem at light load is highlighted.
In order to solve the above problem, the present application further provides a stability enhancing circuit in the LDO circuit, see the dashed box of fig. 1.
The stability enhancing circuit is connected to the output end of the error operational amplifier and the NMOS transistor M N1 Is defined (node a).
The stability enhancing circuit comprises a voltage detecting element (or expressed as a voltage detecting circuit) and an impedance self-adapting regulating element (or expressed as an impedance self-adapting regulating circuit), wherein the voltage detecting element is used for detecting the voltage of the node A, and the impedance self-adapting regulating element is used for tracking the working state of the LDO circuit according to the detected voltage of the node A and self-adapting regulating the compensating resistor R provided by the LDO circuit C Therefore, the impedance at the node A is adaptively adjusted to improve the stability of the LDO circuit under light load.
Specifically:
under the condition of light load, the load current is reduced, the current flowing through the buffer stage is reduced under the control of the LDO loop, and the voltage of the node B is increased at the same time, so that the PMOS power tube M PWR Is reduced by the output current of (a)The voltage detection element detects the voltage reduction of the node A, and the impedance adaptive adjustment element adjusts the compensation resistor R provided by the voltage detection element C So that the compensation resistor R C The resistance of the LDO loop is reduced, so that the output impedance at the node A is reduced, and the stability of the LDO loop is improved.
Under the condition of heavy load, the load current is increased, the current flowing through the buffer stage is increased under the control of the LDO loop, and the voltage of the node B is reduced, so that the PMOS power tube M PWR The voltage detection element detects the voltage increase of the node A, and the impedance adaptive adjustment element adjusts the compensation resistor R provided by the voltage detection element C So that the compensation resistor R C The stability enhancing circuit is equivalent to an open circuit, is not connected into the LDO circuit, does not influence the output impedance at the node A, and does not influence the stability of the LDO loop.
Therefore, the voltage detection element and the impedance self-adaptive regulating element are added at the output end (node A) of the error operational amplifier, the voltage at the node A is detected through the voltage detection element, the working state of the LDO is tracked, and the compensation resistor R is provided for the LDO through the impedance self-adaptive regulating element C The resistance value of (a) is adjusted, so that the output impedance at the node A is adjusted, the stability in light load is improved, and additional power consumption is not required to be increased.
Second embodiment
Further, fig. 2 provides a second embodiment of the present application, which provides a specific implementation of the stability enhancing circuit based on the first embodiment of the present application.
As shown in fig. 2, the stability enhancing circuit includes: NMOS transistor M N2 NMOS transistor M N3 And NMOS transistor M N4 。
Wherein the NMOS transistor M N3 Is connected with a current source I B Current source I B Is connected with a low-voltage power supply AVDD. The NMOS transistor M N3 Is connected with the source of the NMOS transistor M N2 The drain of the NMOS transistor M N2 Is connected with the source electrode of (C)And (3) ground. The NMOS transistor M N3 Source of (d) and the NMOS transistor M N2 A node C is arranged between the drains of the NMOS transistors M N2 Is connected to the node C. The NMOS transistor M N3 Gate of (d) and the NMOS transistor M N4 Is connected with the gate of the NMOS transistor M N3 Gate of (d) and the NMOS transistor M N4 A node D is arranged between the gates of the NMOS transistors M N3 Drain of (d) and current source I B At a node therebetween. The NMOS transistor M N4 The drain electrode of the NMOS transistor M is connected with a low-voltage power supply AVDD N4 Is connected to the node a.
Preferably, the stability enhancing circuit may further include a resistor R S1 The resistance R S1 Connected to the NMOS transistor M N4 Between the source of (c) and the node a. The resistor R S1 The process is mainly used for dealing with errors occurring in the process manufacturing, and is not essential.
Wherein the voltage detection element is formed by the NMOS transistor M N2 NMOS transistor M N3 NMOS transistor M N4 Resistor R S1 (resistance R) S1 Not necessarily), the compensation resistance provided by the impedance-adaptive adjusting element is implemented by the NMOS transistor M operating in the saturation region N4 Realization of the NMOS transistor M N4 The conversion of voltage to resistance can be achieved.
Specifically:
under light load, load current is reduced, and under the control of the LDO loop, voltage V of node A A Decreasing the current flowing through the buffer stage while the voltage of node B increases, so that the PMOS power tube M PWR The output current of (c) decreases.
Through a current source I B For the NMOS transistor M N2 Providing a proper bias current to make the NMOS transistor M under light load N2 And the voltage V of the node A A Equal. An NMOS transistor M is superimposed on the node C N3 The NMOS transistor M N3 For giving said NMOS transistor M N4 A bias voltage is provided.
At this time, the NMOS transistor M N2 And the NMOS transistor M N3 The voltage V generated D Constant. Due to voltage V of node A A Reduction of the NMOS transistor M N4 And the resistance R S1 Detecting the voltage V of the node A A Reducing to make the NMOS transistor M N4 The control voltage (voltage difference between nodes D, E) of (a) increases, so that the NMOS transistor M N4 The on-resistance of (a) decreases, i.e. the NMOS transistor M N4 The compensation resistance is reduced, so that the output impedance at the node A can be reduced, and the stability of the LDO loop is improved.
Preferably, to cope with the influence of variations in the manufacturing process, a resistor R of a suitable size is introduced S1 And selecting a proper value of K (where K is the NMOS transistor M N3 And the NMOS transistor M N4 Ratio of the aspect ratio of (2) to (I), which is selected from B In relation) such that the compensation resistance R C Approximately equal to
（/>
For the NMOS transistor M N3 The transconductance of (c) such that the LDO loop gain can meet circuit design and usage requirements even in certain extreme cases.
Under the condition of heavy load, load current increases, and under the control of the LDO loop, voltage V of node A A Rise to increase the current flowing through the buffer stage, and simultaneously the voltage of the node B is reduced to enable the PMOS power tube M PWR The output current of (a) increases. At this time, the NMOS transistor M N2 And the NMOS transistor M N3 The voltage V generated D Constant. The NMOS transistor M N4 And the resistance R S1 Detecting the voltage V of the node A A Rise to make the NMOS transistor M N4 The control voltage (voltage difference between nodes D, E) of the NMOS transistor M decreases N4 The on-resistance of the NMOS transistor M at this time increases N4 The LDO circuit cannot be normally conducted, which is equivalent to open circuit, and the stability enhancing circuit does not play a role and does not influence the LDO circuit.
The voltage detection element and the impedance self-adaptive regulating element are introduced at the output end (node A) of the error operational amplifier, the working state of the LDO is tracked by detecting the voltage of the node A, and the compensation resistor R is controlled C And the stability of the LDO circuit is improved during light load, and additional power consumption is not required to be increased.
Third embodiment
On the basis of the second embodiment of the application, a specific implementation manner of the error amplifier in the LDO is further provided in the third embodiment of the application.
As shown in fig. 3, the error amplifier includes: PMOS transistor M P11 PMOS transistor M P12 NMOS transistor M N11 And NMOS transistor M N12 。
Wherein the PMOS transistor M P11 Is connected with the reference voltage V REF The PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 Is connected with the drain of the NMOS transistor M N11 The source of (c) is grounded. The PMOS transistor M P11 Source of (d) and the PMOS transistor M P12 Is connected to the source of the PMOS transistor M and is connected to the low-voltage power supply AVDD P12 Is connected to the drain of the NMOS transistor M N12 Is connected with the drain of the NMOS transistor M N12 The source electrode of the NMOS transistor M is grounded N12 Gate of (d) and the NMOS transistor M N11 Gate connection of the PMOS transistor M P12 Is connected to the feedback point F.
The PMOS transistor M P12 Is connected to the drain of the NMOS transistor M N12 Is connected to said node a. The NMOS transistor M N12 Gate of (d) and the NMOS transistor M N11 Has a node O between the gates 1 . The PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 A node between the drains of (a) and said node O 1 And (5) connection.
The error amplifier of fig. 3 is implemented using a five-tube op-amp, primarily to provide loop gain. NMOS transistor M of buffer stage N1 A smaller channel length is adopted, so that the parasitic capacitance C at the node A is generated in light load A As small as possible, the pole frequency generated is relatively high. In addition, PMOS power tube M PWR And buffer stage PMOS transistor M P1 The ratio N of the width to length ratio is required to be based on the size of the load capacitor and the feedback resistor R F1 And R is F2 Is chosen to ensure that the pole at node B has less effect on the stability of the loop under light load.
In summary, the present application is implemented by introducing a voltage detection element and a compensation resistor R controlled by the LDO operating state at node A C By reducing the output impedance at the node A during light load, the pole contributed by the node A is pushed to a high frequency, the GBW of the loop is reduced, the stability of the LDO loop is obviously improved, and additional power consumption is not required to be increased while the stability is improved. The stability enhancing circuit has a simple structure, can be suitable for different LDO circuits, and is beneficial to realizing the miniaturization of chips. Even if the LDO works under the condition of ultralow static bias, the loop can be stable, and no influence is caused under the heavy load condition, so that the application scene of the LDO circuit is greatly increased.
Based on this, embodiments also provide a chip system including an LDO including a stability enhancement circuit of any of the LDOs provided above; or the LDO is implemented using any of the stability enhancement methods of LDOs provided above.
Embodiments also provide an apparatus comprising a circuit board comprising any of the stability enhancement circuits provided above for LDO.
It should be noted that, the descriptions provided above for the LDO stability enhancement circuit/method may be incorporated into the system-on-chip or the device, and the embodiments of the present application are not repeated here.
In another aspect of the application, there is also provided a non-transitory computer readable storage medium for use with a computer having software for creating an integrated circuit, the computer readable storage medium having stored thereon one or more computer readable data structures having photomask data for manufacturing a stability enhancement circuit for an LDO provided by any of the illustrations provided above.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (10)
1. The LDO stability enhancement circuit is characterized by comprising an error operational amplifier, wherein a first node is arranged at the output end of the error operational amplifier, and the stability enhancement circuit is connected to the first node; the stability enhancement circuit has only one connection point with the LDO, namely the first node; the stability enhancing circuit comprises a voltage detecting element and an impedance self-adaptive adjusting element, wherein the voltage detecting element is used for detecting the voltage at the first node, the impedance self-adaptive adjusting element is used for providing a compensation resistor, and the impedance self-adaptive adjusting element is used for adaptively adjusting the resistance value of the compensation resistor provided by the impedance self-adaptive adjusting element according to the detected voltage at the first node, so that the output impedance at the first node is adaptively adjusted, and the stability of the LDO under light load is improved.
2. The stability enhancement circuit of claim 1, wherein the voltage detection element is formed from an NMOS die
Body tube M N2 NMOS transistor M N3 NMOS transistor M N4 Realizing; the NMOS transistor M N3 Connected to a current source I B And the NMOS transistor M N2 Between them; through a current source I B For the NMOS transistor M N2 Providing a bias current to make the NMOS transistor M N2 Is equal to the voltage at the first node; the NMOS transistor M N3 For giving said NMOS transistor M N4 Providing a bias voltage; the NMOS transistor M N4 And connecting the first node.
3. The stability enhancement circuit of claim 2 wherein the compensation resistance provided by the impedance adaptive adjustment element is provided by the NMOS transistor M operating in the saturation region N4 Realizing; the NMOS transistor M N4 When the voltage at the first node is detected to change, the resistance value of the compensation resistor provided by the first node is adaptively adjusted, so that the output impedance at the first node is adaptively adjusted.
4. The stability enhancement circuit of claim 3 wherein the stability enhancement circuit further comprises a resistor R S1 The resistance R S1 Connected to the NMOS transistor M N4 Between the first node and the resistor R S1 For compensating errors in process manufacturing.
5. The stability enhancement circuit of claim 4, wherein the compensation resistor has a resistance value R C Approximately equal to
Wherein->
For the NMOS transistor M N3 And the NMOS transistor M N4 Ratio of the aspect ratio, +.>
For the NMOS transistor M N3 Is a transconductance of the first pair.
6. The stability enhancement circuit of claim 1, wherein the stability enhancement circuit is stripped from the first node in the event of a heavy load when the stability enhancement circuit is not connected to the LDO circuit, which has no effect on the stability of the LDO circuit during heavy load.
7. The stability enhancement circuit of claim 1 wherein in the case of a light load, the output impedance at the first node is reduced by the stability enhancement circuit pushing the pole contributed at the first node to a high frequency while reducing the GBW of the loop.
8. The stability enhancement circuit of claim 1 wherein the error op-amp comprises: PMOS transistor M P11 PMOS transistor M P12 NMOS transistor M N11 And NMOS transistor M N12 Wherein the PMOS transistor M P11 Is connected with the reference voltage V REF The PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 Is connected with the drain of the NMOS transistor M N11 The source electrode of the transistor is grounded; the PMOS transistor M P11 Source of (d) and the PMOS transistor M P12 Is connected to the source of the PMOS transistor M and is connected to the low-voltage power supply AVDD P12 Is connected to the drain of the NMOS transistor M N12 Is connected with the drain of the NMOS transistor M N12 The source electrode of the NMOS transistor M is grounded N12 Gate of (d) and the NMOS transistor M N11 Gate connection of the PMOS transistor M P12 The grid electrode of (a) is connected with the feedback point of the LDO circuit, aThe PMOS transistor M P12 Is connected to the drain of the NMOS transistor M N12 A second node is arranged between the drains of the first and second transistors, and the second node is connected with the first node; the NMOS transistor M N12 Gate of (d) and the NMOS transistor M N11 A third node between the gates of the PMOS transistor M P11 Is connected to the drain of the NMOS transistor M N11 A fourth node is arranged between the drains of the first and second transistors, and the third node is connected with the fourth node.
9. A method of enhancing the stability of an LDO implemented using a stability enhancing circuit as claimed in any of claims 1-8, the method comprising:
detecting voltage information of a first node at an error operational amplifier output end of the LDO circuit;
according to the detected voltage information of the first node, the resistance value of the compensation resistor connected to the first node is adaptively adjusted, so that the output impedance of the first node is adaptively adjusted, and the stability of the LDO circuit under light load is improved.
10. A chip system, characterized in that the chip system comprises an LDO comprising a stability enhancing circuit of one of the LDOs of claims 1-8; or the LDO is implemented with a method of enhancing the stability of the LDO as claimed in claim 9.
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| US6690147B2 (en) * | 2002-05-23 | 2004-02-10 | Texas Instruments Incorporated | LDO voltage regulator having efficient current frequency compensation |
| CN101667812A (en) * | 2009-07-24 | 2010-03-10 | Bcd半导体制造有限公司 | Frequency compensation method and linear voltage stabilizer with ultra low differential pressure |
| CN202372876U (en) * | 2011-12-20 | 2012-08-08 | 上海贝岭股份有限公司 | Low-dropout linear voltage regulator with frequency compensating function |
| CN109164861A (en) * | 2018-10-31 | 2019-01-08 | 上海海栎创微电子有限公司 | A kind of low pressure difference linear voltage regulator of fast transient response |
| CN114510102A (en) * | 2021-12-30 | 2022-05-17 | 上海华力微电子有限公司 | Linear voltage stabilizer |
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