CN113064464A - High-precision low-dropout linear regulator with quick transient response - Google Patents
High-precision low-dropout linear regulator with quick transient response Download PDFInfo
- Publication number
- CN113064464A CN113064464A CN202110344620.7A CN202110344620A CN113064464A CN 113064464 A CN113064464 A CN 113064464A CN 202110344620 A CN202110344620 A CN 202110344620A CN 113064464 A CN113064464 A CN 113064464A
- Authority
- CN
- China
- Prior art keywords
- tube
- pmos
- nmos
- transistor
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
A high-precision and quick transient response low-dropout linear voltage regulator belongs to the technical field of power management. In the invention, the source electrode of the PMOS power tube is connected with the input voltage of the LDO, and the drain electrode of the PMOS power tube outputs the output voltage of the LDO and obtains feedback voltage after voltage division is carried out through a voltage division feedback network; the error amplifier processes the feedback voltage and the reference voltage and generates a grid control signal of the PMOS power tube through the dynamic frequency compensation network and the voltage buffer. The FVF structure of the error amplifier can overcome the problem that the slew rate of the traditional error amplifier is limited by a tail current source, can also improve the transconductance of input geminate transistors, and realizes the transconductance enhancement effect, thereby improving the static performances such as the load regulation rate, the linear regulation rate and the like of the LDO; meanwhile, through the use of an on-chip dynamic two-type frequency compensation technology and a feedback voltage buffer with high slew rate, the transient speed is greatly improved, and meanwhile, no ESR (equivalent series resistance) is theoretically needed for frequency compensation, so that the invention has good dynamic characteristics.
Description
Technical Field
The invention belongs to the technical field of power management, and relates to a design of a low dropout regulator, which can be used for supplying power to a circuit inside a chip.
Background
Low Dropout Regulator (Low Dropout Regulator-LDO) has the characteristics of Low cost, Low noise, simple structure, strong input noise rejection, Low power consumption, etc., and compared with a switching Regulator, the LDO becomes another important power management chip, and is widely applied to consumer electronics scenes such as portable devices. Compared with a common voltage reference, the LDO has a strong loading capability, and fig. 1 shows a conventional LDO structure with a large off-chip capacitor, which mainly comprises an Error Amplifier (EA), a power tube (MP), a feedback network, and an output filter capacitor.
The performance index of the LDO mainly includes static characteristics and dynamic characteristics. The static characteristics of the LDO mainly include a load regulation rate and a linear regulation rate, which measure the operating accuracy of the LDO, and the larger loop gain of the LDO as a feedback system usually represents higher accuracy. The LDO is used as a power supply module, and its load and linear transient performance, especially the load transient performance, are the most important dynamic characteristics.
In order to improve the transient performance of the LDO, whether to add off-chip capacitors is an important condition besides the limitation of the bandwidth and slew rate of the negative feedback loop; the off-chip load large capacitor is used as a temporary 'charge bank', and can provide or store charges during the transient period, so that the fluctuation of the output voltage is reduced; however, in terms of loop stability, the low frequency output pole caused by the off-chip filter capacitor often conflicts with the pole of the Error Amplifier (EA) output, resulting in instability of the feedback loop.
In order to solve the problem of stability of a negative feedback loop of an off-chip large capacitor LDO, the conventional off-chip large capacitor LDO is usually compensated by using a load capacitor or an extra ESR (equivalent series resistance) resistor. But the resistance value of the ESR resistor fluctuates along with the external environment; in addition, during a transient period, a current flows through the ESR, which causes a large output voltage fluctuation, and conversely, deteriorates transient performance.
Disclosure of Invention
Aiming at the problems of static and dynamic characteristics of the traditional low dropout linear regulator, the invention provides an off-chip large-capacitance type low dropout linear regulator with high precision and rapid transient characteristics, the structure of the invention can be externally hung with a 1 muF load capacitor, and simultaneously, because of the characteristics of high loop gain, large loop bandwidth, no ESR compensation resistor and the like of the low dropout linear regulator, the output voltage precision of the low dropout linear regulator is improved, the faster load transient characteristics are brought, and the static and dynamic characteristics of the low dropout linear regulator are improved.
The technical scheme of the invention is as follows:
a high-precision low-dropout linear regulator with quick transient response comprises an error amplifier, a PMOS power tube, a voltage division feedback network, a dynamic frequency compensation network and a voltage buffer;
the source electrode of the PMOS power tube is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the PMOS power tube outputs the output voltage of the low-dropout linear voltage regulator; the voltage division feedback network is used for dividing the output voltage of the low dropout linear regulator to obtain a feedback voltage;
the error amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein the third NMOS transistor and the sixth NMOS transistor have the same size, the fourth NMOS transistor and the fifth NMOS transistor have the same size and are smaller than the third NMOS transistor and the sixth NMOS transistor, and the seventh NMOS transistor and the eighth NMOS transistor have the same size;
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the feedback voltage, the source electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the eighth PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube and the reference voltage, the source electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the sixth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube;
the grid electrode of the seventh NMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode and the drain electrode of the sixth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the second PMOS tube and the source electrode of the ninth NMOS tube;
the grid electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode and the drain electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, and the drain electrode of the eighth NMOS tube is connected with the drain electrode of the third PMOS tube and the source electrode of the tenth NMOS tube;
the grid electrodes of the first NMOS tube and the second NMOS tube are both connected with a first bias voltage, and the grid electrodes of the ninth NMOS tube and the tenth NMOS tube are both connected with a second bias voltage;
the grid electrode of the tenth PMOS tube is connected with the grid electrode and the drain electrode of the ninth PMOS tube and the drain electrode of the ninth NMOS tube, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube and serves as the output end of the error amplifier;
the source electrodes of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are all connected with the input voltage of the low dropout linear regulator, and the source electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all grounded;
the input end of the voltage buffer is connected with the output end of the error amplifier, and the output end of the voltage buffer is connected with the grid electrode of the PMOS power tube;
the dynamic frequency compensation network comprises an eleventh PMOS (P-channel metal oxide semiconductor) tube, a twelfth PMOS tube, an eleventh NMOS (N-channel metal oxide semiconductor) tube, a first capacitor and a first resistor;
the grid electrode of the eleventh PMOS tube is connected with the drain electrode of the twelfth PMOS tube and the source electrode of the eleventh NMOS tube, the source electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube and is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the eleventh PMOS tube is in short circuit with the substrate and is connected with one end of the first resistor;
the grid electrode of the twelfth PMOS tube is connected with a third bias voltage;
the grid electrode of the eleventh NMOS tube is connected with the output end of the error amplifier, passes through the first capacitor and then is connected with the other end of the first resistor, and the drain electrode of the eleventh NMOS tube is grounded.
Specifically, the voltage buffer comprises a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a second resistor, a third resistor, a second capacitor and a third capacitor, wherein the thirteenth PMOS transistor and the fourteenth PMOS transistor have the same size;
the grid electrode of the eighteenth PMOS tube is connected with one end of a third resistor and is connected with the input voltage of the low dropout linear regulator after passing through a third capacitor, and the drain electrode of the eighteenth PMOS tube is connected with the other end of the third resistor, the grid electrode of the seventeenth PMOS tube and the drain electrode of the fourteenth NMOS tube;
the grid electrode of the fourteenth NMOS tube is connected with the second bias voltage, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube and the drain electrode of the fifteenth NMOS tube;
the grid electrode of the sixteenth PMOS tube is connected with the third bias voltage, and the drain electrode of the sixteenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube, the drain electrode of the thirteenth NMOS tube, the grid electrode and the drain electrode of the fifteenth PMOS tube and the drain electrode of the seventeenth PMOS tube and is connected with the output end of the voltage buffer;
the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube and connected with the input end of the voltage buffer, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and the grid electrode of the thirteenth NMOS tube, and is grounded after passing through the second resistor and the second capacitor in sequence;
the grid electrodes of the twelfth NMOS tube and the fifteenth NMOS tube are connected with the output voltage of the low dropout linear regulator, the source electrodes of the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube and the eighteenth PMOS tube are all connected with the input voltage of the low dropout linear regulator, and the source electrodes of the twelfth NMOS tube, the thirteenth NMOS tube and the fifteenth NMOS tube are all grounded.
Specifically, a transient enhancement high-pass network is further arranged before the gates of a twelfth NMOS transistor and a fifteenth NMOS transistor in the voltage buffer are connected with the output voltage of the low dropout linear regulator, and the transient enhancement high-pass network comprises a fourth resistor and a fourth capacitor; one end of a fourth resistor is connected with the first bias voltage, and the other end of the fourth resistor is connected with one end of a fourth capacitor and the grids of a twelfth NMOS tube and a fifteenth NMOS tube; the other end of the fourth capacitor is connected with the output voltage of the low dropout regulator.
Specifically, the size of the eleventh NMOS transistor is equal to the size of the thirteenth PMOS transistor and the fourteenth PMOS transistor.
Specifically, the low dropout regulator further comprises a bias module for generating the first bias voltage, the second bias voltage and the third bias voltage, wherein the bias module comprises a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor and an eighteenth NMOS transistor;
the grid electrode of the twentieth PMOS tube is connected with the grid electrode and the drain electrode of the nineteenth PMOS tube, the grid electrode of the twenty-first PMOS tube and the bias current and generates a third bias voltage, the source electrode of the twentieth PMOS tube is connected with the source electrode of the nineteenth PMOS tube and the source electrode of the twenty-first PMOS tube and is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the twentieth PMOS tube is connected with the grid electrode and the drain electrode of the sixteenth NMOS tube and generates a first bias voltage;
the grid electrode and the drain electrode of the eighteenth NMOS tube are connected with the grid electrode of the seventeenth NMOS tube and the drain electrode of the twenty-first PMOS tube and generate the second bias voltage, and the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the seventeenth NMOS tube;
and the source electrodes of the sixteenth NMOS tube and the seventeenth NMOS tube are grounded.
Specifically, the size of the seventh NMOS transistor is the sum of the sizes of the third NMOS transistor and the fourth NMOS transistor.
The invention has the beneficial effects that: the low dropout linear regulator provided by the invention controls the power consumption and simultaneously greatly improves the transconductance of the error amplifier through a transconductance enhancement technology, thereby improving the loop gain of the LDO, and further improving the static performances such as the load regulation rate and the linear regulation rate of the LDO; meanwhile, through the use of an on-chip dynamic two-type frequency compensation technology and a feedback voltage buffer with high slew rate, the transient speed is greatly improved, and meanwhile, no ESR (equivalent series resistance) is theoretically needed for frequency compensation, so that the invention has good static and dynamic characteristics.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a structural diagram of a conventional off-chip large capacitor LDO.
Fig. 2 is a topology structure diagram of a high-precision fast transient response low dropout regulator according to the present invention.
Fig. 3 is a transistor-level schematic diagram of a high-precision fast transient response low dropout regulator according to the present invention.
Fig. 4 is a circuit diagram of an implementation of a bias module in a high-precision fast transient response low dropout regulator according to the present invention.
Fig. 5 is a schematic diagram of the frequency response of a high-precision fast transient response low dropout regulator according to the present invention.
Fig. 6 is a simulated waveform diagram of the transient response of the load in some embodiments of the high-precision fast transient response low dropout linear regulator of the present invention.
Fig. 7 is a simulated waveform diagram of the transient response of the load in other embodiments of the high-precision fast transient response low dropout linear regulator according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a high-precision fast transient response low dropout linear regulator, which comprises an error amplifier, a PMOS (P-channel metal oxide semiconductor) power tube MP, a voltage division feedback network, a dynamic frequency compensation network and a voltage buffer, wherein as shown in figure 3, the source electrode of the PMOS power tube MP is connected with the input voltage VIN of the low dropout linear regulator, and the drain electrode thereof outputs the output voltage V of the low dropout linear regulatorOUT(ii) a Voltage dividing feedback network for applying output voltage V of low dropout linear regulatorOUTAfter voltage division, feedback voltage V is obtainedFBAnd fed to the error amplifier.
As shown in FIG. 3, the error amplifier of the present invention includes a first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M11And the fourth NMOS tube M12The fifth NMOS transistor M13And a sixth NMOS transistor M14And a seventh NMOS transistor M15And the eighth NMOS transistor M16And a ninth NMOS transistor M17The tenth NMOS transistor M18The first PMOS transistor M3A second PMOS transistor M4And the third PMOS transistor M5And the fourth PMOS transistor M6The fifth PMOS transistor M7Sixth PMOS transistor M8Seventh PMOS transistor M9Eighth PMOS transistor M10Ninth PMOS transistor M19And a tenth PMOS transistor M20Wherein the third NMOS transistor M is made11And a sixth NMOS transistor M14Are of equal size and are all alpha, and a fourth NMOS transistor M12And a fifth NMOS transistor M13Are equal in size and are all beta, and a seventh NMOS transistor M15And an eighth NMOS transistor M16Are equal in size; first PMOS transistor M3The grid electrode of the transistor is connected with a second PMOS transistor M4Gate and feedback voltage VFBThe source electrode of the PMOS transistor is connected with a third PMOS tube M5Source electrode and fifth PMOS transistor M7The drain electrode of the transistor is connected with the first NMOS tube M1Drain electrode of (1), fifth PMOS tube M7Grid and eighth PMOS transistor M10A gate electrode of (1); fourth PMOS transistor M6The grid electrode of the transistor is connected with a third PMOS transistor M5Gate of (2) and reference voltage VREFThe source of which is connected toTwo PMOS tube M4Source electrode and sixth PMOS transistor M8The drain electrode of the first NMOS tube M is connected with the drain electrode of the second NMOS tube M2Drain electrode of (1), sixth PMOS tube M8Grid and seventh PMOS tube M9A gate electrode of (1); seventh NMOS transistor M15The grid electrode of the transistor is connected with an eighth PMOS tube M10Drain electrode of (1), fourth NMOS tube M12Grid electrode of (1), fifth NMOS tube M13Drain electrode of (1) and sixth NMOS transistor M14The drain electrode of the first PMOS tube M is connected with the grid electrode and the drain electrode of the second PMOS tube M4Drain electrode of (1) and ninth NMOS transistor M17A source electrode of (a); eighth NMOS transistor M16The grid electrode of the transistor is connected with a seventh PMOS tube M9Drain electrode of (1), third NMOS tube M11Grid and drain of the transistor, and a fourth NMOS transistor M12Drain electrode of and the fifth NMOS transistor M13The drain electrode of the grid electrode is connected with a third PMOS tube M5Drain electrode of (1) and tenth NMOS transistor M18A source electrode of (a); first NMOS transistor M1And a second NMOS transistor M2Are all connected with a first bias voltage VBNNinth NMOS transistor M17And a tenth NMOS transistor M18Are all connected with a second bias voltage VBN2(ii) a Tenth PMOS tube M20The grid electrode of the first PMOS tube is connected with a ninth PMOS tube M19Gate and drain of (1) and ninth NMOS transistor M17The drain electrode of the transistor is connected with the tenth NMOS tube M18And as the output of the error amplifier; fifth PMOS transistor M7Sixth PMOS transistor M8Seventh PMOS transistor M9Eighth PMOS transistor M10Ninth PMOS transistor M19And a tenth PMOS transistor M20The source electrodes of the NMOS transistors are connected with the input voltage VIN of the low dropout linear regulator, and the first NMOS transistor M1A second NMOS transistor M2And the third NMOS transistor M11And the fourth NMOS tube M12The fifth NMOS transistor M13And a sixth NMOS transistor M14And a seventh NMOS transistor M15And an eighth NMOS transistor M16Are all grounded.
The error amplifier provided by the invention comprises three parts, namely an input pair unit, a transconductance enhancement structure and a folding sleeve output stage, wherein in the input pair unit of the error amplifier, an input pair transistor is a second PMOS transistor M4And a third PMOS transistor M5Second PMOS transistor M4And thirdPMOS tube M5The load of (1) is composed of a dynamically biased folded Voltage Follower (FVF structure), and the FVF structure comprises a first NMOS tube M1The first PMOS transistor M3The fifth PMOS transistor M7And a second NMOS transistor M2A second PMOS transistor M4And the fourth PMOS transistor M6Compared with the traditional common differential structure, the FVF structure can not only overcome the problem that the slew rate of EA is limited by a tail current source, but also improve the transconductance of input geminate transistors; in addition, tail tube (i.e. fifth PMOS tube M) of FVF structure is used7And a sixth PMOS transistor M8) Equivalently sampling a second PMOS tube M of the input pair tubes4And a third PMOS transistor M5The characteristics of AC (alternating current) information, and the seventh PMOS tube M is reused9And eighth PMOS transistor M10Carrying out mirror image and simultaneously utilizing a third NMOS tube M11And the fourth NMOS tube M12The fifth NMOS transistor M13And a sixth NMOS transistor M14The negative resistance of the latch structure (i.e. the equivalent AC resistance with opposite phase to the common resistance due to the positive feedback) amplifies the mirrored AC current and then passes through the seventh NMOS transistor M15And an eighth NMOS transistor M16Mirror these two AC currents with the common input pair transistor second PMOS transistor M4And a third PMOS transistor M5The AC currents are superimposed and summed together at the output node of the EA, thereby achieving the transconductance enhancement effect.
It is noted that all nodes of the transconductance enhancement path are low-impedance nodes, and the third NMOS transistor M is effectively adjusted11And the fourth NMOS tube M12The fifth NMOS transistor M13And a sixth NMOS transistor M14And a seventh NMOS transistor M15And the eighth NMOS transistor M16The values of a and β of the transistor sizes are equal, so that a transconductance enhancement effect and a frequency band of a parasitic pole can be balanced, and the EA is represented as a transconductance amplifier (OTA) with high transconductance and high bandwidth, and the transconductance and the gain of the EA can be simply expressed as:
Adc_EA≈GMEAro20
let the third NMOS transistor M11And a sixth NMOS transistor M14The size alpha of the NMOS transistor is larger than that of the fourth NMOS transistor M12And a fifth NMOS transistor M13The dimension beta ensures that the lacth structure as a whole still has positive resistance (namely, the third NMOS tube M)11And a sixth NMOS transistor M14The fourth NMOS transistor M is a positive resistor12And a fifth NMOS transistor M13Exhibiting negative resistance). Specific values of a and β are considered as follows, the closer β is to a, and VB in fig. 31Node and VB2The higher the AC impedance of the node, and thus the greater the magnitude of the transconductance enhancement, but now at VB for the signal path1Node and VB2The bandwidth of two nodes is smaller, so that the transconductance enhancement and the bandwidth compromise need to be considered. Let the seventh NMOS transistor M15And an eighth NMOS transistor M16Has a size of k, and VB if a and β are smaller compared to the value of k1Node and VB2The lower the bandwidth (i.e., the frequency of the equivalent pole) at the node is, the lower k may be, alpha + β or another ratio, and since the parasitic pole is often required to be larger than the loop bandwidth of the LDO, the influence on the signal transmission speed and the loop stability is avoided, so that the selection may be performed according to the loop bandwidth requirement of the specific LDO.
Output signal V of error amplifierEAOThe grid electrode of the PMOS power tube MP is connected after passing through the voltage buffer. The voltage buffer can be implemented by the simplest source follower, and can also adopt the basic structure of a super source follower, and fig. 3 shows an implementation circuit of the embodiment in which the voltage buffer adopts the super source follower structure, and the implementation circuit comprises a thirteenth PMOS transistor M24Fourteenth PMOS transistor M25Fifteenth PMOS transistor M28Sixteenth PMOS tube M29Seventeenth PMOS transistor M30Eighteenth PMOS tube M31Twelfth NMOS tube M26Thirteenth NMOS transistor M27Fourteenth NMOS transistor M32Fifteenth NMOS transistor M33A second resistor R2A third resistor R3A second capacitor C2And thirdCapacitor C3Wherein the thirteenth PMOS transistor M24And a fourteenth PMOS transistor M25Are equal in size; eighteenth PMOS tube M31Is connected with a third resistor R3And through a third capacitor C3The input voltage VIN of the low-dropout linear regulator is connected at the back, and the drain electrode of the low-dropout linear regulator is connected with a third resistor R3Another end of the seventeenth PMOS transistor M30Gate of (1) and fourteenth NMOS transistor M32A drain electrode of (1); fourteenth NMOS tube M32Is connected to a second bias voltage VBN2The source electrode of the transistor is connected with a thirteenth PMOS tube M24Drain electrode of (1) and a fifteenth NMOS tube M33A drain electrode of (1); sixteenth PMOS tube M29Is connected to a third bias voltage VBPThe drain electrode of the transistor is connected with a thirteenth PMOS tube M24Source electrode, fourteenth PMOS tube M25Source electrode of (1), thirteenth NMOS tube M27Drain electrode of (1), fifteenth PMOS tube M28Gate and drain of the transistor and a seventeenth PMOS transistor M30The drain electrode of the first transistor is connected with the output end of the voltage buffer in parallel; fourteenth PMOS tube M25Grid electrode of the transistor is connected with a thirteenth PMOS tube M24The grid of the transistor is connected in parallel with the input end of the voltage buffer, and the drain of the transistor is connected with a twelfth NMOS transistor M26Drain electrode of (1), thirteenth NMOS tube M27And then through the second resistor R2And a second capacitor C2Then grounding; twelfth NMOS tube M26And a fifteenth NMOS transistor M33Grid electrode of the low dropout regulator is connected with the output voltage VOUTFifteenth PMOS transistor M28Sixteenth PMOS tube M29Seventeenth PMOS transistor M30And eighteenth PMOS transistor M31The source electrodes of the first and second NMOS transistors are connected with the input voltage VIN of the low dropout linear regulator26Thirteenth NMOS transistor M27And a fifteenth NMOS transistor M33Are all grounded.
In this embodiment, the voltage Buffer adopts a basic structure of a super-source follower, and an Adaptive transistor (Adaptive transistor) that can mirror the current of the power transistor, that is, a fifteenth PMOS transistor M, is added on the basis of the basic structure28Fifteenth PMOS transistor M28The PMOS power tube MP gate end capacitor can be charged during the period that the load jumps from heavy load to light load, and the charge is carried outCan dynamically change the thirteenth NMOS tube M27The magnitude of the current (small signal transconductance) enables the Buffer to push the pole of the grid end of the power tube to a higher frequency by utilizing a negative feedback loop of the Buffer under heavy load.
Compared with the traditional super source follower, the Buffer not only has a path for rapidly discharging the grid-end capacitor of the power tube (namely M)25-M26-M27) Also by M24-M32-M31-M30When the loop jumps from heavy load to light load, EA output is turned high, and then a seventeenth PMOS tube M is pulled low30The gate voltage of the LDO is higher than that of the gate end of the power tube, so that the parasitic capacitance of the gate end of the power tube is charged, and the transient speed of the LDO when the LDO jumps from a heavy load to a light load is greatly improved.
The dynamic frequency compensation network arranged at the output of EA adopts dynamic two-type compensation, as shown in figure 3, the dynamic frequency compensation network comprises an eleventh PMOS tube M21Twelfth PMOS tube M22Eleventh NMOS transistor M23A first capacitor C1And a first resistor R1(ii) a Eleventh PMOS tube M21The grid electrode of the transistor is connected with a twelfth PMOS tube M22Drain electrode of (1) and eleventh NMOS transistor M23Source electrode of the transistor, the source electrode is connected with a twelfth PMOS tube M22The source of the low-dropout linear regulator is connected with an input voltage VIN of the low-dropout linear regulator, and the drain of the low-dropout linear regulator is in short circuit with the substrate and is connected with one end of the first resistor; twelfth PMOS tube M22Is connected to a third bias voltage VBP(ii) a Eleventh NMOS transistor M23Is connected to the output of the error amplifier and passes through a first capacitor C1Rear connection first resistor R1And the other end of the second transistor, the drain of which is grounded.
In the dynamic frequency compensation network, a twelfth PMOS tube M of a source follower is utilized22And an eleventh NMOS transistor M23Thirteenth PMOS tube M of input tube for simulating real voltage Buffer24And a fourteenth PMOS transistor M25The source-follower effect on the MP gate terminal of the PMOS power transistor is due to the eleventh NMOS transistor M in some embodiments23As the source follower, it is preferable to make the eleventh NMOS transistor M23Size of and thirteenth PMOS tube M24And a fourteenth PMOS transistor M25Are equal in size in the second placeEleven NMOS tubes M23Thirteenth PMOS transistor M24And a fourteenth PMOS transistor M25Taking the same bias current, the eleventh NMOS transistor M23The source end successfully mirrors the information of the gate end of the PMOS power tube MP due to the dynamic compensation resistor (namely the eleventh PMOS tube M)21The channel resistance) bypasses a power tube gate end with a large parasitic capacitance, so that the dynamic compensation resistance can be quickly established in a transient period, and the stability and transient characteristic of a loop are improved; besides, the eleventh NMOS transistor M can be correspondingly selected according to the loop bandwidth of the LDO23Compared with the thirteenth PMOS transistor M24And a fourteenth PMOS transistor M25The size of (c). It is noted that the eleventh PMOS transistor M is controlled in the present invention21The eleventh PMOS transistor M of the AC channel equivalent resistance Rds _ on21The substrate and the drain terminal of the low dropout linear regulator are shorted together, so that the low dropout linear regulator is connected from the input voltage VIN to the first resistor R at the end of the load jumping from heavy load to light load1The upper PN junction can be used for compensating the capacitor, namely the first capacitor C1And the charge is replenished, so that the recovery process of the internal node voltage of the circuit at the end stage of the load step transient is greatly accelerated.
Second resistor R in voltage buffer2And a second capacitor C2And a third resistor R3And a third capacitance C3Two resistance-capacitance networks are formed for compensating the sub-loop in the voltage buffer, and a second resistor R2And a second capacitor C2The purpose of (1) is to maintain the stability of the negative feedback loop in the voltage buffer itself; and a third resistor R3And a third capacitance C3The purpose of the method is to rapidly charge the grid end capacitor of the power tube when the load is switched from heavy load to light load. In some embodiments, a transient enhanced high-pass network is further introduced, as shown in fig. 3, and the transient enhanced high-pass network comprises a fourth resistor R4And a fourth capacitance C4(ii) a A fourth resistor R4One end of the first bias voltage is connected with a first bias voltage VBNThe other end is connected with a fourth capacitor C4And a twelfth NMOS tube M26And a fifteenth NMOS transistor M33A gate electrode of (1); fourth capacitor C4Another end of (a) is connected toOutput voltage V connected to low dropout regulatorOUT. A fourth resistor R4And a fourth capacitance C4The high-pass path is introduced by the network, so that the ripple signal of the output voltage of the LDO can bypass EA through the coupling effect and directly pass through the twelfth NMOS tube M26And the fifteenth NMOS transistor M33The working state of the voltage buffer is adjusted, and the transient response speed of the LDO is improved to a certain extent.
First bias voltage VBNA second bias voltage VBN2And a third bias voltage VBPCan be provided externally or can be generated by arranging a bias module, and as shown in fig. 4, the invention provides a method for generating the first bias voltage VBNA second bias voltage VBN2And a third bias voltage VBPThe bias module comprises a nineteenth PMOS transistor MB1Twentieth PMOS transistor MB2Twenty-first PMOS transistor MB3Sixteenth NMOS transistor MB4Seventeenth NMOS transistor MB5And eighteenth NMOS transistor MB6(ii) a Twentieth PMOS tube MB2The grid electrode of the transistor is connected with a nineteenth PMOS tube MB1The grid electrode and the drain electrode of the PMOS transistor M, and a twenty-first PMOS transistor MB3And a bias current IINAnd generates a third bias voltage VBPThe source electrode of the transistor is connected with a nineteenth PMOS tube MB1Source electrode and twenty-first PMOS tube MB3The source of the low dropout linear regulator is connected with the input voltage VIN of the low dropout linear regulator, and the drain of the low dropout linear regulator is connected with the sixteenth NMOS tube MB4And generates a first bias voltage VBN(ii) a Eighteenth NMOS tube MB6The grid and the drain of the transistor are connected with a seventeenth NMOS transistor MB5Grid and twenty-first PMOS transistor MB3And generates a second bias voltage VBN2The source electrode of the transistor is connected with a seventeenth NMOS transistor MB5A drain electrode of (1); sixteenth NMOS tube MB4And seventeenth NMOS transistor MB5Are all grounded. Bias current I of bias module in this embodimentINThrough a nineteenth PMOS tube MB1Twentieth PMOS transistor MB2Twenty-first PMOS transistor MB3Current mirror and sixteenth NMOS transistor MB4Seventeenth NMOS transistor MB5And eighteenth NMOS transistor MB6The use of the MOS tube with equal diode connection can obtain the required first bias voltage VBNA second bias voltage VBN2And a third bias voltage VBP。
As can be seen in conjunction with the topology of fig. 2, the transfer function of the LDO negative feedback loop can be approximately expressed as:
wherein Loop _ gain is the open Loop gain of the whole LDO, gmEAIs the equivalent transconductance of the Error Amplifier (EA), ro1Is the equivalent output impedance of the error amplifier, gmPIs the equivalent transconductance, R, of the PMOS power tube MPLIs equivalent parallel resistance of load resistance and power tube channel resistance, RZAnd CZTwo type of compensation parameter for the output of the error amplifier, CLIs an externally hung load large capacitor, RESRFor loading large capacitance CLEquivalent series parasitic resistance of (1), Cp1Equivalent parasitic capacitance, GBW, for the error amplifier output to AC groundBUFIs GBW of the internal feedback loop of the voltage Buffer (Buffer), which is also the pole of the gate terminal of the PMOS power transistor MP, and Wnd2_BUFIs a high-frequency parasitic pole inside the Buffer.
Only an output pole of the EA and an output pole of the LDO are always arranged in the feedback loop, and a fast following zero introduced by the dynamic two-type compensation network compensates a secondary pole in the loop GBW, so that the loop stability (150 mA-0A) of the LDO under the steady state and the transient state of all loads is ensured. In addition, it is worth noting that the replacement of the major and minor poles is adopted in the loop, and the R is caused under heavy loadLSmaller, the EA output pole becomes the dominant pole, R is under light loadLThe output pole of the LDO is used as the dominant pole, so that the size of EA output compensation capacitor and resistor can be reduced, and the chip area is saved.
Fig. 5 is a diagram of loop frequency response characteristics of the LDO under different loads, and it can be seen that the LDO has a larger bandwidth (3MHz) under a heavy load and ensures good stability under a full load.
The feedback network is composed of two feedback resistors RF1And RF2Composition, assuming large feedback gain, output voltage VOUTThe steady state value of (d) may be expressed as:
fig. 6 and fig. 7 respectively show transient simulation waveforms when the LDO performs load switching, and it can be seen that the Undershoot is 12mV when the LDO load is switched from a light load of 100uA to a heavy load of 150mA, and the Overshoot is 8mV when the LDO load is switched from the heavy load of 150mA to 100 uA; in addition, the change of the DC value of the output voltage under different loads is small, which shows that the LDO has high DC precision.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (6)
1. A high-precision fast transient response low dropout linear regulator is characterized by comprising an error amplifier, a PMOS power tube, a voltage division feedback network, a dynamic frequency compensation network and a voltage buffer;
the source electrode of the PMOS power tube is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the PMOS power tube outputs the output voltage of the low-dropout linear voltage regulator; the voltage division feedback network is used for dividing the output voltage of the low dropout linear regulator to obtain a feedback voltage;
the error amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein the third NMOS transistor and the sixth NMOS transistor have the same size, the fourth NMOS transistor and the fifth NMOS transistor have the same size and are smaller than the third NMOS transistor and the sixth NMOS transistor, and the seventh NMOS transistor and the eighth NMOS transistor have the same size;
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the feedback voltage, the source electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the eighth PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube and the reference voltage, the source electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the sixth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube;
the grid electrode of the seventh NMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode and the drain electrode of the sixth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the second PMOS tube and the source electrode of the ninth NMOS tube;
the grid electrode of the eighth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode and the drain electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, and the drain electrode of the eighth NMOS tube is connected with the drain electrode of the third PMOS tube and the source electrode of the tenth NMOS tube;
the grid electrodes of the first NMOS tube and the second NMOS tube are both connected with a first bias voltage, and the grid electrodes of the ninth NMOS tube and the tenth NMOS tube are both connected with a second bias voltage;
the grid electrode of the tenth PMOS tube is connected with the grid electrode and the drain electrode of the ninth PMOS tube and the drain electrode of the ninth NMOS tube, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube and serves as the output end of the error amplifier;
the source electrodes of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are all connected with the input voltage of the low dropout linear regulator, and the source electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all grounded;
the input end of the voltage buffer is connected with the output end of the error amplifier, and the output end of the voltage buffer is connected with the grid electrode of the PMOS power tube;
the dynamic frequency compensation network comprises an eleventh PMOS (P-channel metal oxide semiconductor) tube, a twelfth PMOS tube, an eleventh NMOS (N-channel metal oxide semiconductor) tube, a first capacitor and a first resistor;
the grid electrode of the eleventh PMOS tube is connected with the drain electrode of the twelfth PMOS tube and the source electrode of the eleventh NMOS tube, the source electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube and is connected with the input voltage of the low-dropout linear voltage regulator, and the drain electrode of the eleventh PMOS tube is in short circuit with the substrate and is connected with one end of the first resistor;
the grid electrode of the twelfth PMOS tube is connected with a third bias voltage;
the grid electrode of the eleventh NMOS tube is connected with the output end of the error amplifier, passes through the first capacitor and then is connected with the other end of the first resistor, and the drain electrode of the eleventh NMOS tube is grounded.
2. The high-precision fast transient response low dropout regulator according to claim 1, wherein the voltage buffer comprises a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a second resistor, a third resistor, a second capacitor and a third capacitor, wherein the thirteenth PMOS transistor and the fourteenth PMOS transistor have the same size;
the grid electrode of the eighteenth PMOS tube is connected with one end of a third resistor and is connected with the input voltage of the low dropout linear regulator after passing through a third capacitor, and the drain electrode of the eighteenth PMOS tube is connected with the other end of the third resistor, the grid electrode of the seventeenth PMOS tube and the drain electrode of the fourteenth NMOS tube;
the grid electrode of the fourteenth NMOS tube is connected with the second bias voltage, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube and the drain electrode of the fifteenth NMOS tube;
the grid electrode of the sixteenth PMOS tube is connected with the third bias voltage, and the drain electrode of the sixteenth PMOS tube is connected with the source electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube, the drain electrode of the thirteenth NMOS tube, the grid electrode and the drain electrode of the fifteenth PMOS tube and the drain electrode of the seventeenth PMOS tube and is connected with the output end of the voltage buffer;
the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube and connected with the input end of the voltage buffer, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube and the grid electrode of the thirteenth NMOS tube, and is grounded after passing through the second resistor and the second capacitor in sequence;
the grid electrodes of the twelfth NMOS tube and the fifteenth NMOS tube are connected with the output voltage of the low dropout linear regulator, the source electrodes of the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube and the eighteenth PMOS tube are all connected with the input voltage of the low dropout linear regulator, and the source electrodes of the twelfth NMOS tube, the thirteenth NMOS tube and the fifteenth NMOS tube are all grounded.
3. The high-precision fast transient response low dropout regulator according to claim 2, wherein the gates of the twelfth NMOS transistor and the fifteenth NMOS transistor in the voltage buffer are further provided with a transient enhancement high-pass network before being connected to the output voltage of the low dropout regulator, and the transient enhancement high-pass network comprises a fourth resistor and a fourth capacitor; one end of a fourth resistor is connected with the first bias voltage, and the other end of the fourth resistor is connected with one end of a fourth capacitor and the grids of a twelfth NMOS tube and a fifteenth NMOS tube; the other end of the fourth capacitor is connected with the output voltage of the low dropout regulator.
4. The high accuracy fast transient response low dropout regulator of claim 2, wherein the size of the eleventh NMOS transistor is equal to the size of the thirteenth PMOS transistor and the fourteenth PMOS transistor.
5. The high accuracy fast transient response low dropout regulator of any one of claims 1-4, further comprising a bias module for generating said first, second and third bias voltages, said bias module comprising a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor and an eighteenth NMOS transistor;
the grid electrode of the twentieth PMOS tube is connected with the grid electrode and the drain electrode of the nineteenth PMOS tube, the grid electrode of the twenty-first PMOS tube and the bias current and generates a third bias voltage, the source electrode of the twentieth PMOS tube is connected with the source electrode of the nineteenth PMOS tube and the source electrode of the twenty-first PMOS tube and is connected with the input voltage of the low dropout linear regulator, and the drain electrode of the twentieth PMOS tube is connected with the grid electrode and the drain electrode of the sixteenth NMOS tube and generates a first bias voltage;
the grid electrode and the drain electrode of the eighteenth NMOS tube are connected with the grid electrode of the seventeenth NMOS tube and the drain electrode of the twenty-first PMOS tube and generate the second bias voltage, and the source electrode of the eighteenth NMOS tube is connected with the drain electrode of the seventeenth NMOS tube;
and the source electrodes of the sixteenth NMOS tube and the seventeenth NMOS tube are grounded.
6. The high accuracy fast transient response low dropout regulator of claim 1, wherein the size of the seventh NMOS transistor is the sum of the sizes of the third NMOS transistor and the fourth NMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110344620.7A CN113064464B (en) | 2021-03-31 | 2021-03-31 | High-precision low-dropout linear regulator with quick transient response |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110344620.7A CN113064464B (en) | 2021-03-31 | 2021-03-31 | High-precision low-dropout linear regulator with quick transient response |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113064464A true CN113064464A (en) | 2021-07-02 |
| CN113064464B CN113064464B (en) | 2022-03-08 |
Family
ID=76565267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110344620.7A Active CN113064464B (en) | 2021-03-31 | 2021-03-31 | High-precision low-dropout linear regulator with quick transient response |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113064464B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113741604A (en) * | 2021-07-27 | 2021-12-03 | 西安电子科技大学 | Low-power-consumption and quick transient response numerical control LDO circuit |
| CN113885651A (en) * | 2021-10-19 | 2022-01-04 | 广东合微集成电路技术有限公司 | Low dropout voltage stabilizing circuit and low dropout voltage stabilizer |
| CN114167935A (en) * | 2021-08-02 | 2022-03-11 | 沈阳工业大学 | Current feedback voltage driver circuit with recovery time acceleration function |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114356008A (en) * | 2021-12-16 | 2022-04-15 | 上海川土微电子有限公司 | Low dropout regulator |
| CN115309225A (en) * | 2022-10-11 | 2022-11-08 | 江南大学 | Fully-integrated low-dropout regulator for low-power management system |
| CN115357078A (en) * | 2022-08-22 | 2022-11-18 | 电子科技大学 | LDO circuit for improving transient response capability |
| CN115421547A (en) * | 2022-09-30 | 2022-12-02 | 中国电子科技集团公司第二十四研究所 | Low dropout regulator with transconductance enhancement circuit |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104950975A (en) * | 2015-06-30 | 2015-09-30 | 电子科技大学 | Low dropout voltage regulator |
| CN106774614A (en) * | 2016-12-05 | 2017-05-31 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
| CN106933288A (en) * | 2017-04-25 | 2017-07-07 | 电子科技大学 | A kind of low-power consumption is without the outer capacitor type low pressure difference linear voltage regulator of piece |
| CN107092295A (en) * | 2017-04-28 | 2017-08-25 | 电子科技大学 | A kind of high Slew Rate fast transient response LDO circuit |
| CN107315441A (en) * | 2017-07-03 | 2017-11-03 | 电子科技大学 | Low pressure difference linear voltage regulator on a kind of piece with fast transient response |
-
2021
- 2021-03-31 CN CN202110344620.7A patent/CN113064464B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104950975A (en) * | 2015-06-30 | 2015-09-30 | 电子科技大学 | Low dropout voltage regulator |
| CN106774614A (en) * | 2016-12-05 | 2017-05-31 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
| CN106933288A (en) * | 2017-04-25 | 2017-07-07 | 电子科技大学 | A kind of low-power consumption is without the outer capacitor type low pressure difference linear voltage regulator of piece |
| CN107092295A (en) * | 2017-04-28 | 2017-08-25 | 电子科技大学 | A kind of high Slew Rate fast transient response LDO circuit |
| CN107315441A (en) * | 2017-07-03 | 2017-11-03 | 电子科技大学 | Low pressure difference linear voltage regulator on a kind of piece with fast transient response |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113741604A (en) * | 2021-07-27 | 2021-12-03 | 西安电子科技大学 | Low-power-consumption and quick transient response numerical control LDO circuit |
| CN114167935A (en) * | 2021-08-02 | 2022-03-11 | 沈阳工业大学 | Current feedback voltage driver circuit with recovery time acceleration function |
| CN113885651A (en) * | 2021-10-19 | 2022-01-04 | 广东合微集成电路技术有限公司 | Low dropout voltage stabilizing circuit and low dropout voltage stabilizer |
| CN113885651B (en) * | 2021-10-19 | 2022-09-27 | 广东合微集成电路技术有限公司 | Low dropout voltage stabilizing circuit and low dropout voltage stabilizer |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114356008A (en) * | 2021-12-16 | 2022-04-15 | 上海川土微电子有限公司 | Low dropout regulator |
| CN114356008B (en) * | 2021-12-16 | 2023-11-03 | 上海川土微电子有限公司 | Low-dropout linear voltage regulator |
| CN115357078A (en) * | 2022-08-22 | 2022-11-18 | 电子科技大学 | LDO circuit for improving transient response capability |
| CN115421547B (en) * | 2022-09-30 | 2023-07-25 | 中国电子科技集团公司第二十四研究所 | Low dropout linear voltage regulator with transconductance enhancement circuit |
| CN115421547A (en) * | 2022-09-30 | 2022-12-02 | 中国电子科技集团公司第二十四研究所 | Low dropout regulator with transconductance enhancement circuit |
| CN115309225A (en) * | 2022-10-11 | 2022-11-08 | 江南大学 | Fully-integrated low-dropout regulator for low-power management system |
| CN115309225B (en) * | 2022-10-11 | 2022-12-27 | 江南大学 | Fully-integrated low dropout regulator for low-power management system |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
| CN117075673B (en) * | 2023-10-16 | 2024-01-05 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113064464B (en) | 2022-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113064464B (en) | High-precision low-dropout linear regulator with quick transient response | |
| US10019023B2 (en) | Low-dropout linear regulator with super transconductance structure | |
| US11480986B2 (en) | PMOS-output LDO with full spectrum PSR | |
| CN100480944C (en) | Voltage controlled current source and low voltage difference regulated power supply installed with same | |
| CN109656300B (en) | Rapid load response L DO based on dual power rail power supply | |
| US20120212200A1 (en) | Low Drop Out Voltage Regulator | |
| CN114253330A (en) | Quick transient response's no off-chip capacitance low dropout linear voltage regulator | |
| CN113467559B (en) | Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator) | |
| CN110888484A (en) | Linear voltage regulator with low standby power consumption and high power supply rejection ratio | |
| Montalvo-Galicia et al. | Comparison of two internal miller compensation techniques for LDO regulators | |
| CN104950976B (en) | Voltage stabilizing circuit based on slew rate increasing | |
| CN113741610B (en) | Reference voltage circuit and chip | |
| CN113342108B (en) | Parallel operational amplifier zero compensation circuit | |
| CN108880228B (en) | Loop compensation system based on pole-zero tracking mechanism | |
| CN108733129B (en) | LDO (low dropout regulator) based on improved load current replication structure | |
| JP2021072033A (en) | Power supply circuit | |
| Stanescu | Buffer stage for fast response LDO | |
| CN115237193A (en) | LDO system suitable for low-voltage input and large-current output | |
| CN210155569U (en) | High-precision rapid transient response capacitor-free LDO (low dropout regulator) on full chip | |
| CN114840051A (en) | Low-power-consumption high-transient-response low-dropout linear voltage regulator without off-chip capacitor | |
| Liu et al. | Chip-area-efficient capacitor-less LDO regulator with fast-transient response | |
| Zhang et al. | A Capacitor-less LDO with Nested Miller Compensation and Bulk-Driven Techniques in 90nm CMOS | |
| KR20160012858A (en) | Low dropout regulator | |
| CN114756081B (en) | NMOS isolation type low dropout linear voltage regulator in self-synchronizing system | |
| Kuo et al. | Settling Time Enhancement of Output Capacitor-Less Low-Dropout Regulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |