CN106933288A - A kind of low-power consumption is without the outer capacitor type low pressure difference linear voltage regulator of piece - Google Patents
A kind of low-power consumption is without the outer capacitor type low pressure difference linear voltage regulator of piece Download PDFInfo
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- CN106933288A CN106933288A CN201710284463.9A CN201710284463A CN106933288A CN 106933288 A CN106933288 A CN 106933288A CN 201710284463 A CN201710284463 A CN 201710284463A CN 106933288 A CN106933288 A CN 106933288A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
A kind of low-power consumption belongs to technical field of power management without the outer capacitor type low pressure difference linear voltage regulator of piece.Pair error amplifier circuit enhanced with mutual conductance is input into using common gate to amplify by the two-way to signal, mutual conductance is carried out k1*k2 times of amplification, without the zero level point for introducing low frequency, synchronously increase gain and bandwidth, using the input of common gate to strengthening Slew Rate while low-power consumption is ensured, be conducive to shifting output limit onto higher frequency simultaneously, realize bandwidth higher；High pass detection network lifting transient response, output voltage V when reducing transient changingOUTThe undershoot voltage of appearance, further expands bandwidth；Transient state enhancing circuit provides a more quick path, is not worked when load stabilization, and the adjustment of major loop is not influenceed, when transient state, for improving bigger dynamically loop gain, strengthens the transient response speed of low pressure difference linear voltage regulator.The present invention has the characteristics of transient response speed fast and low-power consumption.
Description
Technical field
The invention belongs to technical field of power management, and in particular to a kind of without the outer capacitor type low pressure difference linear voltage regulator of piece
(CAPLESS-LDO) design.
Background technology
The features such as low pressure difference linear voltage regulator (LDO) has low-power consumption, low noise, small chip occupying area, extensively
It is applied to mobile electronic equipment.And LDO (i.e. Capless-LDO) without the outer capacitor type of piece because its can be integrated advantage, more
Plus it is widely used in on-chip system (SOC：system-on-chip).
Without the outer capacitor type low pressure difference linear voltage regulator Capless-LDO of piece and typical low pressure difference linear voltage regulator LDO framves
Structure is identical, specifically includes：Error amplifier EA (Error Amplifier), adjustment pipe MP、RF1And RF2The electric resistance partial pressure of composition is anti-
Feedback network, load current source Iload and output capacitance CO.The maximum disparity of two kinds of low pressure difference linear voltage regulator LDO is to export
Electric capacity COSize, compared to the ceramic electrical that the low pressure difference linear voltage regulator LDO of the outer electric capacity of strap generally uses microfarad (uF) level
Hold, the output capacitance C without the outer capacitor type low pressure difference linear voltage regulator Capless-LDO of pieceOIt is general each by on-chip system SOC inside
The parasitic capacitance of the power bus of module is constituted, under normal circumstances less than 100pF.Because small output capacitance is when switching is loaded
Enough electric currents can not be provided, without the piece faster loop adjustment of outer capacitor type low pressure difference linear voltage regulator Capless-LDO requirements,
Avoid excessive overshoot voltage and undershoot voltage.Therefore without the hair of the outer capacitor type low pressure difference linear voltage regulator Capless-LDO of piece
Exhibition demand requires transient response more rapidly in addition to low-power consumption, also.
The content of the invention
The present invention provides a kind of low pressure difference linear voltage regulator LDO circuit without the outer electric capacity of piece, with low-power consumption and quick wink
The characteristics of state is responded, is particularly suited for on-chip system SOC.
The technical scheme is that：
A kind of low-power consumption strengthens circuit, detects net containing high pass without the outer capacitor type low pressure difference linear voltage regulator of piece, including transient state
The error amplifier circuit of network, buffer circuits, adjustment pipe MP, output capacitance C0With load current source Iload,
The error amplifier circuit includes the common gate input being made up of the first PMOS PM1 and the second PMOS PM2
To, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th
NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8, the 9th NMOS tube NM9, the tenth NMOS tube NM10, the 11st NMOS
Pipe NM11, the 12nd NMOS tube NM12, the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the 7th PMOS
PM7, the 8th PMOS PM8, the 9th PMOS PM9, the tenth PMOS PM10, the 11st PMOS PM11, the 12nd PMOS
PM12, Miller capacitance CCWith zero-regulator resistor RZ,
The high pass detection network includes the 4th resistance R of series connectionAWith the second electric capacity CA, its series connection point connects the 4th PMOS
The grid of PM4, the 4th resistance RAThe first bias voltage of another termination VB1, the second electric capacity CAAnother termination output voltage VOUT；
The grid leak short circuit of the first NMOS tube NM1 and drain electrode, the 3rd NMOS tube NM3 and the 9th of the first PMOS PM1 of connection
The grid of NMOS tube MP9, the grid leak short circuit of the second PMOS PM2 and the grid and the second NMOS tube of the first PMOS PM1 of connection
The drain electrode of NM2, the source electrode of the first PMOS PM1 meets adjustment pipe MPDrain electrode, the grid of the second NMOS tube NM2 connects the second biased electrical
Pressure VB2,
The grid leak short circuit of the 4th NMOS tube NM4 and grid, the 3rd NMOS tube NM3 and the 4th of the 5th NMOS tube NM5 of connection
The drain electrode of PMOS PM4, the grid leak short circuit of the 6th PMOS PM6 and grid, the 5th NMOS tube of the 7th PMOS PM7 of connection
The drain electrode of NM5 and the 5th PMOS PM5, the grid of the 5th PMOS PM5 meets the first bias voltage VB1, the 7th NMOS tube NM7's
Grid, the drain electrode of the 6th NMOS tube NM6 and the 7th PMOS PM7 of grid leak short circuit and the 8th NMOS tube NM8 of connection, the 6th NMOS
The grid of pipe NM6 meets the second bias voltage VB2, the source electrode of the 4th PMOS PM4 meets the 5th PMOS PM5, the 6th PMOS PM6
With the source electrode of the 7th PMOS PM7,
The leakage of the grid leak short circuit and the grid and the 9th NMOS tube NM9 of the 9th PMOS PM9 of connection of the 8th PMOS PM8
Pole, the grid leak short circuit of the 11st NMOS tube NM11 and grid, the 9th PMOS PM9 and the tenth of the 12nd NMOS tube NM12 of connection
The drain electrode of NMOS tube NM10, the grid of the tenth NMOS tube NM10 meets the second bias voltage VB2, the grid leak of the 11st PMOS PM11
Grid, the drain electrode of the tenth PMOS PM10 and the 12nd NMOS tube NM12 of short circuit and the 12nd PMOS PM12 of connection, the tenth
The grid of PMOS PM10 meets the first bias voltage VB1,
The drain electrode of the 8th NMOS tube NM8 and the 12nd PMOS PM12 is connected and connects and adjusts pipe MPGrid, Miller electricity
Hold CCOne end connection adjustment pipe MPGrid, the other end pass through zero-regulator resistor RZConnection afterwards adjusts pipe MPDrain electrode, the 8th PMOS
Pipe PM8, the 9th PMOS PM9, the tenth PMOS PM10, the 11st PMOS PM11, the 12nd PMOS PM12 and adjustment pipe
MPSource electrode meet input voltage VIN, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, the 4th NMOS tube NM4,
5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8, the 9th NMOS tube NM9, the tenth
The source ground of NMOS tube NM10, the 11st NMOS tube NM11 and the 12nd NMOS tube NM12；
The 8th PMOS PM8 and the 9th PMOS PM9 constitutes a pair of current mirrors, and image ratio is 1：k1, the 11st
NMOS tube NM11 and the 12nd NMOS tube NM12 constitutes a pair of current mirrors, and image ratio is 1：k2, the 11st PMOS PM11 and
12 PMOS PM12 constitute a pair of current mirrors, and image ratio is 1：1, the 4th NMOS tube NM4 and the 5th NMOS tube NM5 are constituted a pair
Current mirror, image ratio is 1：k1, the 6th PMOS PM6 and the 7th PMOS PM7 a pair of current mirrors of composition, image ratio is 1：k2, the
Seven NMOS tube NM7 and the 8th NMOS tube NM8 constitute a pair of current mirrors, and image ratio is 1：1；
The transient state enhancing circuit includes the 13rd NMOS tube NM13, the 14th NMOS tube NM14, the 15th NMOS tube
NM15, the 16th NMOS tube NM16, the 13rd PMOS PM13, the 14th PMOS PM14, the 15th PMOS PM15, the tenth
Six PMOS PM16, second resistance R2With 3rd resistor R3,
The grid of the 13rd NMOS tube NM13 connects the grid of the 3rd NMOS tube NM3 in the error amplifier circuit, the
The grid leak short circuit of 14 NMOS tube NM14 and grid, the 13rd NMOS tube NM13 and the 13rd of the 15th NMOS tube NM15 of connection
The drain electrode of PMOS PM13, the source electrode of the 14th NMOS tube NM14 is by ground connection, the 13rd PMOS PM13 after 3rd resistor R3
With the gate interconnection of the 4th PMOS PM4 in the error amplifier circuit, its source electrode also interconnects,
The grid of the 16th NMOS tube NM16 connects the grid of the 9th NMOS tube NM9 in the error amplifier circuit, the
The grid leak short circuit of 15 PMOS PM15 and grid, the 16th NMOS tube NM16 and the 14th of the 16th PMOS PM16 of connection
The drain electrode of PMOS PM14, the source electrode of the 14th PMOS PM14 and the 16th PMOS PM16 meets input voltage VIN, its grid
The grid of the 4th PMOS PM4 in the error amplifier circuit is connect, the source electrode of the 15th PMOS PM15 passes through second resistance
R2 is followed by input voltage VIN, the 13rd NMOS tube NM13, the source electrode of the 15th NMOS tube NM15 and the 16th NMOS tube NM16 connect
Ground, the drain interconnection of the 15th NMOS tube NM15 and the 16th PMOS PM16 simultaneously connects adjustment pipe MPGrid, adjustment pipe MP's
Drain as the low pressure difference linear voltage regulator output end and by output capacitance C0Iload's and it is coupled with load current source
It is grounded after structure；
The input termination reference voltage V REF of the buffer circuits, second in its output described error amplifier of termination
The source electrode of PMOS PM2.
Specifically, the buffer circuits include the 17th NMOS tube NM17, the 18th NMOS tube NM18, the 19th NMOS
Pipe NM19, the 17th PMOS PM17, the 18th PMOS PM18, the 3rd PMOS PM3, the first electric capacity C1With first resistor R1,
The source electrode of the 18th NMOS tube NM18 and the 19th NMOS tube NM19 mutually and connects the 17th NMOS tube NM17
Drain electrode, the grid of the 17th NMOS tube NM17 meets the second bias voltage VB2, its source ground；The grid of the 18th NMOS tube NM18
Used as the input of the buffer circuits, the drain electrode of the 17th PMOS PM17 of its drain electrode connection is with the 3rd PMOS PM3's
Grid；The grid of the 19th NMOS tube NM19 connects the drain electrode of the 3rd PMOS PM3 and as the output end of the buffer circuits,
The leakage of the grid leak short circuit and the grid and the 19th NMOS tube NM19 of the 17th PMOS PM17 of connection of the 18th PMOS PM18
Pole, the 3rd PMOS PM3, the source electrode of the 17th PMOS PM17 and the 18th PMOS PM18 meet input voltage VIN, the first electricity
Hold C1One end connect the 3rd PMOS PM3 drain electrode, the other end pass through first resistor R1The grid of the 3rd PMOS PM3 are connected afterwards
Pole.
Specifically, the k1It is 3 or 4.
Specifically, the k2It is 3 or 4.
Beneficial effects of the present invention：Low pressure difference linear voltage regulator LDO circuit without the outer electric capacity of piece proposed by the present invention, has
Transient response speed is fast and the characteristics of low-power consumption, is particularly suited for on-chip system SOC, to the design of on-chip system SOC with apply
Serve impetus；Error amplifier circuit is amplified by the two-way to signal, mutual conductance is carried out k1*k2 times of amplification, together
When do not have introduce low frequency zero level point, synchronously increase gain and bandwidth；Error amplifier circuit is right using the input of common gate
First PMOS PM1 and the second PMOS PM2, strengthens Slew Rate, while being conducive to that limit will be exported while low-power consumption is ensured
(the secondary limit of loop) shifts higher frequency onto, realizes bandwidth higher；High pass detection network lifting transient response, reduces transient state change
Output voltage V during changeOUTThe undershoot voltage of appearance, further expands bandwidth；Transient state enhancing circuit provides one and more quickly leads to
Road, is not worked when load stabilization, and the adjustment of major loop is not influenceed, when transient state, for improving bigger dynamic
Loop gain, the transient response speed of enhancing low pressure difference linear voltage regulator LDO.
Brief description of the drawings
Fig. 1 is low pressure difference linear voltage regulator LDO basic framework schematic diagrames.
A kind of low-power consumption of fast transient response that Fig. 2 is provided for the present invention is without the outer capacitor type low pressure difference linear voltage regulator of piece
LDO circuit figure.
Fig. 3 is the loop response Bode diagram without high pass network.
Fig. 4 is the loop response Bode diagram containing high pass network.
Fig. 5 is loop adjustment diagram when underloading jumps heavy duty.
Fig. 6 is loop adjustment diagram when underloading is jumped in heavy duty.
Specific embodiment
Specific embodiment of the invention and principle are further elaborated with reference to diagram.
The main common gate that employs of the invention is input into pair error amplifier enhanced with mutual conductance, and high pass detection network to open up
Exhibition loop bandwidth, strengthens Slew Rate, improves transient response, especially suitable not terminate in on-chip system but on-chip system.
It is proposed by the present invention without the outer electric capacity low pressure difference linear voltage regulator LDO physical circuits of piece as shown in Fig. 2 the present invention is by mistake
Transconductance-enhanced technology is employed in the agent structure of difference amplifier, its implementation is：Error amplifier top half shown in Fig. 2
In, the drain electrode of the grid leak short circuit and the grid and the 9th NMOS tube NM9 of the 9th PMOS PM9 of connection of the 8th PMOS PM8, the tenth
The grid leak short circuit of one NMOS tube NM11 and the grid of the 12nd NMOS tube NM12 of connection, the 9th PMOS PM9 and the tenth NMOS tube
The drain electrode of NM10, the grid of the tenth NMOS tube NM10 meets the second bias voltage VB2, the grid leak short circuit of the 11st PMOS PM11 is simultaneously
Connect grid, the drain electrode of the tenth PMOS PM10 and the 12nd NMOS tube NM12 of the 12nd PMOS PM12, the tenth PMOS
The grid of PM10 meets the first bias voltage VB1, the 8th PMOS PM8 and the 9th PMOS PM9 a pair of current mirrors of composition, image ratio
It is 1：k1, the 11st NMOS tube NM11 and the 12nd NMOS tube NM12 a pair of current mirrors of composition, image ratio is 1：k2, the 11st
PMOS PM11 and the 12nd PMOS PM12 constitutes a pair of current mirrors, and image ratio is 1：1.Error amplifier lower half in Fig. 2
In point, grid, the 3rd NMOS tube NM3 and the 4th PMOS of the grid leak short circuit of the 4th NMOS tube NM4 and the 5th NMOS tube NM5 of connection
The drain electrode of pipe PM4, the grid leak short circuit of the 6th PMOS PM6 and connect the grid of the 7th PMOS PM7, the 5th NMOS tube NM5 and
The drain electrode of the 5th PMOS PM5, the grid of the 5th PMOS PM5 meets the first bias voltage VB1, the grid leak of the 7th NMOS tube NM7 is short
Connect and connect grid, the drain electrode of the 6th NMOS tube NM6 and the 7th PMOS PM7 of the 8th NMOS tube NM8, the 6th NMOS tube NM6
Grid meet the second bias voltage VB2, the source electrode of the 4th PMOS PM4 meets the 5th PMOS PM5, the 6th PMOS PM6 and the 7th
The source electrode of PMOS PM7, the 4th NMOS tube NM4 and the 5th NMOS tube NM5 constitute a pair of current mirrors, and image ratio is 1：k1, the 6th
PMOS PM6 and the 7th PMOS PM7 constitutes a pair of current mirrors, and image ratio is 1：k2, the 7th NMOS tube NM7 and the 8th NMOS tube
NM8 constitutes a pair of current mirrors, and image ratio is 1：1.The leakage of the grid leak short circuit and the first PMOS PM1 of connection of the first NMOS tube NM1
Pole, the grid of the 3rd NMOS tube NM3 and the 9th NMOS tube MP9, the grid leak short circuit of the second PMOS PM2 simultaneously connect the first PMOS
The drain electrode of the grid of PM1 and the second NMOS tube NM2, the source electrode of the first PMOS PM1 meets adjustment pipe MPDrain electrode, the second NMOS tube
The grid of NM2 meets the second bias voltage VB2, the drain electrode of the 8th NMOS tube NM8 and the 12nd PMOS PM12 is connected and connects adjustment
Pipe MPGrid, Miller capacitance CCOne end connection adjustment pipe MPGrid, the other end pass through zero-regulator resistor RZConnection adjustment afterwards is managed
MPDrain electrode, the 8th PMOS PM8, the 9th PMOS PM9, the tenth PMOS PM10, the 11st PMOS PM11, the 12nd
PMOS PM12 and adjustment pipe MPSource electrode meet input voltage VIN, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube
NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8,
Nine NMOS tube NM9, the tenth NMOS tube NM10, the source ground of the 11st NMOS tube NM11 and the 12nd NMOS tube NM12.
High pass detection network includes the 4th resistance R of series connectionAWith the second electric capacity CA, its series connection point connects the 4th PMOS PM4's
Grid, the 4th resistance RAThe first bias voltage of another termination VB1, the second electric capacity CAAnother termination output voltage VOUT.Buffering
The input termination reference voltage V REF of device circuit, the source electrode of the second PMOS PM2 in its output termination error amplifier.
In error amplifier circuit common gate input to circuit implementing scheme be：Adjustment pipe MPDrain electrode connection first
The grid of the source electrode of PMOS PM1, the first PMOS PM1 and the second PMOS PM2 is connected, and the grid leak of the second PMOS PM2 is short
Connect, the input that the first PMOS PM1 and the second PMOS PM2 constitutes common gate is right.The source electrode of the second PMOS PM2 was connected
Equivalent reference voltage V REF after buffer circuits, the drain electrode of the second PMOS PM2 is connected to the drain electrode of the 2nd NMSO pipes NM2, the
The grid of two NMOS tube NM2 meets the second bias voltage VB2, it is ensured that the second NMOS tube NM2 is sub-thread bias current I by electric currentB,
The source ground of the second NMOS tube NM2.The drain electrode of the first PMOS PM1 is connected to the drain electrode of the first NMOS tube NM1, the first NMOS tube
NM1 grid leak short circuits, grid is connected to the grid of the 3rd NMOS tube NM3 and the 9th NMOS tube NM9, the first NMOS tube NM1 respectively and
3rd NMOS tube NM3 and the 9th NMOS tube NM9 forms current mirror.Drain terminal and a PMOS of the small-signal from the first NMOS tube NM1
The drain terminal outflow of pipe PM1, is divided into the top and the bottom that two-way flows into error amplifier, all the way by the 3rd NMOS tube NM3, the 4th
NMOS tube NM4, the 5th NMOS tube NM5, the 6th PMOS PM6, the 7th PMOS PM7, the 7th NMOS tube NM7, the 8th NMOS tube
NM8；Another road is by the 9th NMOS tube NM9, the 8th PMOS PM8, the 9th PMOS PM9, the 11st NMOS tube NM11, the
12 NMOS tube NM12, the 11st NMOS tube PM11, the 12nd PMOS PM12.Small-signal current is in adjustment pipe MPGrid converge
Close, common adjustment adjustment pipe MPGrid voltage.In the case of stable state, signal code is amplified by two-stage, equivalent to will be across
The amplification for carrying out k1*k2 times is led, while not introducing the zero pole point of low frequency, gain and bandwidth is synchronously increased.But because most
Big bandwidth is limited by time limit, so the value of k1, k2 can not obtain excessive, it is proposed that take 3~4.5th PMOS PM5, the
The effect of four PMOS PM4, the tenth PMOS PM10, the 6th NMOS tube NM6, the tenth NMOS tube NM10 is by larger inclined of prime
Put electric current to cut, it is to avoid quiescent current also passes through current mirror and amplifies step by step, increase quiescent dissipation.
The complete transfer function of loop is：
Wherein gmp1、gmp4The mutual conductance of the first PMOS PM1 and the 4th PMOS PM4 pipes, R are represented respectivelyOARepresentative errors are put
The output resistance of big device EA, CgRepresent power tube MPEquivalent grid capacitance, gmpRepresent power tube MPMutual conductance, RORepresenting should
The output resistance of low pressure difference linear voltage regulator LDO, CORepresent the output capacitance of low pressure difference linear voltage regulator LDO.(S is transmission
Variable in function, is an amount for being used to weigh frequency, and the S=jw typically in circuit system, wherein w are angular frequencies, and j is empty
Number unit.)
The input of error amplifier EA to the input using common gate to the first PMOS PM1 and the second PMOS PM2,
Ensure to strengthen Slew Rate while low-power consumption, while being conducive to shifting output limit (the secondary limit of loop) onto higher frequency, realize more
Bandwidth high.General error amplifier uses the differential pair of common source, and differential pair shares a tail current source, low in order to ensure
The design of power consumption, general tail current can not be too big, but when transient state switches, the maximum output current of error amplifier EA
It is limited to the size of tail current.Tail current limits Slew Rate, while the transient state for also limiting low pressure difference linear voltage regulator LDO is rung
Should.Common gate is input into, first PMOS PM1 and second similar to operation principle to the input with common source when stable state
, because loop adjustment clamper is equal, grid voltage is also identical, therefore quiescent current is identical, is for the source voltage of PMOS PM2
Bias current IB.As shown in fig. 6, when load is redirected from heavy duty toward underloading, output voltage VOUTVoltage rise, first
The value of the gate source voltage of PMOS PM1 | VGS| increase, cause the electric current for flowing through the first PMOS PM1 to increase, this strand of electric current passes through
Rear class amplifies the maximum output current as error amplifier EA step by step, and the electric current of the first PMOS PM1 is not limited by biasing
Electric current IB, and can be much larger than bias current IB, the maximum output current of such error amplifier EA also would not be because of biasing
Electric current IBAnd be limited, therefore common gate input to ensure low speed paper tape reader static power disspation in the case of can be simultaneously reached Slew Rate higher,
Without limitation on the performance of transient state, then by the amplification step by step of mutual conductance enhancing structure below, increase Slew Rate, improve transient response.
Further, since output limit is determined by the impedance and output capacitance of output end, from terms of the source of the first PMOS PM1
The impedance entered is a relatively low equivalent resistance, and its value is 1/gmp1, wherein gmp1It is the mutual conductance of the first PMOS, originally defeated
Going out impedance impedance in parallel can reduce whole equiva lent impedance, be conducive to pushing output limit to higher frequency, ensure enough phases
Under the nargin of position, bandwidth higher can be designed, be more favorable for transient state enhancing.
In output voltage VOUTWhen reduction, the maximum output current of error amplifier EA will not be right because of the input of common grid
Improved accordingly, so optimizing such case present invention employs high pass network.Fig. 5 is that the transient state of underloading jump heavy duty is cut
Ring change road response diagram, can be explained the effect that high pass network lifts transient response, and wherein Cg is adjustment pipe MPEquivalent gate capacitance.
When load is from underloading toward heavy duty switching, output voltage VOUTDecline at once, high pass network is by output voltage VOUTChange be coupled to
The grid voltage V of the 4th PMOS PM4APlace, the electric current for causing to flow through the 4th PMOS PM4 increases, the electric current by rear class by
Level is amplified, and obtains a bigger pull-down current, and help adjusts pipe MPGrid capacitance CgElectric discharge, reduces adjustment pipe M as early as possibleP's
Grid voltage, makes adjustment pipe MPFaster by bigger electric current, output voltage V is helpedOUTRecover.Therefore, high pass network
Output voltage V when introducing reduces transient changingOUTThe undershoot voltage of appearance.
High pass network introduces a pair of zero pole points pair near gain bandwidth product GBW, and the zero point of Left half-plane is slightly less than pole
Point, therefore positive phase is contribute to, in the case of same phase margin, further expand bandwidth.Fig. 3 is free from high pass
The frequency response figure of network, makes dominant pole be separated with secondary limit present invention employs miller compensation technology, and by zero-regulator resistor RZWill
The zero point of RHP is shifted onto at extremely high frequency.Secondary limit is low at gain bandwidth product GBW in the case of the most underloading, it is ensured that most
Poor phase margin is more than 45 degree.Fig. 4 is the frequency response figure for containing high pass network, it can be seen that because what high pass network was introduced
The compensation of " pole after first zero " so that bandwidth is further expanded.
Transient state enhancing circuit in Fig. 2 provides a more quick path, is not worked when load stabilization, not shadow
The adjustment of major loop is rung, when transient state, for improving bigger dynamically loop gain, strengthens low pressure difference linear voltage regulator
The transient response speed of LDO.
Because reference voltage V REF is not directly connected to source electrode typically, so reference voltage V REF is by one in the present embodiment
Buffer circuits are followed by the source electrode to the second PMOS, as shown in Fig. 2 the buffer circuits used in the present embodiment include the tenth
Seven NMOS tube NM17, the 18th NMOS tube NM18, the 19th NMOS tube NM19, the 17th PMOS PM17, the 18th PMOS
PM18, the 3rd PMOS PM3, the first electric capacity C1With first resistor R1, the 18th NMOS tube NM18's and the 19th NMOS tube NM19
Source electrode mutually and connects the drain electrode of the 17th NMOS tube NM17, and the grid of the 17th NMOS tube NM17 meets the second bias voltage VB2,
Its source ground；The grid of the 18th NMOS tube NM18 as the buffer circuits input, its drain electrode connection the 17th
The drain electrode of PMOS PM17 and the grid of the 3rd PMOS PM3；The grid of the 19th NMOS tube NM19 connects the 3rd PMOS PM3's
Drain and as the output end of the buffer circuits, the grid leak short circuit of the 18th PMOS PM18 simultaneously connects the 17th PMOS
The drain electrode of the grid of PM17 and the 19th NMOS tube NM19, the 3rd PMOS PM3, the 17th PMOS PM17 and the 18th PMOS
The source electrode of pipe PM18 meets input voltage VIN, the first electric capacity C1One end connect the drain electrode of the 3rd PMOS PM3, the other end is by the
One resistance R1The grid of the 3rd PMOS PM3 is connected afterwards.
One of ordinary skill in the art can make various not departing from originally according to these technical inspirations disclosed by the invention
Other various specific deformations and combination of essence are invented, these deformations and combination are still within the scope of the present invention.
Claims (4)
1. a kind of low-power consumption strengthens circuit, detects network containing high pass without the outer capacitor type low pressure difference linear voltage regulator of piece, including transient state
Error amplifier circuit, buffer circuits, power tube (MP), output capacitance (C0) and load current source (Iload), its feature
It is,
The error amplifier circuit includes the common gate input being made up of the first PMOS (PM1) and the second PMOS (PM2)
To, the first NMOS tube (NM1), the second NMOS tube (NM2), the 3rd NMOS tube (NM3), the 4th NMOS tube (NM4), the 5th NMOS tube
(NM5), the 6th NMOS tube (NM6), the 7th NMOS tube (NM7), the 8th NMOS tube (NM8), the 9th NMOS tube (NM9), the tenth
NMOS tube (NM10), the 11st NMOS tube (NM11), the 12nd NMOS tube (NM12), the 4th PMOS (PM4), the 5th PMOS
(PM5), the 6th PMOS (PM6), the 7th PMOS (PM7), the 8th PMOS (PM8), the 9th PMOS (PM9), the tenth
PMOS (PM10), the 11st PMOS (PM11), the 12nd PMOS (PM12), Miller capacitance (CC) and zero-regulator resistor (RZ),
The high pass detection network includes the 4th resistance (R of series connectionA) and the second electric capacity (CA), its series connection point connects the 4th PMOS
(PM4) grid, the 4th resistance (RA) the first bias voltage of another termination (VB1), the second electric capacity (CA) another termination output
Voltage (VOUT)；
The grid leak short circuit of the first NMOS tube (NM1) simultaneously connects the drain electrode of the first PMOS (PM1), the 3rd NMOS tube (NM3) and the
The grid of nine NMOS tubes (MP9), the grid leak short circuit of the second PMOS (PM2) simultaneously connects the grid and the of the first PMOS (PM1)
The drain electrode of two NMOS tubes (NM2), the source electrode of the first PMOS (PM1) meets adjustment pipe (MP) drain electrode, the second NMOS tube (NM2)
Grid meets the second bias voltage (VB2),
The grid leak short circuit of the 4th NMOS tube (NM4) simultaneously connects the grid of the 5th NMOS tube (NM5), the 3rd NMOS tube (NM3) and the
The drain electrode of four PMOSs (PM4), the grid leak short circuit of the 6th PMOS (PM6) and grid, the 5th of the 7th PMOS (PM7) of connection
The drain electrode of NMOS tube (NM5) and the 5th PMOS (PM5), the grid of the 5th PMOS (PM5) meets the first bias voltage (VB1), the
The grid leak short circuit of seven NMOS tubes (NM7) and the grid of the 8th NMOS tube (NM8) of connection, the 6th NMOS tube (NM6) and the 7th PMOS
The drain electrode of (PM7) is managed, the grid of the 6th NMOS tube (NM6) meets the second bias voltage (VB2), the source electrode of the 4th PMOS (PM4) connects
The source electrode of the 5th PMOS (PM5), the 6th PMOS (PM6) and the 7th PMOS (PM7),
The leakage of the grid leak short circuit and the grid and the 9th NMOS tube (NM9) of the 9th PMOS (PM9) of connection of the 8th PMOS (PM8)
Pole, the grid leak short circuit of the 11st NMOS tube (NM11) and grid, the 9th PMOS (PM9) of the 12nd NMOS tube (NM12) of connection
With the drain electrode of the tenth NMOS tube (NM10), the grid of the tenth NMOS tube (NM10) meets the second bias voltage (VB2), the 11st PMOS
Manage the grid leak short circuit of (PM11) and connect grid, the tenth PMOS (PM10) and the 12nd NMOS of the 12nd PMOS (PM12)
The drain electrode of (NM12) is managed, the grid of the tenth PMOS (PM10) meets the first bias voltage (VB1),
8th NMOS tube (NM8) is connected with the drain electrode of the 12nd PMOS (PM12) and connects adjustment and manages (MP) grid, Miller electricity
Hold (CC) one end connection adjustment pipe (MP) grid, the other end pass through zero-regulator resistor (RZ) adjustment pipe (M is connected afterwardsP) drain electrode,
8th PMOS (PM8), the 9th PMOS (PM9), the tenth PMOS (PM10), the 11st PMOS (PM11), the 12nd
PMOS (PM12) and adjustment pipe (MP) source electrode meet input voltage (VIN), the first NMOS tube (NM1), the second NMOS tube (NM2),
3rd NMOS tube (NM3), the 4th NMOS tube (NM4), the 5th NMOS tube (NM5), the 6th NMOS tube (NM6), the 7th NMOS tube
(NM7), the 8th NMOS tube (NM8), the 9th NMOS tube (NM9), the tenth NMOS tube (NM10), the 11st NMOS tube (NM11) and
The source ground of 12 NMOS tubes (NM12)；
8th PMOS (PM8) and the 9th PMOS (PM9) constitute a pair of current mirrors, and image ratio is 1：k1, the 11st NMOS
Pipe (NM11) and the 12nd NMOS tube (NM12) constitute a pair of current mirrors, and image ratio is 1：k2, the 11st PMOS (PM11) and
12nd PMOS (PM12) constitutes a pair of current mirrors, and image ratio is 1：1, the 4th NMOS tube (NM4) and the 5th NMOS tube (NM5)
A pair of current mirrors are constituted, image ratio is 1：k1, the 6th PMOS (PM6) and the 7th PMOS (PM7) constitute a pair of current mirrors, mirror
As than being 1：k2, the 7th NMOS tube (NM7) and the 8th NMOS tube (NM8) constitute a pair of current mirrors, and image ratio is 1：1；
The transient state enhancing circuit includes the 13rd NMOS tube (NM13), the 14th NMOS tube (NM14), the 15th NMOS tube
(NM15), the 16th NMOS tube (NM16), the 13rd PMOS (PM13), the 14th PMOS (PM14), the 15th PMOS
(PM15), the 16th PMOS (PM16), second resistance (R2) and 3rd resistor (R3),
The grid of the 13rd NMOS tube (NM13) connects the grid of the 3rd NMOS tube (NM3) in the error amplifier circuit, the
The grid leak short circuit of 14 NMOS tubes (NM14) and connect the grid of the 15th NMOS tube (NM15), the 13rd NMOS tube (NM13) and
The drain electrode of the 13rd PMOS (PM13), the source electrode of the 14th NMOS tube (NM14) is grounded afterwards by 3rd resistor (R3), and the tenth
The gate interconnection of three PMOSs (PM13) and the 4th PMOS (PM4) in the error amplifier circuit, its source electrode is also interconnected,
The grid of the 16th NMOS tube (NM16) connects the grid of the 9th NMOS tube (NM9) in the error amplifier circuit, the
The grid leak short circuit of 15 PMOSs (PM15) and connect the grid of the 16th PMOS (PM16), the 16th NMOS tube (NM16) and
The source electrode of the drain electrode of the 14th PMOS (PM14), the 14th PMOS (PM14) and the 16th PMOS (PM16) connects input electricity
Pressure (VIN), its grid connects the grid of the 4th PMOS (PM4) in the error amplifier circuit, the 15th PMOS (PM15)
Source electrode is followed by input voltage (V by second resistance (R2)IN), the 13rd NMOS tube (NM13), the 15th NMOS tube (NM15) and
The drain interconnection of the source ground of the 16th NMOS tube (NM16), the 15th NMOS tube (NM15) and the 16th PMOS (PM16)
And connect adjustment pipe (MP) grid, adjustment pipe (MP) drain electrode as the low pressure difference linear voltage regulator output end and pass through
Output capacitance (C0) and the parallel-connection structure of load current source (Iload) after be grounded；
The input of the buffer circuits terminates reference voltage (VREF), second in its output described error amplifier circuit of termination
The source electrode of PMOS (PM2).
2. low-power consumption according to claim 1 is without the outer capacitor type low pressure difference linear voltage regulator of piece, it is characterised in that described slow
Rushing device circuit includes the 17th NMOS tube (NM17), the 18th NMOS tube (NM18), the 19th NMOS tube (NM19), the 17th
PMOS (PM17), the 18th PMOS (PM18), the 3rd PMOS (PM3), the first electric capacity (C1) and first resistor (R1),
The source electrode of the 18th NMOS tube (NM18) and the 19th NMOS tube (NM19) mutually and connect the 17th NMOS tube (NM17)
Drain electrode, the grid of the 17th NMOS tube (NM17) meets the second bias voltage (VB2), its source ground；18th NMOS tube
(NM18) grid as the buffer circuits input, the drain electrode and the of its drain electrode the 17th PMOS (PM17) of connection
The grid of three PMOSs (PM3)；The grid of the 19th NMOS tube (NM19) connects the drain electrode of the 3rd PMOS (PM3) and as described
The output end of buffer circuits, the grid leak short circuit of the 18th PMOS (PM18) and the grid of the 17th PMOS (PM17) of connection
With the drain electrode of the 19th NMOS tube (NM19), the 3rd PMOS (PM3), the 17th PMOS (PM17) and the 18th PMOS
(PM18) source electrode meets input voltage (VIN), the first electric capacity (C1) one end connect the 3rd PMOS (PM3) drain electrode, the other end
By first resistor (R1) afterwards connect the 3rd PMOS (PM3) grid.
3. low-power consumption according to claim 1 is without the outer capacitor type low pressure difference linear voltage regulator of piece, it is characterised in that the k1
It is 3 or 4.
4. low-power consumption according to claim 3 is without the outer capacitor type low pressure difference linear voltage regulator of piece, it is characterised in that the k2
It is 3 or 4.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113050750A (en) * | 2021-03-19 | 2021-06-29 | 电子科技大学 | Low dropout regulator capable of realizing wide input range and rapid stable state |
| CN113064464A (en) * | 2021-03-31 | 2021-07-02 | 电子科技大学 | High-precision low-dropout linear regulator with quick transient response |
| CN113190075A (en) * | 2021-04-21 | 2021-07-30 | 电子科技大学 | Wide input range's digital power supply Capless LDO |
| CN113377152A (en) * | 2021-07-14 | 2021-09-10 | 电子科技大学 | Quick response does not have external electric capacity type linear voltage regulator |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114510109A (en) * | 2022-01-13 | 2022-05-17 | 电子科技大学 | high-PSR (power supply rejection) fast transient response dual-mode LDO (low dropout regulator) without off-chip capacitor |
| CN114546026A (en) * | 2022-03-02 | 2022-05-27 | 上海先楫半导体科技有限公司 | Linear voltage stabilization module and system on chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6522111B2 (en) * | 2001-01-26 | 2003-02-18 | Linfinity Microelectronics | Linear voltage regulator using adaptive biasing |
| CN102298407A (en) * | 2010-06-28 | 2011-12-28 | 中国人民解放军国防科学技术大学 | Low-output voltage and fast response low-dropout regulator (LDO) circuit based on current control loop |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| US20150130434A1 (en) * | 2013-11-08 | 2015-05-14 | Texas Instruments Incorporated | Fast current limiting circuit in multi loop ldos |
| CN104898752A (en) * | 2015-06-26 | 2015-09-09 | 中国兵器工业集团第二一四研究所苏州研发中心 | Capacitor-less LDO (low dropout regulator) capable of achieving fast transient response |
-
2017
- 2017-04-25 CN CN201710284463.9A patent/CN106933288B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6522111B2 (en) * | 2001-01-26 | 2003-02-18 | Linfinity Microelectronics | Linear voltage regulator using adaptive biasing |
| CN102298407A (en) * | 2010-06-28 | 2011-12-28 | 中国人民解放军国防科学技术大学 | Low-output voltage and fast response low-dropout regulator (LDO) circuit based on current control loop |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| US20150130434A1 (en) * | 2013-11-08 | 2015-05-14 | Texas Instruments Incorporated | Fast current limiting circuit in multi loop ldos |
| CN104076854A (en) * | 2014-06-27 | 2014-10-01 | 电子科技大学 | Capless LDO (Low Dropout Regulator) |
| CN104898752A (en) * | 2015-06-26 | 2015-09-09 | 中国兵器工业集团第二一四研究所苏州研发中心 | Capacitor-less LDO (low dropout regulator) capable of achieving fast transient response |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113050750A (en) * | 2021-03-19 | 2021-06-29 | 电子科技大学 | Low dropout regulator capable of realizing wide input range and rapid stable state |
| CN113050750B (en) * | 2021-03-19 | 2021-11-23 | 电子科技大学 | Low dropout regulator capable of realizing wide input range and rapid stable state |
| CN113064464A (en) * | 2021-03-31 | 2021-07-02 | 电子科技大学 | High-precision low-dropout linear regulator with quick transient response |
| CN113064464B (en) * | 2021-03-31 | 2022-03-08 | 电子科技大学 | High-precision low-dropout linear regulator with quick transient response |
| CN113190075A (en) * | 2021-04-21 | 2021-07-30 | 电子科技大学 | Wide input range's digital power supply Capless LDO |
| CN113377152A (en) * | 2021-07-14 | 2021-09-10 | 电子科技大学 | Quick response does not have external electric capacity type linear voltage regulator |
| CN113377152B (en) * | 2021-07-14 | 2022-06-24 | 电子科技大学 | Quick response does not have external electric capacity type linear voltage regulator |
| CN114253330A (en) * | 2021-12-02 | 2022-03-29 | 电子科技大学 | Quick transient response's no off-chip capacitance low dropout linear voltage regulator |
| CN114510109A (en) * | 2022-01-13 | 2022-05-17 | 电子科技大学 | high-PSR (power supply rejection) fast transient response dual-mode LDO (low dropout regulator) without off-chip capacitor |
| CN114546026A (en) * | 2022-03-02 | 2022-05-27 | 上海先楫半导体科技有限公司 | Linear voltage stabilization module and system on chip |
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|---|---|
| CN106933288B (en) | 2018-03-20 |
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