CN117277783A - LDO circuit applied to AC-DC power supply driving chip starting circuit - Google Patents
LDO circuit applied to AC-DC power supply driving chip starting circuit Download PDFInfo
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- CN117277783A CN117277783A CN202311553421.2A CN202311553421A CN117277783A CN 117277783 A CN117277783 A CN 117277783A CN 202311553421 A CN202311553421 A CN 202311553421A CN 117277783 A CN117277783 A CN 117277783A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses an LDO circuit for an AC-DC power supply driving chip starting circuit, which belongs to the technical field of LDO circuits, and comprises a voltage buffer module, a charge pump module, an error amplifying module, a loop stability compensation module, a voltage feedback module, an output power tube module and an overshoot suppression module. By implementing the technical scheme of the invention, a higher power supply rejection ratio can be obtained, the minimum working voltage of the LDO circuit is reduced, and the downward overshoot during the switching of the LDO voltage is restrained, so that the performance of the LDO circuit and the stability of a system are improved.
Description
Technical Field
The invention relates to the technical field of LDO circuits, in particular to an LDO structure applied to an AC-DC power supply driving chip starting circuit.
Background
LDO (low dropout regulator, low dropout linear regulator) is often used as a high-precision, high-speed power management circuit for AC-DC power driving chip start-up circuits to provide stable input voltages for other circuit blocks in the start-up circuit.
As shown in fig. 1, the PSR topology AC-DC circuit block diagram includes the following working procedures: when the AC power supply is connected, the VCC capacitor is charged through the resistor Rstart, when the voltage of the VCC capacitor reaches the requirement, the vcc_on signal is output to trigger the chip to start working, and the system has strict requirements on power consumption and starting time of the system, so that the resistance value of the resistor Rstart is set to be very large, and the working current of an internal circuit in the starting process is as small as possible. Fig. 2 is a block diagram showing the structure of the starting circuit.
When the power-on is started, the input power supply charges the VCC capacitor through Rstart, at the moment, only the VCC detection module detects the value of the VCC voltage in real time, all other modules do not work, and the VCC detection module triggers the vcc_on signal until the VCC voltage reaches the vcc_on threshold value, and the other modules start to work, so that the static current of the VCC detection module is less than 1uA, and the requirement of the system on the power-on time can be well met. The resistance value of Rstart is typically 8MΩ and the VCC capacitance value is typically 4.7uF.
After triggering the vcc_on signal, the bandgap reference block begins to operate and outputs vbg and ibg provide reference voltages and bias currents for the reference voltage and bias current block that generate the reference voltages vref_ldo and bias currents required by the remaining blocks of the system. The power-on reset module detects the vref_ldo signal, and generates a horn 1 signal after reaching a threshold value, and the LDO module starts to work. The horn 1 signal generates a horn signal after passing through the delay module, and the system post-stage module starts to work.
As shown in FIG. 2, the bandgap reference module and the reference voltage and bias current module provide the required bias voltage and current for the whole system, so the requirement on the power supply is relatively high, and therefore, the LDO circuit is designed to supply power for the bandgap reference module and the reference voltage and bias current module, and the stable voltage output and high power supply rejection ratio of the LDO circuit ensure that the bandgap reference module and the reference voltage and bias current module have better working environments, and simultaneously, the module with relatively high requirement on the power supply in the whole system is also supplied with power.
LDO circuits have two important evaluation criteria: smaller operating voltages and higher power supply rejection ratios.
FIG. 3 is a schematic diagram of a conventional PMOS LDO structure without an off-chip capacitor. The LDO circuit is composed of four parts: an error amplifying module (hereinafter referred to as ea), a voltage feedback module, an output power tube module and a loop stability compensation module. When PMOS is used as the output power transistor, the operating voltage of ea determines the minimum operating voltage of the entire LDO. The circuit shown in fig. 3 has the advantage that it requires a lower minimum operating voltage VCC, the minimum supply voltage being:
wherein vdsp7 represents the source-drain voltage difference of the field effect transistor mp 7.
The power supply inhibition ratio is as follows:
where Aea is the gain of the ea input to the ea output, apower is the gain of the output power transistor stage input to the output, accea is the gain of the ea output from VCC to ea, accewer is the gain of the output power transistor stage VCC to the output,
wherein: gmp0, gmp5, gmn1, gmp3, gmp7 are the transconductance of the field effect transistors mp0, mp5, mn1, mp3, mp7, rop5, rop3, ron1, ron3, rop6, rop7 are the output impedance of the field effect transistors mp5, mp3, mn1, mn3, mp6, mp7, respectively, β is the feedback coefficient: (R1+R2)/R2.
The power supply rejection ratio is:
in practical application, the power supply rejection ratio is greater than 40dB at high frequency, and the power supply rejection ratio of the LDO shown in fig. 3 is about 25dB, which cannot meet the application requirements.
FIG. 4 is a schematic diagram of a conventional NMOS LDO structure without an off-chip capacitor. The minimum power supply voltage is:
the power supply inhibition ratio is as follows:
wherein: gmn7 and ron7 represent the transconductance and output impedance of field effect transistor mn7, respectively.
Therefore, the LDO shown in FIG. 4 with NMOS as the output power tube has a better power supply rejection ratio than the LDO shown in FIG. 3 with PMOS as the output power tube.
Although the LDO with the structure shown in fig. 4 has better power supply rejection ratio, and the mobility μn of the NMOS is more than 2 times that of the PMOS, the required size is also 2 times smaller when the same current is driven, but the minimum operating voltage of the NMOS LDO shown in fig. 4 is larger, which does not meet the application requirement of low power supply voltage.
Disclosure of Invention
The invention aims to solve the technical problem that the minimum working voltage of an NMOS LDO circuit in the prior art does not meet the application requirement of a low power supply voltage system, and provides an LDO circuit applied to an AC-DC power supply driving chip starting circuit.
The technical scheme adopted for solving the technical problems is as follows:
the invention provides an LDO circuit for an AC-DC power supply driving chip starting circuit, which is triggered by a first enabling signal and a second enabling signal, outputs a stable voltage signal according to an input reference voltage signal to supply power for part of modules in the AC-DC power supply driving chip starting circuit, and comprises a voltage buffer module, a charge pump module, an error amplification module, a loop stability compensation module, a voltage feedback module, an output power tube module and an overshoot suppression module;
the second enabling signal is obtained by delaying the first enabling signal;
the charge pump module is used for supplying power to the error amplifying module, the voltage input end of the charge pump module is connected with a working power supply VDD, the enabling input end of the charge pump module is connected with the first enabling signal, the output end of the charge pump module is connected with the positive power input end of the error amplifying module, and the charge pump module starts to work when the first enabling signal is triggered;
the positive input end of the voltage buffer module is connected with the reference voltage, and the negative input end of the voltage buffer module is connected with the output end;
the overshoot suppression module comprises a capacitor, the input end of the capacitor is connected with the output end of the voltage buffer module, the output end of the capacitor is connected with the forward input end of the error amplification module, the capacitor is used for charging when the LDO circuit is started, and after the LDO circuit begins to work formally, the capacitor is used for slowly discharging until the LDO output voltage reaches a stable value;
the error amplification module is used for amplifying the difference value between the input reference voltage and the feedback voltage, the forward input end of the error amplification module is connected with the output end of the voltage buffer module through the overshoot suppression module, and the reverse input end of the error amplification module is connected with the output end of the voltage feedback module;
the input end of the loop stability compensation module is connected with the output end of the error amplification module and is used for guaranteeing the stability of the LDO feedback loop;
the input end of the voltage feedback module is connected with the output end of the loop stability compensation module;
the output power tube module is an NMOS field effect tube.
According to the technical scheme, an NMOS field effect transistor is adopted as an output power transistor of the LDO circuit, a charge pump is used for supplying power to an error amplifying circuit, and a voltage buffer module and an overshoot suppression module are used for enabling output voltage of the LDO to be slowly discharged through a capacitor when being switched, so that smooth transition of the output voltage is realized. Therefore, by adopting the technical scheme of the invention, a higher power supply rejection ratio can be obtained, the minimum working voltage of the LDO circuit is reduced, and the downward overshoot during the switching of the LDO voltage is restrained, so that the performance of the LDO circuit and the stability of a system are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention.
Fig. 1 is a block diagram of a PSR topology AC-DC circuit.
Fig. 2 is a block diagram of the start-up circuit in the circuit of fig. 1.
FIG. 3 is a schematic diagram of a conventional PMOS LDO structure without an off-chip capacitor.
FIG. 4 is a schematic diagram of an NMOS LDO structure.
FIG. 5 is a schematic diagram of an NMOS LDO structure of a charge pump according to an embodiment of an LDO circuit for an AC-DC power driver chip start-up circuit.
Fig. 6 is a block diagram of a whole AC-DC power driving chip start-up circuit corresponding to the LDO circuit shown in fig. 5.
Fig. 7 is a waveform diagram illustrating operation of the circuit of fig. 6.
FIG. 8 is a schematic diagram of an NMOS LDO structure of a charged pump according to another embodiment of an LDO circuit for an AC-DC power driving chip start-up circuit.
Fig. 9 is a waveform diagram of the operation of the circuit shown in fig. 8.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Exemplary embodiments of the present invention are illustrated in the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and not limited to the technical solutions of the present application, and the embodiments of the present invention and the technical features in the embodiments may be combined with each other without conflict.
The LDO structure is applied to an AC-DC power supply driving chip starting circuit.
In order to solve the problem that the minimum operating voltage of the NMOS LDO in fig. 4 does not meet the application requirement of the low power consumption system, an embodiment of the present invention designs the NMOS LDO circuit structure of the charge pump shown in fig. 5, wherein the block diagram of the entire corresponding start-up circuit is shown in fig. 6, and the operating waveform of the start-up circuit is shown in fig. 7.
As shown in fig. 6, after the enable signal horn 1 of the LDO circuit output by the power-on reset module passes through the delay module, a horn 2 signal is output, where both the horn 1 signal and the horn 2 signal are used as the enable signal of the LDO circuit, and after the horn 2 signal passes through the first-stage delay module, the horn signal is output to the system post-stage module.
As shown in fig. 5, an embodiment of the present invention provides an LDO circuit for an AC-DC power supply driving chip starting circuit, where the LDO circuit outputs a stable voltage signal according to an input reference voltage signal vref_ldo under the triggering of a first enable signal horn 1 and a second enable signal horn 2 to supply power to a bandgap reference module and a reference voltage and bias current module in the AC-DC power supply driving chip starting circuit, and the LDO circuit includes a charge pump module, an error amplifying module, a loop stability compensation module, a voltage feedback module, and an output power tube module.
The second enable signal horn 2 is obtained by delaying the first enable signal horn 1.
The charge pump module is used for supplying power to the error amplifying module, the voltage input end of the charge pump module is connected with the working power supply VDD, the enabling input end of the charge pump module is connected with the first enabling signal, the output end of the charge pump module is connected with the positive power input end of the error amplifying module, and the charge pump module starts to work when the first enabling signal is triggered.
The error amplifying module is used for amplifying the difference value between the input reference voltage and the feedback voltage, the forward input end of the error amplifying module is connected with the reference voltage, and the reverse input end of the error amplifying module is connected with the output end of the voltage feedback module.
The input end of the loop stability compensation module is connected with the output end of the error amplification module and is used for guaranteeing the stability of the loop of the voltage feedback module.
The input end of the voltage feedback module is connected with the output end of the loop stability compensation module.
The output power tube module is an NMOS field effect tube mn7, the grid electrode of the NMOS field effect tube is connected with the loop stability compensation module, the drain electrode of the NMOS field effect tube is connected with an input power supply VCC of the LDO circuit, and the source electrode of the NMOS field effect tube is grounded after passing through the voltage feedback module.
The error amplifying module comprises a first field effect transistor mp0, a second field effect transistor mp1, a third field effect transistor mp2, a fourth field effect transistor mp3, a fifth field effect transistor mp4, a sixth field effect transistor mp5, a seventh field effect transistor mp6, an eighth field effect transistor mn0, a ninth field effect transistor mn1, a tenth field effect transistor mn2, an eleventh field effect transistor mn3, a twelfth field effect transistor mp10 and a thirteenth field effect transistor mp11, wherein the drain electrode of the thirteenth field effect transistor mp11 is connected with the output end of the charge pump module, and the grid electrode is connected with the drain electrode of the twelfth field effect transistor mp10 after being connected with the source electrode; the grid electrode of the twelfth field effect transistor mp10 is connected with a working power supply VCC, and the source electrode is grounded; the drain electrode of the seventh field effect transistor mp6 is connected with the output end of the charge pump module, and the source electrode is connected with the drain electrodes of the first field effect transistor mp0 and the second field effect transistor mp 1; the grid electrode of the first field effect transistor mp0 is connected with an input reference signal vref_ldo, and the source electrode is grounded through the tenth field effect transistor mn 2; the grid electrode of the second field effect tube mp1 is connected with the output end of the voltage feedback module, and the source electrode is grounded through the eleventh field effect tube mn 3; the drains of the third field effect transistor mp2 and the fourth field effect transistor mp3 are connected with the output end of the charge pump module, the grid electrode of the third field effect transistor mp2 is connected with the grid electrode of the fourth field effect transistor mp3, the source electrode of the third field effect transistor mp2 is connected with the drain electrode of the fifth field effect transistor mp4, the source electrode of the fourth field effect transistor mp3 is connected with the drain electrode of the sixth field effect transistor mp5, the grid electrode of the fifth field effect transistor mp4 is connected with the grid electrode of the sixth field effect transistor mp5, and the source electrodes of the fifth field effect transistor mp4 and the sixth field effect transistor mp5 are respectively connected with the drain electrodes of the eighth field effect transistor mn0 and the ninth field effect transistor mn 1; the source electrode of the fifth field effect transistor mp4 is connected with the grid electrode of the third field effect transistor mp 2; the grid electrode of the eighth field effect tube mn0 is connected with the grid electrode of the ninth field effect tube mn1, the source electrodes of the eighth field effect tube mn0 and the ninth field effect tube mn1 are respectively connected with the drain electrodes of the tenth field effect tube mn2 and the eleventh field effect tube mn3, the tenth field effect tube mn2 is connected with the grid electrode of the eleventh field effect tube mn3, and the source electrodes of the tenth field effect tube mn2 and the eleventh field effect tube mn3 are grounded.
The loop stability compensation module comprises a sixteenth field effect transistor mp7, a seventeenth field effect transistor mp8, an eighteenth field effect transistor mp9 and a second capacitor Cc; the drain electrode of the sixteenth field effect transistor mp7 is connected with the source electrode of the output power transistor mn7, is also connected with the output end of the LDO circuit, the grid electrode is connected with the second enabling signal, and the source electrode is connected with the input end of the voltage feedback module; the drain electrode of the seventeenth field effect transistor mp8 is connected with the working power supply VCC, the grid electrode of the seventeenth field effect transistor mp8 is connected with a third enabling signal, the third enabling signal is obtained by inverting the second enabling signal, and the source electrode of the seventeenth field effect transistor mp8 is connected with the output end of the LDO circuit after being connected with the source electrode of the output power transistor mn 7; the drain electrode of the eighteenth field effect transistor mp9 is connected with the output end of the charge pump module, the source electrode is respectively connected with the output end of the error amplifying module and the grid electrode of the output power transistor mn7, the drain electrode is grounded through the second capacitor Cc, the grid electrode is connected with a fourth enabling signal, and the fourth enabling signal is obtained by level conversion after the second enabling signal is inverted.
The voltage feedback module comprises a second resistor R1 and a third resistor R2, one end of the second resistor R1 is connected with the source electrode of the sixteenth field effect transistor mp7, and the other end of the second resistor R1 is connected with the voltage feedback end of the error amplifying module and is grounded through the third resistor R2.
The LDO circuit further comprises an output load module, wherein the output load module comprises a third capacitor Cload and a fourth resistor Rload, and the third capacitor Cload and the fourth resistor Rload are connected in parallel and then connected between the output end of the LDO circuit and the ground.
The working principle of the LDO circuit shown in fig. 5 is as follows:
during the start-up process, when the LDO starts to operate, the LDO does not start to operate yet, at this time, vdd=vcc is designed, when horn 1 is triggered, the charge pump starts to operate, at this time, mp8 is turned on, vdd=vcc, vpump=2×vcc, because vpump is clamped by mp10 and mp11, at this time vpump=vcc+vgsp 10+vgsp11, gate voltage vgate of mn7 is pulled up to vpump, when horn 2 is triggered, mp8 and mp9 are turned off, the loop starts to operate, at this time, vdd=vcc is switched off, vfb > vref_ldo, vgate is adjusted to 0, mn7 is turned off, cload starts to discharge, and when fb voltage vfb is smaller than vref_ldo, vgate starts to rise until vdd=vref_ldo (r1+r2)/R2, and thus, vgate is stable.
ea is supplied by vpump, vpump=2×vdd, but vpump is clamped by mp10 and mp11 to vcc+vgsp11+vgsp10, where vgsp11 and vgsp10 are the voltage differences between the gates and sources of field effect transistors mp11 and mp10, respectively, vgsp11+vgsp 10=1.2v, the minimum operating voltage of VCC is vcc=4v, vdd=3.3V, and thus the minimum voltage of vpump is vpmu=vcc+vgsp 11+vgsp10=5.2V>vdd+1.1=4.4v, so the power supply of ea does not become the minimum power bottleneck of NMOS LDOs. The minimum VCC voltage that this structure can meet is:wherein vdsn7 is the source-drain voltage difference of the fet mn7, and vdsn7=vdrop is the voltage separated from the linear region, and the full load is about 0.1V. Therefore, the LDO structure shown in fig. 5 satisfies both the minimum power supply requirement and the high power supply rejection ratio requirement, and reduces the power tube area.
As shown in fig. 7, vdd may have a downward overshoot during the switch from VCC to a stable value due to loop adjustment. The vdd down overshoot may affect the normal operation of the bandgap reference module, resulting in a reset of the bgok signal, an anomaly of the vref signal, and an infinite restart of the entire system. In order to solve the problem of the overshoot down when the LDO circuit shown in fig. 5 is started, another embodiment of the present invention designs the LDO circuit shown in fig. 8, and specifically, a voltage buffer module and an overshoot suppression module are added:
the positive input end of the voltage buffer module is connected with the reference voltage, and the negative input end of the voltage buffer module is connected with the output end;
the overshoot suppression module comprises a capacitor, the input end of the capacitor is connected with the output end of the voltage buffer module, the output end of the capacitor is connected with the forward input end of the error amplification module, the capacitor is used for charging when the LDO circuit is started, and after the LDO circuit begins to work formally, the capacitor is used for slowly discharging until the LDO output voltage reaches a stable value;
the overshoot suppression module comprises a first resistor R0, a first capacitor C0, a fourteenth field effect tube mp12 and a fifteenth field effect tube mn8, one end of the first resistor R0 is connected with the output end of the voltage buffer module, the other end of the first resistor R0 is connected with the source electrode of the fifteenth field effect tube mn8, the grid electrode of the fifteenth field effect tube mn8 and the grid electrode of the fourteenth field effect tube mp12 are jointly connected with a third enabling signal, the third enabling signal is obtained by inverting the second enabling signal, the drain electrode of the third enabling signal is connected with the source electrode of the fourteenth field effect tube mp12 and the input end of the error amplification module, the drain electrode of the fourteenth field effect tube mp12 is grounded through the first capacitor C0, and the drain electrode of the fourteenth field effect tube mp12 is connected with a working power supply VCC.
The resistance value of the first resistor R0 and the capacitance value of the first capacitor C0 need to satisfy: r0 is C0> Cc/gmp0, wherein Cc is the capacitance value of the second capacitor Cc, and gmp0 is the transconductance of the first field effect transistor mp 0.
The working waveforms of the LDO circuit shown in fig. 8 are as shown in fig. 9, and the working principle is as follows: mp12 is conducted when the power-on is started, mn8 is turned off, and vref_in is charged to VCC; after horn 2 triggers mp12 is turned off and mn8 is turned on, when vdd=vcc, vref_in > vfb, vfb > vref_ldo, vgate is equal to vpump, when vref_in is slowly discharged through R0, C0 to equal vfb, the loop starts to adjust, vref_in=vfb > vref_ldo, at which time:
vdd=vref_in*(R1+R2)/R2
as vref_in continues to discharge, vdd follows a drop, and when it drops to vref_in=vref_ldo, vdd drops to a final value: vdd=vref_ldo (r1+r2)/R2.
It can be seen from fig. 9 that the vdd waveform does not appear to overshoot downwards, switching smoothly to a stable value.
According to the technical scheme, an NMOS field effect transistor is adopted as an output power transistor of the LDO circuit, a charge pump is used for supplying power to an error amplifying circuit, and a voltage buffer module and an overshoot suppression module are used for enabling output voltage of the LDO to be slowly discharged through a capacitor when being switched, so that smooth transition of the output voltage is realized. Therefore, by adopting the technical scheme of the invention, a higher power supply rejection ratio can be obtained, the minimum working voltage of the LDO circuit is reduced, and the downward overshoot during the switching of the LDO voltage is restrained, so that the performance of the LDO circuit and the stability of a system are improved.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The terms including ordinal numbers such as "first", "second", and the like used in the present specification may be used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present invention. "connecting" or "connecting" between two entities includes not only directly connecting the two entities, but also indirectly connecting through other entities having beneficial improvements.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made thereto by those of ordinary skill in the art without departing from the spirit of the present invention and the scope of the appended claims, which fall within the protection of the present invention.
Claims (8)
1. The LDO circuit for the AC-DC power supply driving chip starting circuit is characterized in that the circuit outputs a stable voltage signal to supply power for part of modules in the AC-DC power supply driving chip starting circuit according to an input reference voltage signal under the triggering of a first enabling signal and a second enabling signal, and the LDO circuit comprises a voltage buffer module, a charge pump module, an error amplifying module, a loop stability compensation module, a voltage feedback module, an output power tube module and an overshoot suppression module;
the second enabling signal is obtained by delaying the first enabling signal;
the charge pump module is used for supplying power to the error amplifying module, the voltage input end of the charge pump module is connected with a working power supply VDD, the enabling input end of the charge pump module is connected with the first enabling signal, the output end of the charge pump module is connected with the positive power input end of the error amplifying module, and the charge pump module starts to work when the first enabling signal is triggered;
the positive input end of the voltage buffer module is connected with the reference voltage, and the negative input end of the voltage buffer module is connected with the output end;
the overshoot suppression module comprises a capacitor, the input end of the capacitor is connected with the output end of the voltage buffer module, the output end of the capacitor is connected with the forward input end of the error amplification module, the capacitor is used for charging when the LDO circuit is started, and after the LDO circuit begins to work formally, the capacitor is used for slowly discharging until the LDO output voltage reaches a stable value;
the error amplification module is used for amplifying the difference value between the input reference voltage and the feedback voltage, the forward input end of the error amplification module is connected with the output end of the voltage buffer module through the overshoot suppression module, and the reverse input end of the error amplification module is connected with the output end of the voltage feedback module;
the input end of the loop stability compensation module is connected with the output end of the error amplification module and is used for guaranteeing the stability of the loop of the voltage feedback module;
the input end of the voltage feedback module is connected with the output end of the loop stability compensation module;
the output power tube module is an NMOS field effect tube.
2. The LDO circuit for the AC-DC power driving chip starting circuit according to claim 1, wherein the output power tube module is an NMOS field effect tube (mn 7), the grid electrode of the NMOS field effect tube is connected with the loop stability compensation module, the drain electrode of the NMOS field effect tube is connected with the input power VCC of the LDO circuit, and the source electrode of the NMOS field effect tube is grounded after passing through the voltage feedback module.
3. The LDO circuit for an AC-DC power supply driven chip start-up circuit of claim 1, wherein the error amplification module comprises a first fet (mp 0), a second fet (mp 1), a third fet (mp 2), a fourth fet (mp 3), a fifth fet (mp 4), a sixth fet (mp 5), a seventh fet (mp 6), an eighth fet (mn 0), a ninth fet (mn 1), a tenth fet (mn 2), an eleventh fet (mn 3), a twelfth fet (mp 10), a thirteenth fet (mp 11), the drain of the thirteenth fet (mp 11) being connected to the output of the charge pump module, the gate being connected to the source and then to the drain of the twelfth fet (mp 10); the grid electrode of the twelfth field effect transistor (mp 10) is connected with a working power supply VCC, and the source electrode is grounded; the drain electrode of the seventh field effect tube (mp 6) is connected with the output end of the charge pump module, and the source electrode is connected with the drain electrodes of the first field effect tube (mp 0) and the second field effect tube (mp 1); the grid electrode of the first field effect tube (mp 0) is connected with the output end of the overshoot suppression module, and the source electrode is grounded through the tenth field effect tube (mn 2); the grid electrode of the second field effect tube (mp 1) is connected with the output end of the voltage feedback module, and the source electrode is grounded through the eleventh field effect tube (mn 3); the drains of the third field effect tube (mp 2) and the fourth field effect tube (mp 3) are connected with the output end of the charge pump module, the grid electrode of the third field effect tube (mp 2) is connected with the grid electrode of the fourth field effect tube (mp 3), the source electrode of the third field effect tube (mp 2) is connected with the drain electrode of the fifth field effect tube (mp 4), the source electrode of the fourth field effect tube (mp 3) is connected with the drain electrode of the sixth field effect tube (mp 5), the grid electrode of the fifth field effect tube (mp 4) is connected with the grid electrode of the sixth field effect tube (mp 5), and the source electrodes of the fifth field effect tube (mp 4) and the sixth field effect tube (mp 5) are respectively connected with the drain electrodes of the eighth field effect tube (mn 0) and the ninth field effect tube (mn 1); the source electrode of the fifth field effect transistor (mp 4) is connected with the grid electrode of the third field effect transistor (mp 2); the grid electrode of the eighth field effect tube (mn 0) is connected with the grid electrode of the ninth field effect tube (mn 1), the source electrodes of the eighth field effect tube (mn 0) and the ninth field effect tube (mn 1) are respectively connected with the drain electrodes of the tenth field effect tube (mn 2) and the eleventh field effect tube (mn 3), the tenth field effect tube (mn 2) is connected with the grid electrode of the eleventh field effect tube (mn 3), and the source electrodes of the tenth field effect tube (mn 2) and the eleventh field effect tube (mn 3) are grounded.
4. An LDO circuit for an AC-DC power drive chip start-up circuit according to claim 3, wherein the loop stability compensation module comprises a sixteenth field effect transistor (mp 7), a seventeenth field effect transistor (mp 8), an eighteenth field effect transistor (mp 9), a second capacitor (Cc); the drain electrode of the sixteenth field effect transistor (mp 7) is connected with the source electrode of the output power transistor (mn 7), is also connected with the output end of the LDO circuit, the grid electrode is connected with the second enabling signal, and the source electrode is connected with the input end of the voltage feedback module; the drain electrode of the seventeenth field effect transistor (mp 8) is connected with a working power supply VCC, the grid electrode of the seventeenth field effect transistor is connected with a third enabling signal, the third enabling signal is obtained by reversing the second enabling signal, and the source electrode of the seventeenth field effect transistor is connected with the source electrode of the output power transistor (mn 7) and then is connected with the output end of the LDO circuit; the drain electrode of the eighteenth field effect transistor (mp 9) is connected with the output end of the charge pump module, the source electrode is respectively connected with the output end of the error amplifying module and the grid electrode of the output power transistor (mn 7), the drain electrode is grounded through the second capacitor (Cc), the grid electrode is connected with a fourth enabling signal, and the fourth enabling signal is obtained by level conversion after the second enabling signal is inverted.
5. The LDO circuit for an AC-DC power supply driven chip start circuit of claim 4, wherein the overshoot suppression module comprises a first resistor (R0), a first capacitor (C0), a fourteenth field effect transistor (mp 12), and a fifteenth field effect transistor (mn 8), wherein one end of the first resistor (R0) is connected to the output terminal of the voltage buffer module, the other end is connected to the source terminal of the fifteenth field effect transistor (mn 8), the gate terminal of the fifteenth field effect transistor (mn 8) and the gate terminal of the fourteenth field effect transistor (mp 12) are commonly connected to a third enable signal, the third enable signal is obtained by inverting the second enable signal, the drain terminal is connected to the source terminal of the fourteenth field effect transistor (mp 12), is connected to the input terminal of the error amplification module, and is further grounded via the first capacitor (C0), and the drain terminal of the fourteenth field effect transistor (mp 12) is connected to a working power supply VCC.
6. The LDO circuit for an AC-DC power driving chip start-up circuit of claim 5, wherein the resistance value of the first resistor (R0), the capacitance value of the first capacitor (C0) needs to satisfy: r0 is C0> Cc/gmp0, wherein Cc is the capacitance value of the second capacitor (Cc), and gmp0 is the transconductance of the first field effect transistor (mp 0).
7. The LDO circuit for an AC-DC power supply driven chip start-up circuit of claim 4, wherein said voltage feedback module comprises a second resistor (R1) and a third resistor (R2), said second resistor (R1) having one end connected to the source of said sixteenth fet (mp 7) and the other end connected to the voltage feedback end of the error amplification module and connected to ground via said third resistor (R2).
8. The LDO circuit for an AC-DC power driven chip start-up circuit of claim 1, further comprising an output load module comprising a third capacitor (Cload) and a fourth resistor (Rload), the third capacitor (Cload) being connected in parallel with the fourth resistor (Rload) and then connected between the output of the LDO circuit and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311553421.2A CN117277783B (en) | 2023-11-21 | LDO circuit applied to AC-DC power supply driving chip starting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311553421.2A CN117277783B (en) | 2023-11-21 | LDO circuit applied to AC-DC power supply driving chip starting circuit |
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| Publication Number | Publication Date |
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| CN117277783A true CN117277783A (en) | 2023-12-22 |
| CN117277783B CN117277783B (en) | 2024-04-26 |
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