CN111338413A - Low dropout regulator with high power supply rejection ratio - Google Patents
Low dropout regulator with high power supply rejection ratio Download PDFInfo
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
A low dropout linear regulator with high power supply rejection ratio is provided with an auxiliary module and a buffer stage which are connected with the output end of an error amplifier and the control end of a power switch tube, wherein the power switch tube is scaled down and copied in the auxiliary module to obtain a first switch tube, the first switch tube flows through the current of a first direct current source and forms a current mirror structure with a second switch tube, and the current of the mirror image of the second switch tube generates voltage drop on a first resistor to obtain an auxiliary voltage signal which is connected with the inverting input end of a first operational amplifier; the first operational amplifier, the second resistor and the third resistor form a proportional amplification circuit to process the auxiliary voltage signal and output the auxiliary voltage signal to the buffer stage; when the grid voltage of the power switch tube is increased or decreased, the buffer stage reduces or increases the load current flowing through the power switch tube, so that the output voltage of the low dropout linear regulator is decreased or increased, and the change of the output voltage is counteracted; and the grid voltage of the power switch tube does not change along with the change of the power supply ripple, thereby realizing high power supply rejection ratio.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and relates to a low dropout regulator circuit with a high power supply rejection ratio.
Background
As shown in fig. 1, a conventional low dropout regulator circuit is usually disposed in front of a power receiving unit, and a typical low dropout regulator structure generally comprises a voltage reference source VREF, an error amplifier EA, a power transistor MP, a feedback network Rf1 and Rf 2. The working principle is as follows: the output voltage is sampled by a negative feedback system and then compared with a reference voltage, and the output voltage Vout is stabilized by loop regulation. The error amplifier EA is used for comparing the sampling voltage with a reference voltage; the power transistor is a flow channel of load current, and the conduction strength of the power transistor is controlled by a negative feedback loop, and a PMOS (P-channel metal oxide semiconductor) tube is usually used.
However, when the output voltage Vout of the conventional low dropout regulator circuit rises, the feedback voltage after passing through the resistor voltage-dividing feedback network also rises, which causes the output voltage of the error amplifier to rise, so that the output voltage of the low dropout regulator circuit is unstable. In addition, in the conventional low dropout linear regulator circuit, ripple and noise on a power supply flow into a load and a gate end coupled to a power transistor through the power transistor, and then the ripple and the noise are converted into current of an output end through a large transconductance of the power transistor and flow into the load, which has a large influence on the power supply rejection ratio of the low dropout linear regulator circuit.
Disclosure of Invention
Aiming at the defects of unstable output voltage and large influence on the power supply rejection ratio of the traditional low-dropout linear regulator, the invention provides a low-dropout linear regulator circuit with a high power supply rejection ratio.
The technical scheme of the invention is as follows:
a low dropout regulator with high power supply rejection ratio comprises an error amplifier, a power switch tube, a first feedback resistor, a second feedback resistor and a first capacitor,
the inverting input end of the error amplifier is connected with the reference voltage, and the output end of the error amplifier is connected with the control end of the power switch tube;
two ends of the power switch tube are respectively connected with the power voltage and the output end of the low dropout linear regulator;
the first feedback resistor and the second feedback resistor are connected in series and are connected between the output end of the low-dropout linear voltage regulator and the ground, and the series point of the first feedback resistor and the second feedback resistor is connected with the non-inverting input end of the error amplifier;
the first capacitor is connected between the output end of the low dropout linear regulator and the ground;
the low dropout regulator further comprises an auxiliary module and a buffer stage,
the auxiliary module comprises a first direct current source, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first operational amplifier, wherein the first switch tube is obtained by scaling down and copying the power switch tube;
the first switching tube flows through the current of the first direct current source and forms a current mirror structure with the second switching tube, and the current mirrored by the second switching tube generates voltage drop on the first resistor to obtain an auxiliary voltage signal;
the inverting input end of the first operational amplifier is connected with the auxiliary voltage signal, the non-inverting input end of the first operational amplifier is connected with one end of the second resistor and one end of the third resistor, and the output end of the first operational amplifier is used as the output end of the auxiliary module and connected with the other end of the third resistor; the other end of the second resistor is grounded;
the buffer stage comprises a fourth resistor, a second operational amplifier, a second direct current source, a third direct current source, a ninth PMOS tube, a fifth NMOS tube and a sixth NMOS tube,
one end of the fourth resistor is connected with the output end of the auxiliary module, and the other end of the fourth resistor is connected with the inverted input end of the second operational amplifier;
the grid electrode of the ninth PMOS tube is connected with the non-inverting input end and the output end of the second operational amplifier, the source electrode of the ninth PMOS tube is connected with the second direct current source, and the drain electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube;
the source electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube and is grounded, and the drain electrode of the sixth NMOS tube is used as the output end of the buffer stage and is connected with a second direct current source;
and the output end of the buffer stage is connected with the control end of the power switch tube.
Specifically, the power switch tube is a PMOS power tube, a gate of the PMOS power tube is used as a control end of the power switch tube to connect the output end of the error amplifier and the output end of the buffer stage, a source of the PMOS power tube is connected to the power voltage, and a drain of the PMOS power tube is connected to the output end of the low dropout linear regulator.
Specifically, the first switch tube is a seventh PMOS tube, the second switch tube is an eighth PMOS tube, a gate drain of the seventh PMOS tube is in short circuit and is connected with a gate of the eighth PMOS tube and a first direct current source, and a source of the seventh PMOS tube is connected with a source of the eighth PMOS tube and is connected with a power supply voltage; one end of the first resistor is grounded, and the other end of the first resistor is connected with the drain electrode of the eighth PMOS tube and outputs the auxiliary voltage signal.
Specifically, the power switch tube is an NMOS power tube, a gate of the NMOS power tube is used as a control end of the power switch tube to connect the output end of the error amplifier and the output end of the buffer stage, a drain of the NMOS power tube is connected to the power supply voltage, and a source of the NMOS power tube is connected to the output end of the low dropout linear regulator.
Specifically, the first switch tube is a seventh NMOS tube, the second switch tube is an eighth NMOS tube, a gate-drain short circuit of the seventh NMOS tube is connected to a gate of the eighth NMOS tube and a first direct current source, and a source electrode of the seventh NMOS tube is connected to a source electrode of the eighth NMOS tube and grounded; one end of the first resistor is connected with a power supply voltage, and the other end of the first resistor is connected with the drain electrode of the eighth NMOS tube and outputs the auxiliary voltage signal.
Specifically, the error amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a fourth DC current source,
the grid electrode of the third PMOS tube is used as the inverting input end of the error amplifier, the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube;
the grid electrode of the fourth PMOS tube is used as the non-inverting input end of the error amplifier, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube;
the grid-drain short circuit of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the fourth direct current source, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with power supply voltage;
the grid electrode of the sixth PMOS tube is connected with the drain electrode of the third NMOS tube and the grid electrode and the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as the output end of the error amplifier;
the source electrodes of the first NMOS tube, the second NMOS tube and the fourth NMOS tube are grounded.
The invention has the beneficial effects that: according to the invention, the buffer stage and the auxiliary module are introduced into the low dropout regulator, so that when the input power supply voltage is higher than the set voltage, the output power supply voltage is constant to be the set output voltage, the output voltage is stabilized, the output power supply voltage is less influenced by temperature change and process deviation, and meanwhile, the cleaner power supply voltage with smaller power supply ripple can be provided for the power receiving unit.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional low dropout regulator.
Fig. 2 is a block diagram of the low dropout regulator with high power supply rejection ratio according to the present invention, when the power transistor is a PMOS power transistor.
Fig. 3 is a circuit implementation structure diagram of an error amplifier in a low dropout regulator with a high power supply rejection ratio according to the present invention.
Fig. 4 is a schematic diagram of an implementation circuit structure of an auxiliary module and a buffer stage of the low dropout regulator with a high power supply rejection ratio when a power transistor is a PMOS power transistor.
Fig. 5 is a block diagram of the low dropout regulator with high power supply rejection ratio according to the present invention, when the power transistor is an NMOS power transistor.
Fig. 6 is a schematic diagram of an implementation circuit structure of an auxiliary module and a buffer stage of the low dropout regulator with a high power supply rejection ratio when a power transistor is an NMOS power transistor.
Detailed Description
The technical scheme of the invention is detailed below by combining the accompanying drawings and the embodiment.
The invention provides a low dropout regulator with high power supply rejection ratio, which comprises an error amplifier, a power switch tube and a first feedback resistor R6A second feedback resistor R7And a first capacitor CLThe inverting input terminal of the error amplifier is connected with a reference voltage VREFThe output end of the power switch tube is connected with the control end of the power switch tube; the two ends of the power switch tube are respectively connected with a power supply voltage VDDAnd an output terminal of the low dropout linear regulator; first feedback resistor R6And a second feedback resistor R7A feedback network is formed and connected in series between the output end of the low-dropout linear regulator and the ground, and the series point of the feedback network is connected with the non-inverting input end of the error amplifier; a first capacitor CLAnd the low dropout linear regulator is connected between the output end of the low dropout linear regulator and the ground.
Wherein the power switch tube is a PMOS tube, as shown in FIG. 2, the power switch tube is a PMOS power tube MPPMOS power tube MPThe grid electrode of the power switch tube is used as the control end of the power switch tube and is connected with the output end of the error amplifier and the output end of the buffer stage, and the source electrode of the power switch tube is connected with the power supply voltage VDDAnd the drain electrode of the low dropout regulator is connected with the output end of the low dropout regulator.
In some cases, the power switch tube may also be an NMOS tube, as shown in fig. 5, the power switch tube is an NMOS power tube MNNMOS power tube MNThe grid electrode of the power switch tube is used as the control end of the power switch tube and is connected with the output end of the error amplifier and the output end of the buffer stage, and the drain electrode of the power switch tube is connected with the power supply voltage VDDThe source electrode of the low dropout linear regulator is connected with the output of the low dropout linear regulatorAnd (4) an end.
The working principle of the low dropout linear regulator provided by the invention is as follows: at the input power Vin, i.e. the supply voltage VDDAfter power-on, the output voltage Vout of the low dropout linear regulator is sampled by using a negative feedback system and then is compared with a reference voltage, namely a reference voltage VREFThe comparison is performed and the output voltage Vout is stabilized by the regulation of the loop. The error amplifier is used for comparing the sampling voltage with a reference voltage VREFComparing; power switch tube (with PMOS power tube M)PFor example) is the flow path of the load current, and the conduction strength is controlled by a negative feedback loop.
When the output voltage Vout rises, the feedback voltage VFB after passing through the resistor voltage-dividing feedback network also rises, and the output voltage of the error amplifier rises, which causes unstable output of the low dropout linear regulator. The invention is provided with a buffer stage which is an in-phase buffer, so that the PMOS power tube MPIs increased to reduce the current flowing through the PMOS power tube MPThe output voltage Vout is lowered, thereby canceling the variation in the rise of the output voltage Vout. Similarly, when the output voltage Vout drops, the loop control will make the current flow through the PMOS power transistor MPThe load current increases to raise the output voltage Vout and finally the output voltage Vout is stabilized. PMOS power tube M in practical situationPThe output impedance of the power supply is not infinite, so that ripples and noises on the power supply pass through the PMOS power tube MPOutput impedance r ofdsAnd a capacitance C between the drain and the substratedbFlowing into the load, and through the PMOS power transistor MPGate source capacitance C ofgsThe auxiliary module is coupled to a grid end of the power tube, and then the current is converted into current of an output end through larger transconductance of the power tube to flow into a load, and the current greatly influences the power supply rejection ratio of the low dropout linear regulator circuit.
The auxiliary module comprises a first direct current source I0, a first switch tube, a second switch tube, a first resistor R2, a second resistor R3, a third resistor R4 and a first operational amplifier OP1, wherein the first switch tube is obtained by scaling down and copying a power switch tube; the first switching tube flows through the current of the first direct current source I0 and forms a current mirror structure with the second switching tube, and the current mirrored by the second switching tube generates a voltage drop on the first resistor R2 to obtain an auxiliary voltage signal; the inverting input end of the first operational amplifier OP1 is connected with the auxiliary voltage signal, the non-inverting input end thereof is connected with one end of the second resistor R3 and one end of the third resistor R4, and the output end thereof is used as the output end of the auxiliary module and is connected with the other end of the third resistor R4; the other end of the second resistor R3 is connected to ground.
The first switch tube and the second switch tube form a current mirror structure, and the first switch tube is obtained by scaling down and copying the power switch tube, so when the power switch tube is a PMOS tube, the first switch tube and the second switch tube are also PMOS tubes, as shown in fig. 4, the first switch tube is a seventh PMOS tube MP6, the second switch tube is an eighth PMOS tube MP7, the gate drain of the seventh PMOS tube MP6 is shorted, and is connected to the gate of the eighth PMOS tube MP7 and the first dc current source I0, and the source thereof is connected to the source of the eighth PMOS tube MP7 and to the supply voltage VDD; one end of the first resistor R2 is grounded, and the other end is connected to the drain of the eighth PMOS transistor MP7 and outputs an auxiliary voltage signal.
Therefore, when the power switch tube is an NMOS tube, the first switch tube and the second switch tube are also NMOS tubes, as shown in fig. 6, the first switch tube is a seventh NMOS tube MN6, the second switch tube is an eighth NMOS tube MP7, the gate-drain short circuit of the seventh NMOS tube MN6 connects the gate of the eighth NMOS tube MP7 and the first dc current source I0, and the source thereof is connected to the source of the eighth NMOS tube MP7 and grounded; one end of the first resistor R2 is connected to the power voltage VDD, and the other end is connected to the drain of the eighth NMOS transistor MP7 and outputs the auxiliary voltage signal.
As shown in fig. 4 and fig. 6, the buffer stage includes a fourth resistor R5, a second operational amplifier OP2, a second dc current source I1, a third dc current source I2, a ninth PMOS transistor, a fifth NMOS transistor MN4, and a sixth NMOS transistor MN5, wherein one end of the fourth resistor R5 is connected to the output end of the auxiliary module, and the other end is connected to the inverting input end of the second operational amplifier OP 2; the grid electrode of the ninth PMOS tube is connected with the non-inverting input end and the output end of the second operational amplifier OP2, the source electrode of the ninth PMOS tube is connected with the second direct current source I1, and the drain electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube MN4 and the grid electrode of the sixth NMOS tube MN 5; the source electrode of the sixth NMOS transistor MN5 is connected to the source electrode of the fifth NMOS transistor MN4 and grounded, and the drain electrode thereof is used as the output end of the buffer stage and connected to the second dc current source I1; the output end of the buffer stage is connected with the control end of the power switch tube.
Under the condition of medium and low frequency, the loop gain of the low dropout linear regulator circuit is improved, and the power supply rejection ratio can be effectively improved. However, at high frequencies, since there is no large off-chip capacitance to filter out power supply noise, it is necessary to design auxiliary circuits to enhance the performance of the power supply rejection ratio PSR at high frequencies. The main factors affecting the power supply rejection ratio at high frequencies are the small signal path from the power supply to the output and the voltage division due to the finite output impedance of the power switch tube. The invention designs a path, and the signal is injected into the grid end of the power switch tube through a buffer for compensation, so that the grid voltage of the power switch tube does not change along with the change of power supply ripple waves, namely under the AC condition, the grid voltage of the power switch tube is 0, and the effect of inhibiting the power supply ripple waves is ensured.
Power switch tube is PMOS power tube MPFor illustration, the specific implementation is to design a PMOS power transistor M in the buffer stage and the auxiliary modulePThe drain current generated by the influence of the power ripple flowing through the seventh PMOS tube MP6 of the seventh PMOS tube MP6 which is copied in a scaling-down manner is
Wherein id_mp6Is the drain current, C, generated by the seventh PMOS transistor MP6 under the influence of the power ripplegdrIs the gate-drain capacitance, C, of the seventh PMOS transistor MP6gsrIs the gate-source capacitance g of the seventh PMOS transistor MP6mp6Is the transconductance of a seventh PMOS transistor MP6, rdsmp6Is the output resistance of the seventh PMOS transistor MP 6.
Since the second term in the above equation is much smaller than the first term, it can be considered that
id_mp6The current signal can effectively track the variation of the power supply ripple, and the current is still sC after passing through the current mirror formed by the seventh PMOS tube MP6 and the eighth PMOS tube MP7gdrVddAnd a magnitude of sC is generated on the first resistor R2gdrVddThe voltage drop of R2 is amplified by a proportional amplifier circuit composed of a first operational amplifier OP1, a second resistor R3 and a third resistor R4 to obtain a voltage sCgdrVddR2 (1+ R4/R3), the value of this amplified signal obtained by passing through the voltage follower constituted by the second operational amplifier OP2 is still sCgdrVddR2 (1+ R4/R3), the signal is converted into a current signal sC through the transconductance of a ninth PMOS tube MP8gdrVddR2*(1+R4/R3)*gmp8By properly designing the proportional relationship among the first resistor R2, the second resistor R3 and the third resistor R4 and the ninth PMOS transistor MP8, the following structure can be obtained
Wherein C isgdIs a PMO S power tube MPGate to drain capacitance of gmp8Is the transconductance of the ninth PMOS transistor MP 8.
sCgdVddThe signal reaches the output end of the buffer stage through a current mirror composed of a fifth NMOS transistor MN4 and a sixth NMOS transistor MN5, and is injected into the PMOS power transistor M from the output end of the buffer stagePThe grid electrode is used for offsetting a small signal path from a power supply to an output and voltage division generated by limited output impedance of the power switch tube, thereby realizing the function of improving the power supply rejection ratio.
As shown in fig. 3, an implementation structure of the error amplifier is given, and in addition, other voltage amplifiers with appropriate input common-mode voltage may also be used, where the error amplifier in this embodiment includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP3, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, and a fourth dc current source, a gate of the third PMOS transistor serves as an inverting input terminal of the error amplifier, a source of the third PMOS transistor MP3 is connected to a source of the fourth PMOS transistor MP1, and a drain of the third PMOS transistor MP3 is connected to a gate and a drain of the first NMOS transistor MN0, and a gate of the second NMOS transistor MN1 is connected to a gate of the fourth NMOS transistor MN 3; the grid electrode of the fourth PMOS tube MP3 is used as the non-inverting input end of the error amplifier, and the drain electrode of the fourth PMOS tube MP3 is connected with the drain electrode of the second NMOS tube MN1 and the grid electrode of the third NMOS tube MN 2; the grid-drain short circuit of the first PMOS tube MP0 is connected with the grid electrode of the second PMOS tube MP1 and a fourth direct current source, and the source electrode of the first PMOS tube MP0 is connected with the source electrodes of the second PMOS tube MP1, the fifth PMOS tube MP4 and the sixth PMOS tube MP5 and is connected with a power supply voltage VDD; the grid electrode of the sixth PMOS tube MP5 is connected with the drain electrode of the third NMOS tube MN2 and the grid electrode and the drain electrode of the fifth PMOS tube MP4, and the drain electrode of the sixth PMOS tube MP5 is connected with the drain electrode of the fourth NMOS tube MN3 and serves as the output end of the error amplifier; the sources of the first NMOS transistor MN0, the second NMOS transistor MN1, and the fourth NMOS transistor MN3 are grounded.
In summary, by arranging the buffer stage and the auxiliary module, when the gate voltage of the power switch tube is increased or decreased, the load current flowing through the power switch tube is reduced or increased, so that the output voltage of the low dropout linear regulator is decreased or increased, thereby offsetting the change of the output voltage, and the output power supply voltage is less affected by temperature change and process deviation, thereby realizing stable output voltage; in addition, the signal is injected into the grid end of the power switch tube through the buffer stage for compensation, so that the grid voltage of the power switch tube does not change along with the change of the power supply ripple, the effect of inhibiting the power supply ripple is realized, and the power supply rejection ratio is improved.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (6)
1. A low dropout regulator with high power supply rejection ratio comprises an error amplifier, a power switch tube, a first feedback resistor, a second feedback resistor and a first capacitor,
the inverting input end of the error amplifier is connected with the reference voltage, and the output end of the error amplifier is connected with the control end of the power switch tube;
two ends of the power switch tube are respectively connected with the power voltage and the output end of the low dropout linear regulator;
the first feedback resistor and the second feedback resistor are connected in series and are connected between the output end of the low-dropout linear voltage regulator and the ground, and the series point of the first feedback resistor and the second feedback resistor is connected with the non-inverting input end of the error amplifier;
the first capacitor is connected between the output end of the low dropout linear regulator and the ground;
characterized in that the low dropout regulator further comprises an auxiliary module and a buffer stage,
the auxiliary module comprises a first direct current source, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first operational amplifier, wherein the first switch tube is obtained by scaling down and copying the power switch tube;
the first switching tube flows through the current of the first direct current source and forms a current mirror structure with the second switching tube, and the current mirrored by the second switching tube generates voltage drop on the first resistor to obtain an auxiliary voltage signal;
the inverting input end of the first operational amplifier is connected with the auxiliary voltage signal, the non-inverting input end of the first operational amplifier is connected with one end of the second resistor and one end of the third resistor, and the output end of the first operational amplifier is used as the output end of the auxiliary module and connected with the other end of the third resistor; the other end of the second resistor is grounded;
the buffer stage comprises a fourth resistor, a second operational amplifier, a second direct current source, a third direct current source, a ninth PMOS tube, a fifth NMOS tube and a sixth NMOS tube,
one end of the fourth resistor is connected with the output end of the auxiliary module, and the other end of the fourth resistor is connected with the inverting input end of the second operational amplifier;
the grid electrode of the ninth PMOS tube is connected with the non-inverting input end and the output end of the second operational amplifier, the source electrode of the ninth PMOS tube is connected with the second direct current source, and the drain electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube;
the source electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube and is grounded, and the drain electrode of the sixth NMOS tube is used as the output end of the buffer stage and is connected with a second direct current source;
and the output end of the buffer stage is connected with the control end of the power switch tube.
2. The low dropout regulator according to claim 1, wherein the power switch is a PMOS power transistor, a gate of the PMOS power transistor is used as a control terminal of the power switch to connect the output terminal of the error amplifier and the output terminal of the buffer stage, a source of the PMOS power transistor is connected to the power voltage, and a drain of the PMOS power transistor is connected to the output terminal of the low dropout regulator.
3. The low dropout regulator with high power supply rejection ratio according to claim 2, wherein the first switching tube is a seventh PMOS tube, the second switching tube is an eighth PMOS tube, the gate-drain short circuit of the seventh PMOS tube connects the gate of the eighth PMOS tube and the first direct current power supply, and the source of the seventh PMOS tube is connected to the source of the eighth PMOS tube and the power supply voltage; one end of the first resistor is grounded, and the other end of the first resistor is connected with the drain electrode of the eighth PMOS tube and outputs the auxiliary voltage signal.
4. The low dropout regulator according to claim 1, wherein the power switch is an NMOS power transistor, a gate of the NMOS power transistor is used as a control terminal of the power switch to connect the output terminal of the error amplifier and the output terminal of the buffer stage, a drain of the NMOS power transistor is connected to the power voltage, and a source of the NMOS power transistor is connected to the output terminal of the low dropout regulator.
5. The low dropout regulator according to claim 4, wherein the first switching transistor is a seventh NMOS transistor, the second switching transistor is an eighth NMOS transistor, a gate-drain short circuit of the seventh NMOS transistor connects a gate of the eighth NMOS transistor and the first dc current source, and a source of the seventh NMOS transistor is connected to a source of the eighth NMOS transistor and grounded; one end of the first resistor is connected with a power supply voltage, and the other end of the first resistor is connected with the drain electrode of the eighth NMOS tube and outputs the auxiliary voltage signal.
6. The low dropout regulator with high power supply rejection ratio according to any one of claims 1 to 5, wherein said error amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a fourth DC current source,
the grid electrode of the third PMOS tube is used as the inverting input end of the error amplifier, the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the grid electrode of the fourth NMOS tube;
the grid electrode of the fourth PMOS tube is used as the non-inverting input end of the error amplifier, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube;
the grid-drain short circuit of the first PMOS tube is connected with the grid electrode of the second PMOS tube and the fourth direct current source, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with power supply voltage;
the grid electrode of the sixth PMOS tube is connected with the drain electrode of the third NMOS tube and the grid electrode and the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as the output end of the error amplifier;
the source electrodes of the first NMOS tube, the second NMOS tube and the fourth NMOS tube are grounded.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113064460A (en) * | 2021-03-24 | 2021-07-02 | 成都瓴科微电子有限责任公司 | Low dropout regulator circuit with high power supply rejection ratio |
| CN113325912A (en) * | 2021-06-10 | 2021-08-31 | 深圳市微源半导体股份有限公司 | LDO circuit suitable for wide input voltage range |
| CN113721695A (en) * | 2021-08-20 | 2021-11-30 | 西安电子科技大学 | Dual-mode low dropout regulator, circuit thereof and electronic product |
| CN114200994A (en) * | 2021-12-07 | 2022-03-18 | 深圳市灵明光子科技有限公司 | Low dropout linear regulator and laser ranging circuit |
| CN114706441A (en) * | 2022-04-07 | 2022-07-05 | 南京市智凌芯科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| US11467614B2 (en) * | 2020-09-10 | 2022-10-11 | Apple Inc. | Voltage mode low-dropout regulator circuit with reduced quiescent current |
| CN115993867A (en) * | 2023-03-03 | 2023-04-21 | 重庆大学 | Low-power-consumption high-voltage linear voltage stabilizer capable of adjusting output voltage and voltage stabilizing method thereof |
| CN117277514A (en) * | 2023-11-17 | 2023-12-22 | 苏州贝克微电子股份有限公司 | Power supply circuit capable of reducing output voltage fluctuation |
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| US11467614B2 (en) * | 2020-09-10 | 2022-10-11 | Apple Inc. | Voltage mode low-dropout regulator circuit with reduced quiescent current |
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| CN113325912B (en) * | 2021-06-10 | 2022-04-01 | 深圳市微源半导体股份有限公司 | LDO circuit suitable for wide input voltage range |
| CN113721695A (en) * | 2021-08-20 | 2021-11-30 | 西安电子科技大学 | Dual-mode low dropout regulator, circuit thereof and electronic product |
| CN113721695B (en) * | 2021-08-20 | 2022-06-17 | 西安电子科技大学 | Dual-mode low dropout regulator, circuit thereof and electronic product |
| CN114200994A (en) * | 2021-12-07 | 2022-03-18 | 深圳市灵明光子科技有限公司 | Low dropout linear regulator and laser ranging circuit |
| CN114706441A (en) * | 2022-04-07 | 2022-07-05 | 南京市智凌芯科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| CN114706441B (en) * | 2022-04-07 | 2023-08-04 | 南京市智凌芯科技股份有限公司 | Low-power-consumption low-dropout linear voltage regulator |
| CN115993867A (en) * | 2023-03-03 | 2023-04-21 | 重庆大学 | Low-power-consumption high-voltage linear voltage stabilizer capable of adjusting output voltage and voltage stabilizing method thereof |
| CN117277514A (en) * | 2023-11-17 | 2023-12-22 | 苏州贝克微电子股份有限公司 | Power supply circuit capable of reducing output voltage fluctuation |
| CN117277514B (en) * | 2023-11-17 | 2024-02-09 | 苏州贝克微电子股份有限公司 | Power supply circuit capable of reducing output voltage fluctuation |
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