CN117234272B - Noise reduction circuit and noise reduction method for low dropout linear voltage regulator - Google Patents
Noise reduction circuit and noise reduction method for low dropout linear voltage regulator Download PDFInfo
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- CN117234272B CN117234272B CN202311523507.0A CN202311523507A CN117234272B CN 117234272 B CN117234272 B CN 117234272B CN 202311523507 A CN202311523507 A CN 202311523507A CN 117234272 B CN117234272 B CN 117234272B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a noise reduction circuit and a noise reduction method of a low dropout linear voltage regulator, wherein the circuit comprises a plurality of switching power supplies, the input ends of the switching power supplies are connected with the same general power supply and general clock signals, the output ends of the switching power supplies are respectively connected with a low dropout linear voltage regulator, and the output ends of the low dropout linear voltage regulators are connected in parallel and then output; the switching power supply is internally provided with a delay unit which is used for adjusting the delay time of the corresponding total clock signal so as to control the output signal of the switching power supply; the total clock signal is connected with a low-dropout linear voltage regulator output control module and is used for controlling the low-dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the switching power supply output signal. The invention can effectively solve the problem of high noise of the low dropout linear voltage regulator.
Description
Technical Field
The invention relates to the technical field of electronic circuit chips, in particular to a noise reduction circuit and a noise reduction method of a low dropout linear voltage regulator.
Background
In integrated chip circuits, power management chips are responsible for the conversion, distribution, detection, etc. of electrical power.
The low dropout linear regulator, LDO (low dropout voltage) for short, has the advantages of high conversion efficiency, small volume, low noise, few external components, low price, and the like, and is widely used, especially in portable systems with battery power supply and communication related electronic products.
At present, as shown in fig. 1, the existing LDO circuit has rectification harmonic wave, switching frequency and harmonic wave thereof and inherent high-speed current and voltage transient in switching, so that the generation of electromagnetic interference is determined by the characteristics of the switching power supply, which is difficult to avoid; that is, the output of the switching power supply often includes ripple, so that the output terminal Vout3 of the LDO also carries glitch noise.
As the signal processing frequency of the portable electronic equipment is continuously increased and the power supply voltage is continuously reduced, the output noise of the existing LDO is continuously increased; meanwhile, the output noise of the LDO can be directly converted into the power supply noise of the load circuit, so that the influence of the power supply noise on the electronic equipment is increased.
Therefore, how to design a low noise LDO to reduce the output noise of the LDO is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the present invention provides a noise reduction circuit and a noise reduction method for a low dropout linear regulator, which solve the problem that the current low dropout linear regulator cannot eliminate noise or has large output noise.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
first, the invention discloses a noise reduction circuit of a low dropout linear voltage regulator, which comprises a plurality of switching power supplies,
the input ends of the plurality of switching power supplies are connected with the same total power supply and the same total clock signal, the output ends of the plurality of switching power supplies are respectively connected with a low-dropout linear voltage regulator, and the output ends of the plurality of low-dropout linear voltage regulators are connected in parallel and then output;
the switching power supply is internally provided with a delay unit which is used for adjusting the delay time of the corresponding total clock signal so as to control the output signal of the switching power supply;
the total clock signal is connected with a low-dropout linear voltage regulator output control module and is used for controlling the low-dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the switching power supply output signal.
In order to optimize the technical scheme, the output control module of the low dropout linear voltage regulator is a sine wave generator, and the output end of the sine wave generator is connected with the reverse input end of the amplifier in the low dropout linear voltage regulator and is used for controlling the low dropout linear voltage regulator to alternately output through the output signal of the sine wave generator;
in order to optimize the technical scheme, the output signal of the sine generator is input to the reverse input end of the amplifier after being overlapped/subtracted with the reference voltage of the low dropout linear voltage regulator.
In order to optimize the technical scheme, a switch is connected before the output end of each low-dropout linear voltage stabilizer is connected in parallel, and the alternating output of each low-dropout linear voltage stabilizer is controlled by the on-off of the switch.
In order to optimize the technical scheme, the output control module of the low dropout linear voltage regulator is an inverter and is used for controlling the switch after reversing the total clock signal; or the output control module of the low dropout linear voltage regulator directly utilizes the total clock signal to control the switch.
In order to optimize the technical scheme, the ripple waves in the output signal of the switching power supply are mutually delayed by T/4n, wherein T is the period of the total clock signal, and n is an integer greater than or equal to 1.
In order to optimize the technical scheme, the voltage of the output end of the noise reduction circuit is fed back to the positive input end of each low dropout linear voltage regulator through the voltage division sampling circuit.
In order to optimize the technical scheme, in the low dropout linear voltage regulator, the output end of the amplifier is connected with the grid electrode of the PMOS, the source electrode of the PMOS is connected with the output end of the corresponding switching power supply, and the drain electrode is connected in parallel and then used as the output end of the noise reduction circuit.
In order to optimize the technical scheme, the drain electrode of the PMOS tube is connected to the grid electrode of the same PMOS tube sequentially through a capacitor and a resistor.
The invention also discloses a noise reduction method of the low-dropout linear voltage regulator, which comprises the following steps,
the output ends of a plurality of low-dropout linear voltage regulators are connected in parallel; the input end of each low-dropout linear voltage regulator shares the same power supply and the same total clock signal;
adjusting the delay time of the corresponding total clock signal and controlling the output signal of the power supply;
and controlling the low dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the power supply output signal.
Compared with the prior art, the invention discloses a noise reduction circuit and a noise reduction method for a low dropout linear voltage regulator, which are based on the principle that sine waves generated according to an input power supply are superimposed on a reference voltage of the low dropout linear voltage regulator, and are used for controlling the output of the low dropout linear voltage regulator accordingly; further, the delay of the input signal of the low dropout linear voltage regulator is set, and then the ripple wave carried by the input signal is avoided when the low dropout linear voltage regulator in the noise reduction circuit outputs under the combined action of the delay and the sine wave.
The invention effectively solves the problem of high noise of the low dropout linear voltage regulator in the prior art by improving the traditional low dropout linear voltage regulator.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram showing a structure of a conventional LDO circuit;
FIG. 2 is a diagram showing a noise reduction circuit of the LDO of the present invention;
FIG. 3 is a schematic diagram of a noise reduction circuit for controlling the alternate output of a low dropout linear regulator by a sine wave according to the present invention;
FIG. 4 is a diagram showing an example of a noise reduction circuit of a LDO when a sine wave mode is adopted;
FIG. 5 is a diagram of the input signal of the noise reduction circuit when a sine wave is used;
FIG. 6 is a graph showing the waveform comparison of input and output signals of the noise reduction circuit when sine waves are adopted;
FIG. 7 is a schematic diagram of a noise reduction circuit employing a switch to control the alternate output of a low dropout linear regulator;
fig. 8 is a diagram showing waveforms of input and output signals of the noise reduction circuit when the switch is adopted.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention discloses a noise reduction circuit and a noise reduction method for a low dropout linear voltage regulator, which are only used for reducing high noise in the current low dropout linear voltage regulator.
In order to make the present invention clearly understood, the following examples are provided.
Example 1
The invention discloses a noise reduction circuit of a low dropout linear voltage regulator, which comprises a plurality of switching power supplies, as shown in figure 2,
the input ends of the plurality of switching power supplies are connected with the same main power supply and the same main clock signal, the output ends of the plurality of switching power supplies are respectively connected with a low-dropout linear voltage regulator, and the output ends of the plurality of low-dropout linear voltage regulators are connected in parallel and then output;
the switching power supply is internally provided with a delay unit which is used for adjusting the delay time of the corresponding total clock signal so as to control the output signal of the switching power supply;
the total clock signal is connected with a low-dropout linear voltage regulator output control module and is used for controlling the low-dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the switching power supply output signal.
It should be noted that, only one LDO output module is shown in fig. 2, but the number of LDO output control modules in the drawing should not be considered as a limitation to the scheme of the present application.
Preferably, the ripple in the output signal of the switching power supply is delayed by T/4n, where T is the period of the total clock signal and n is an integer greater than or equal to 1.
Further, in the present invention, the output control module of the low dropout linear regulator may adopt the following scheme:
the output control module of the first low-dropout linear voltage regulator is a sine wave generator, and the output end of the sine wave generator is connected with the reverse input end of the amplifier in the low-dropout linear voltage regulator and is used for controlling the low-dropout linear voltage regulator to alternately output through the output signal of the sine wave generator.
In this embodiment, after the output signal of the sine generator is superimposed/subtracted with the reference voltage of the low dropout linear regulator, the output signal is input to the inverting input terminal of the amplifier;
and a switch is connected to the output end of each low-dropout linear voltage regulator before switching, and the alternating output of each low-dropout linear voltage regulator is controlled by the on-off of the switch.
At this time, the output control module of the low dropout linear voltage regulator is an inverter and is used for controlling the switch after reversing the total clock signal; or the output control module of the low dropout linear voltage regulator directly utilizes the total clock signal to control the switch.
Here, the present application provides the above two preferred modes for a moment, but should not be construed as limiting the method for controlling the alternate output of the low dropout linear regulator of the present invention.
In addition, the output end voltage of the noise reduction circuit is fed back to the positive input end of each low dropout linear voltage stabilizer through the voltage division sampling circuit. In the low dropout linear voltage regulator, the output end of the amplifier is connected with the grid electrode of the PMOS, the source electrode of the PMOS is connected with the output end of the corresponding switching power supply, and the drain electrode of the PMOS is connected in parallel and then used as the output end of the noise reduction circuit; and the drain electrode of the PMOS tube is connected to the grid electrode of the same PMOS tube through a capacitor and a resistor in sequence.
The invention can effectively reduce the output noise of the low-dropout linear voltage regulator through the matching of the sine wave signal corresponding to the power supply and the delay time of the input signal.
Example two
In this embodiment, the noise reduction circuit of the low dropout linear regulator includes two low dropout linear regulators, the structure of which is shown in fig. 3, wherein the first low dropout linear regulator and the second low dropout linear regulator are commonly connected to the total power supply and the total clock signal CLK0,
the input signal CLK1 of the first LDO is directly obtained according to the total clock signal CLK 0; the input signal CLK2 of the second low dropout linear voltage regulator is obtained after delay by a delay unit in the second switching power supply DCDC 2; as shown in fig. 4, vin1 and Vin2 are ripples carried in the final switching power supply output signal.
In this embodiment, the total clock signal CLK0 may be input to the sine wave generator sinWAVE to obtain the corresponding sine wave signal Vsin;
further, as shown in fig. 3, the sine wave signal Vsin is superimposed with the reference voltage of the amplifier in the low dropout linear regulator and then input to the inverting input terminal of the amplifier in the first low dropout linear regulator, and the superimposed sine wave signal Vsin is input to the inverting input terminal of the amplifier in the second low dropout linear regulator;
at this time, the input signals of the low dropout linear regulators correspond to the grid waveforms of the PMOS transistors and the output signals after noise reduction are shown in fig. 5 and 6;
the working principle of the noise reduction circuit of the low dropout linear voltage regulator is as follows:
when the reference voltage of the amplifier is in the trough of the sine wave, the output signal of the amplifier is increased, and the PMOS tube is basically in a closed state; when the reference voltage of the amplifier is at the peak of the sine wave, the output signal of the amplifier is reduced, and the PMOS tube is in an output state;
when the reference voltage of the first low dropout linear regulator is overlapped with the sine wave, the signal of the first low dropout linear regulator is synchronous with the sine wave, and at this time, if the first low dropout linear regulator is positioned at the peak of the sine wave, the output signal of the amplifier is reduced, and the waveform of the gate_pmos1 is opposite to the sine wave, as shown in fig. 6; at this time, the first low dropout linear regulator has an output, and its input signal can avoid the ripple wave caused by the output signal of the switching power supply;
meanwhile, because the reference voltage of the amplifier in the second low dropout linear voltage regulator is overlapped with Vsin, when the sine wave is in the trough, the second low dropout linear voltage regulator has output, and at the moment, the output signal of the second switching power supply is delayed, so that the ripple wave carried by the output signal of the second switching power supply can be avoided when the second low dropout linear voltage regulator outputs;
in order to further optimize the technical scheme, the ripple waves in the output signal of the switching power supply are mutually delayed by T/4n, wherein T is the period of the total clock signal, and n is an integer greater than or equal to 1. It is preferably at least one of T/4,
as can be seen from fig. 6, when the delay is performed by T/4, the top of the sine wave is located at the center of two ripples, and at this time, the low dropout linear regulator can be ensured to avoid the ripples in the whole output period. Namely, when the delay is carried out by T/4, the noise reduction effect is better.
The invention controls the plurality of low-dropout linear voltage regulators to alternately output through the sine wave signal of the power supply, and simultaneously cooperates with the delay of the input signal, so that the ripple wave carried by the switching power supply signal can be avoided when the low-dropout linear voltage regulator outputs, and the effect of effectively reducing noise is finally realized.
In addition, the embodiment can also control the alternate output of the low dropout linear voltage regulator through a switch; as shown in fig. 7, a switch is connected before the output end of each low dropout linear voltage regulator is connected in parallel, and the alternating output of each low dropout linear voltage regulator is controlled by the on-off of the switch.
The switching on/off of the switch is controlled by a square wave signal output by the total clock, or the switch is turned over by an inverter according to the requirement, and then the turned-over signal is used for controlling the switch to be closed, so that ripples in an output signal of the switching power supply are avoided when the corresponding low-dropout linear voltage regulator outputs. In one embodiment, the correspondence of waveforms is shown in fig. 8.
As can be seen from fig. 8, when the switch K1 is closed, i.e. the first low dropout linear regulator has an output, the switch K corresponds to a relatively smooth voltage in Vin1, i.e. just avoids ripple in the output signal of the switching power supply; similarly, when the switch K2 is closed, the corresponding second low dropout linear regulator has an output, and at this time, the second low dropout linear regulator exactly corresponds to the stationary voltage part in Vin2, so as to avoid the ripple of the output signal of the switching power supply.
It should be noted that this scheme is one of the preferred embodiments, and is not a limitation of the signal delay of the present application. In the application, as long as the delay of the signal, the ripple wave of the input signal can be avoided when the low dropout linear voltage regulator outputs, which is within the protection scope of the invention.
In addition, the noise reduction circuit of the low dropout linear voltage regulator is provided with a voltage division sampling circuit at the output end thereof, the feedback voltage is input to the positive input end of the amplifier in each low dropout linear voltage regulator,
furthermore, the output end of the amplifier is connected with the grid electrode of the PMOS tube, meanwhile, the source electrode of the PMOS tube is connected with the output end of the corresponding switching power supply, and the drain electrode of the PMOS tube is connected in parallel and then used as the output end of the noise reduction circuit; and the drain electrode of the PMOS tube is connected to the grid electrode of the same PMOS tube through a capacitor and a resistor in sequence.
Example III
The core of the invention is a noise reduction method of a low dropout linear regulator, wherein the specific noise reduction method in the embodiment comprises the following steps,
the output ends of a plurality of low-dropout linear voltage regulators are connected in parallel; the input end of each low-dropout linear voltage regulator shares the same power supply and the same total clock signal;
adjusting the delay time of the corresponding total clock signal and controlling the output signal of the power supply;
and controlling the low dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the power supply output signal.
According to the invention, the plurality of low-dropout linear voltage regulators are controlled to alternately work so as to avoid ripples in an input signal, so that a relatively stable output signal is obtained, and finally the noise reduction effect is achieved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A noise reduction circuit of a low dropout linear voltage regulator is characterized by comprising a plurality of switching power supplies,
the input ends of the plurality of switching power supplies are connected with the same total power supply and the total clock signal, the output ends of the switching power supplies are respectively connected with a low-voltage-difference linear voltage stabilizer, and the output ends of the low-voltage-difference linear voltage stabilizers are connected in parallel and then output;
the switching power supply is internally provided with a delay unit which is used for adjusting the delay time corresponding to the total clock signal and controlling the output signal of the switching power supply;
the total clock signal is also connected with a low-dropout linear voltage regulator output control module which is used for controlling the low-dropout linear voltage regulator to alternately output and avoiding the ripple wave of the switching power supply output signal.
2. The noise reduction circuit of the low dropout linear regulator according to claim 1, wherein the output control module of the low dropout linear regulator is a sine wave generator, and an output end of the sine wave generator is connected with an inverting input end of an amplifier in the low dropout linear regulator, and is used for controlling the low dropout linear regulator to alternately output through an output signal of the sine wave generator.
3. The noise reduction circuit of claim 2, wherein the output signal of the sine wave generator is superimposed/subtracted with the reference voltage of the low dropout linear regulator and then input to the inverting input terminal of the amplifier.
4. The noise reduction circuit of the low dropout linear voltage regulator according to claim 1, wherein a switch is connected to the output end of each of the low dropout linear voltage regulators before the output ends are connected in parallel, and the alternating output of each of the low dropout linear voltage regulators is controlled by the on-off of the switch.
5. The noise reduction circuit of the low dropout linear regulator according to claim 4, wherein the output control module of the low dropout linear regulator is an inverter for controlling the switch after inverting the total clock signal; or (b)
And the output control module of the low dropout linear voltage regulator directly controls the switch by using the total clock signal.
6. The noise reduction circuit of claim 1, wherein the ripple in the output signal of the switching power supply is delayed by T/4n, where T is the period of the total clock signal and n is an integer greater than or equal to 1.
7. The noise reduction circuit of claim 1, wherein the voltage at the output terminal of the noise reduction circuit is fed back to the positive input terminal of each of the LDO's through a voltage division sampling circuit.
8. The noise reduction circuit of the low dropout linear regulator according to claim 1, wherein in the low dropout linear regulator, an output end of the amplifier is connected with a gate of the PMOS tube, a source of the PMOS tube is connected with an output end of a corresponding switching power supply, and a drain of the PMOS tube is connected in parallel and then used as an output end of the noise reduction circuit.
9. The noise reduction circuit of the low dropout linear regulator according to claim 8, wherein the drain electrodes of the PMOS transistors are connected to the gate electrodes of the same PMOS transistor sequentially through a capacitor and a resistor.
10. A noise reduction method for a low dropout linear regulator is characterized by comprising the steps of,
the output ends of a plurality of low-dropout linear voltage regulators are connected in parallel; the input end of each low-dropout linear voltage regulator shares the same power supply and the same total clock signal;
adjusting the delay time of the total clock signal and controlling the output signal of the power supply;
and controlling the low dropout linear voltage regulator to alternately output so as to avoid the ripple wave of the power supply output signal.
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