CN207408852U - The low pressure difference linear voltage regulator of high PSRR - Google Patents
The low pressure difference linear voltage regulator of high PSRR Download PDFInfo
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- CN207408852U CN207408852U CN201721413864.1U CN201721413864U CN207408852U CN 207408852 U CN207408852 U CN 207408852U CN 201721413864 U CN201721413864 U CN 201721413864U CN 207408852 U CN207408852 U CN 207408852U
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Abstract
The utility model provides a kind of low pressure difference linear voltage regulator of high PSRR, including：Partial pressure unit is for one voltage division signal of generation；Comparing unit, including two input terminals and an output terminal, one of input terminal couples partial pressure unit, for receiving voltage division signal, another input terminal is for receiving reference voltage signal, and output terminal is for output according to voltage division signal and the amplification voltage signal of reference voltage signal；Boosting unit couples the output terminal of comparing unit, for providing a switching signal；Switch unit, couple output terminal, partial pressure unit and the boosting unit of comparing unit, for responding to switch signal, it receives and according to amplification voltage signal output buck signal, switch unit includes the first NMOS tube, the output terminal of the grid coupling comparing unit of first NMOS tube, drain electrode coupling first voltage signal, source electrode coupling partial pressure unit.By boosting unit and the first NMOS tube, high PSRR can be provided, exports stable buck signal, reduces noise output.
Description
Technical field
The utility model is related to low pressure difference linear voltage regulator equipment technical field, more particularly to a kind of high PSRR
Low pressure difference linear voltage regulator.
Background technology
LDO, that is, low dropout regulator are a kind of low pressure difference linear voltage regulators.It is as shown in Figure 1, existing low
Pressure difference linear voltage regulator is generally made of PMOS switch pipe, divider resistance R1 and R2, comparison amplifier.Its principle is：Partial pressure electricity
One input terminal of pressure coupling comparison amplifier, with being added in compared with the reference voltage of another input terminal, the difference of the two is through comparing
After amplifier amplification, the pressure drop of PMOS switch pipe is controlled, so as to stabilize the output voltage.To promote properties of product, often lead to
It crosses on the direction for reducing output noise and studies, but the circuit is 10 in frequency7During HZ, the noise of output is anti-compared with the noise of input
And become much larger, reason mainly has three-line source：Circuit 1 is since there are coupled capacitor, VOUT is defeated inside PMOS tube
Going out is influenced by the coupled capacitor；Circuit 2 be the inside due to comparison amplifier there is also coupled capacitor, the voltage of VA is coupled by this
Capacitive effect can not follow VDD, cause the v of PMOSgs(VDD-VA) constantly shaken with VDD；Circuit 3 is that noise is influenced via VVD
VA, and influence VOUT.
Utility model content
The utility model provides a kind of low pressure difference linear voltage regulator of high PSRR, solves the problem above-mentioned.
To solve the above problems, the utility model embodiment provides a kind of low pressure difference linearity voltage stabilizing of high PSRR
Device, including partial pressure unit, comparing unit, boosting unit and switch unit；
Partial pressure unit, for generating a voltage division signal；
Comparing unit, including two input terminals and an output terminal, one of input terminal couples the partial pressure unit, uses
In receiving the voltage division signal, another input terminal is for receiving reference voltage signal, and output terminal is for output according to voltage division signal
With the amplification voltage signal of reference voltage signal；
Boosting unit couples the output terminal of the comparing unit, for providing a switching signal；
Switch unit couples output terminal, the partial pressure unit and the boosting unit of the comparing unit, for responding
Switching signal to be stated, is received and according to the amplification voltage signal output buck signal, the switch unit includes the first NMOS tube,
The grid of first NMOS tube couples the output terminal of the comparing unit, drain electrode coupling first voltage signal, described point of source electrode coupling
Press unit.
As a kind of embodiment, noise reduction unit is further included, the noise reduction unit includes the second NMOS tube, and described second
The grid of NMOS tube and drain electrode couple first voltage signal, and source electrode couples the drain electrode of the first NMOS.
As a kind of embodiment, the noise reduction unit further includes first resistor, first resistor one end coupling second
The grid of NMOS tube, other end coupling first voltage signal.
As a kind of embodiment, filter unit is further included, the filter unit includes first resistor and the second capacitance, institute
State the grid that first resistor one end couples the second NMOS tube, other end coupling first voltage signal, second capacitance coupling the
The connecting node of one resistance and the second NMOS tube.
As a kind of embodiment, first NMOS tube and the second NMOS tube use native NFET.
As a kind of embodiment, the boosting unit includes the first capacitance, and one end coupling of first capacitance is compared
The connecting node of unit and switch unit, other end ground connection.
The beneficial effects of the utility model compared with the prior art lie in：It, can be with by boosting unit and the first NMOS tube
High PSRR is provided, exports stable buck signal, reduces noise output, and the output signal of comparing unit is made to follow the
One voltage signal；By setting the second NMOS tube between the first NMOS tube and first voltage signal, first voltage signal can be avoided
The electric current of generation directly flows to source electrode from the drain electrode of the first NMOS tube.
Description of the drawings
Fig. 1 is the circuit diagram of low pressure difference linear voltage regulator of the prior art；
Fig. 2 is the circuit diagram of the low pressure difference linear voltage regulator of the high PSRR of the utility model.
Attached drawing marks：1st, partial pressure unit；2nd, comparing unit；3rd, boosting unit；4th, switch unit；5th, noise reduction unit.
Specific embodiment
Below in conjunction with attached drawing, technical characteristic above-mentioned to the utility model and other and advantage carry out clearly and completely
Description, it is clear that described embodiment is only the section Example rather than whole embodiments of the utility model.
As shown in Fig. 2, a kind of low pressure difference linear voltage regulator of high PSRR, including partial pressure unit 1, comparing unit 2,
Boosting unit 3 and switch unit 4；Partial pressure unit 1, for generating a voltage division signal；Comparing unit 2, including two input terminals
With an output terminal, one of input terminal couples partial pressure unit 1, and for receiving voltage division signal, another input terminal is used to receive
Reference voltage signal Vref, output terminal is for output according to voltage division signal and the amplification voltage signal of reference voltage signal；Boosting
Unit 3 couples the output terminal of comparing unit 2, for providing a switching signal；Switch unit 4 couples the defeated of comparing unit 2
Outlet, partial pressure unit 1 and boosting unit 3 for responding to switch signal, receive and according to amplification voltage signal output buck letter
Number VOUT, switch unit 4 include the first NMOS tube, the output terminal of the grid coupling comparing unit 2 of the first NMOS tube, drain electrode coupling
First voltage signal VDD, source electrode coupling partial pressure unit 1.
Boosting unit 3 includes the first capacitance, one end coupling comparing unit 2 of the first capacitance and the connection section of switch unit 4
Point, other end ground connection.Practical solution is in original circuit, increases a capacitance.In the present embodiment, the first capacitance is big for one
Capacity (i.e. existing capacitance adds the superposition of boosting unit 3) for providing a switching signal to the first NMOS tube, makes first
NMOS tube turns on.
In one embodiment, the electric current for first voltage signal is avoided to generate directly flows to source from the drain electrode of the first NMOS tube
Pole.The low pressure difference linear voltage regulator of the high PSRR of the utility model further includes noise reduction unit 5, and noise reduction unit 5 includes the
Two NMOS tubes, the grid of the second NMOS tube and drain electrode couple first voltage signal, and source electrode couples the drain electrode of the first NMOS.At this
In embodiment, the first NMOS tube and the second NMOS tube use native NFET.
In one embodiment, it is the bandwidth of the second NMOS tube of increase, the low voltage difference of the high PSRR of the utility model
The noise reduction unit 5 of linear voltage regulator further includes first resistor R1, and first resistor R1 one end couples the grid of the second NMOS tube, another
End coupling first voltage signal VDD.In the circuit formed in first resistor and the second NMOS tube, first resistor R1, which serves as one, to be had
The effect of source inductance, it is possible to increase by the bandwidth for the circuit that first resistor R1 and the second NMOS tube form, so as to increase low voltage difference line
The output of property voltage-stablizer.
In another embodiment, for the first NMOS tube is given to provide a stable operating point, in the input of the second NMOS tube
End sets filter unit, and filter unit includes first resistor R1 and the second capacitance C2, first resistor R1 one end couple the 2nd NMOS
The grid of pipe, the connection of other end coupling first voltage signal VDD, the second capacitance C2 coupling first resistor R1 and the second NMOS tube
Node.
The Current calculation formula of drain electrode when switching tube saturation is, wherein, be electronics migration rate, be unit area
Gate oxide capacitance is breadth length ratio, is overdrive voltage, is grid voltage and the output of the first NMOS tube in the present embodiment
The voltage difference of voltage (i.e. buck signal), therefore, comparison use the existing scheme of PMOS, which can more stablize, moreover,
Circuit that need not be very big supplements capacitance, significantly reduces chip area, reduces chip outward element quantity.So this practicality
New low pressure difference linear voltage regulator can provide high PSRR, export stable buck signal, reduce noise output, and
The output signal of comparing unit 2 is made to follow first voltage signal.
The utility model can provide high PSRR, export smoothly drop by 3 and first NMOS tube of boosting unit
Signal is pressed, reduces noise output, and the output signal of comparing unit 2 is made to follow first voltage signal；By the first NMOS tube and
Second NMOS tube between first voltage signal is set, the electric current that first voltage signal generates can be avoided directly from the first NMOS tube
Drain electrode flows to source electrode.
Particular embodiments described above has carried out into one the purpose of this utility model, technical solution and advantageous effect
The detailed description of step, it should be understood that the foregoing is merely specific embodiment of the utility model, are not used to limit this reality
With new protection domain.Particularly point out, to those skilled in the art, it is all the spirit and principles of the utility model it
Any modification, equivalent substitution, improvement and etc. that are interior, being done, should be included within the scope of protection of this utility model.
Claims (6)
1. a kind of low pressure difference linear voltage regulator of high PSRR, which is characterized in that including partial pressure unit, comparing unit, liter
Press unit and switch unit；
Partial pressure unit, for generating a voltage division signal；
Comparing unit, including two input terminals and an output terminal, one of input terminal couples the partial pressure unit, for connecing
The voltage division signal is received, another input terminal is for receiving reference voltage signal, and output terminal is for output according to voltage division signal and base
The amplification voltage signal of quasi- voltage signal；
Boosting unit couples the output terminal of the comparing unit, for providing a switching signal；
Switch unit couples output terminal, the partial pressure unit and the boosting unit of the comparing unit, for responding described open
OFF signal, receive and according to it is described amplification voltage signal output buck signal, the switch unit include the first NMOS tube, first
The grid of NMOS tube couples the output terminal of the comparing unit, and drain electrode coupling first voltage signal, it is single that source electrode couples the partial pressure
Member.
2. the low pressure difference linear voltage regulator of high PSRR according to claim 1, which is characterized in that further include noise reduction
Unit, the noise reduction unit include the second NMOS tube, and the grid of second NMOS tube and drain electrode couple first voltage signal,
Source electrode couples the drain electrode of the first NMOS.
3. the low pressure difference linear voltage regulator of high PSRR according to claim 2, which is characterized in that the noise reduction list
Member further includes first resistor, and described first resistor one end couples the grid of the second NMOS tube, other end coupling first voltage signal.
4. the low pressure difference linear voltage regulator of high PSRR according to claim 2, which is characterized in that further include filtering
Unit, the filter unit include first resistor and the second capacitance, and described first resistor one end couples the grid of the second NMOS tube,
The other end couples the connecting node of first voltage signal, the second capacitance coupling first resistor and the second NMOS tube.
5. the low pressure difference linear voltage regulator of high PSRR according to claim 1, which is characterized in that described first
NMOS tube and the second NMOS tube use native NFET.
6. the low pressure difference linear voltage regulator of high PSRR according to claim 1, which is characterized in that the boosting is single
Member includes the first capacitance, one end coupling comparing unit of first capacitance and the connecting node of switch unit, other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721413864.1U CN207408852U (en) | 2017-10-30 | 2017-10-30 | The low pressure difference linear voltage regulator of high PSRR |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721413864.1U CN207408852U (en) | 2017-10-30 | 2017-10-30 | The low pressure difference linear voltage regulator of high PSRR |
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| CN207408852U true CN207408852U (en) | 2018-05-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107632658A (en) * | 2017-10-30 | 2018-01-26 | 杭州洪芯微电子科技有限公司 | The low pressure difference linear voltage regulator of high PSRR |
| CN108874010A (en) * | 2018-09-06 | 2018-11-23 | 深圳市中微半导体有限公司 | A kind of strong anti-interference LDO module and anti-interference touch detection circuit |
| CN113064460A (en) * | 2021-03-24 | 2021-07-02 | 成都瓴科微电子有限责任公司 | Low dropout regulator circuit with high power supply rejection ratio |
-
2017
- 2017-10-30 CN CN201721413864.1U patent/CN207408852U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107632658A (en) * | 2017-10-30 | 2018-01-26 | 杭州洪芯微电子科技有限公司 | The low pressure difference linear voltage regulator of high PSRR |
| CN108874010A (en) * | 2018-09-06 | 2018-11-23 | 深圳市中微半导体有限公司 | A kind of strong anti-interference LDO module and anti-interference touch detection circuit |
| CN113064460A (en) * | 2021-03-24 | 2021-07-02 | 成都瓴科微电子有限责任公司 | Low dropout regulator circuit with high power supply rejection ratio |
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