CN203311292U - Multi-output reference voltage source - Google Patents
Multi-output reference voltage source Download PDFInfo
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- CN203311292U CN203311292U CN2013203187716U CN201320318771U CN203311292U CN 203311292 U CN203311292 U CN 203311292U CN 2013203187716 U CN2013203187716 U CN 2013203187716U CN 201320318771 U CN201320318771 U CN 201320318771U CN 203311292 U CN203311292 U CN 203311292U
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- pmos pipe
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Abstract
The utility model provides a multi-output reference voltage source which can realize a voltage with a negative temperature coefficient without an operational amplifier so as to save the layout area of a circuit, to reduce the complexity and difficulty of the design, and to avoid the influence of the offset voltage of the operational amplifier on the precision of an output voltage. In addition, the voltage source comprises a first lengthwise NPN triode and a second lengthwise NPN triode, wherein the current amplification factors of the lengthwise NPN triodes are very large, so that the precision of an output band-gap reference voltage is further improved. Meanwhile, the multi-output reference voltage source provided by the utility model not only can provide a band-gap reference voltage which is lower than an output voltage of the existing band-gap reference voltage source, but also can obtain a plurality of lower-voltage benchmarks with other lower values through a plurality of output ports of a lower-voltage output stage circuit.
Description
Technical field
The utility model relates to technical field of integrated circuits, more particularly, relates to a kind of many output reference voltages source.
Background technology
Stable bandgap voltage reference is the significant element in precision comparator, power supply, digital to analog converter, analog to digital converter, low pressure difference linear voltage regulator.The output voltage of bandgap voltage reference keeps stablizing constant characteristic when temperature and mains voltage variations, the performance of whole Circuits System is played to vital effect, so bandgap voltage reference is the important module unit in integrated circuit.
Along with the progress with design of electronic products that reduces of integrated circuit technology size, integrated circuit is towards the low-voltage and low-power dissipation future development, and namely the operating voltage of chip is low, and power consumption is also low simultaneously.When the operating voltage of chip reduced, the operating voltage of the composition module of its inside reduced equally, and bandgap voltage reference, as the output module of voltage reference, requires its output voltage correspondingly to reduce.
Negative temperature coefficient voltage in bandgap voltage reference is poor from the emitter voltage of two triodes, namely the base voltage of two triodes equates, and the emitter of these two triodes links together by resistance, the voltage difference of the emitter of two triodes puts on this resistance so, and the voltage of this resistance is negative temperature coefficient voltage.In existing bandgap voltage reference, adopt anode and the negative terminal of the base stage difference concatenation operation amplifier of two PNP triodes, the emitter of two PNP triodes links together by resistance, the void of operational amplifier is short has guaranteed that the base voltage of two PNP triodes equates, the voltage difference of the emitter of two PNP triodes puts on resistance, thereby obtains negative temperature coefficient voltage.But existing bandgap voltage reference adopts operational amplifier, make the bandgap voltage reference design complicated, power consumption is larger, can take larger chip area simultaneously, is unfavorable for improving the integrated level of integrated circuit and reducing production costs; And the open-loop gain of operational amplifier, PSRR(Power Supply Rejection Ratio, Power Supply Rejection Ratio) all can affect the precision and stability of bandgap voltage reference.
The utility model content
In view of this, the utility model provides a kind of many output reference voltages source not only not need to adopt operational amplifier, and simplicity of design, take chip area little; And can also export bandgap voltage reference, also comprise simultaneously a plurality of lower low pressure benchmark of a plurality of output port output.
For achieving the above object, the utility model provides following technical scheme:
A kind of many output reference voltages source, comprise start-up circuit and the biasing circuit be connected with described start-up circuit output, also comprise: the band-gap reference that is connected with described biasing circuit output produces circuit and is connected with the bandgap voltage reference output terminal that described band-gap reference produces circuit, and the low pressure output-stage circuit with a plurality of output ports be comprised of a plurality of metal-oxide-semiconductors; Described band-gap reference produces circuit and comprises the first current source, the second current source, the first horizontal NPN triode, the second horizontal NPN triode, first vertical NPN triode, second vertical NPN triode, the first resistance and the second resistance, wherein, described the first current source size of current provided and size of current ratio that described the second current source provides is 1:2;
The input end of described the first current source all is connected supply voltage with the input end of described the second current source, the output terminal of described the first current source connects the collector of the described first horizontal NPN triode, and the output terminal of described the second current source connects the collector of the described second horizontal NPN triode;
The collector of described first vertical NPN triode connects described supply voltage, the emitter of described first vertical NPN triode and the emitter of the described first horizontal NPN triode all are connected an end of described the first resistance, the emitter of the described second horizontal NPN triode all is connected the other end of described the first resistance and an end of described the second resistance with the emitter of described second vertical NPN triode, and described the second resistance connects earth terminal;
The base stage of the base stage of the base stage of described first vertical NPN triode, the described first horizontal NPN triode and the described second horizontal NPN triode all is connected with the base stage of described second vertical NPN triode, the collector of described second vertical NPN triode connects described supply voltage, and the base stage of described second vertical NPN triode is as described bandgap voltage reference output terminal.
Preferably, described the first current source comprises a PMOS pipe and the 4th PMOS pipe; Described the second current source comprises the 2nd PMOS pipe, the 3rd PMOS pipe and the 5th PMOS pipe;
Wherein, the source electrode of a described PMOS pipe connects described supply voltage as the input end of described the first current source, the grid of a described PMOS pipe connects the first output terminal of described biasing circuit, the grid and the grid that is connected described the 3rd PMOS pipe of described the 2nd PMOS pipe of connection, and the drain electrode of a described PMOS pipe connects the source electrode of described the 4th PMOS pipe;
The input end that the source electrode of the source electrode of described the 2nd PMOS pipe and described the 3rd PMOS pipe is connected as described the second current source is connected described supply voltage, and the drain electrode of described the 2nd PMOS pipe and the drain electrode of described the 3rd PMOS pipe all are connected the source electrode of described the 5th PMOS pipe;
The grid of described the 4th POMS pipe and the grid of described the 5th PMOS pipe all are connected the second output terminal of described biasing circuit, and the drain electrode of described the 4th PMOS pipe connects the collector of the described first horizontal NPN triode as the output terminal of described the first current source;
The drain electrode of described the 5th PMOS pipe connects the collector of the described second horizontal NPN triode as the output terminal of described the second current source.
Preferably, described low pressure output-stage circuit comprises: the 6th PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe, and wherein, described the 2nd NMOS pipe, described the 3rd NMOS pipe and described the 4th NMOS pipe are operated in the subthreshold value zone;
The grid of described the 6th PMOS pipe connects the grid of described the 3rd PMOS pipe, and the source electrode of described the 6th PMOS pipe connects described supply voltage, and the drain electrode of described the 6th PMOS pipe connects grid and the drain electrode of a described NMOS pipe;
The grid of a described NMOS pipe all is connected described bandgap voltage reference output terminal with drain electrode, the source electrode of a described NMOS pipe connects drain electrode and the grid of described the 2nd NMOS pipe, the drain electrode of described the 2nd NMOS pipe is connected with grid, and the source electrode of described the 2nd NMOS pipe connects drain electrode and the grid of described the 3rd NMOS pipe;
The drain electrode of described the 3rd NMOS pipe is connected with grid, and the source electrode of described the 3rd NMOS pipe connects drain electrode and the grid of described the 4th NMOS pipe;
The drain electrode of described the 4th NMOS pipe is connected with grid, the source electrode of described the 4th NMOS pipe connects described earth terminal, the drain electrode of wherein, the drain electrode of described the 2nd NMOS pipe, described the 3rd NMOS pipe and the drain electrode of described the 4th NMOS pipe are respectively as the first output terminal, the second output terminal and the 3rd output terminal of described low pressure output-stage circuit.
Preferably, described start-up circuit comprises: the 7th PMOS pipe, the 8th PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe, and wherein, described the 7th NMOS pipe is the NMOS of falling breadth length ratio pipe;
The source electrode of described the 7th PMOS pipe connects described supply voltage, and the grid of described the 7th PMOS pipe all is connected the source electrode of described the 8th PMOS pipe with draining;
The drain electrode link grid of described the 8th PMOS pipe, the grid of described the 8th PMOS pipe connect grid and described the 5th NMOS pipe drain electrode of the grid of described the 6th NMOS pipe, described the 7th NMOS pipe simultaneously;
The source electrode of described the 5th NMOS pipe connects described earth terminal, and the grid of described the 5th NMOS pipe connects the 3rd input end of described biasing circuit;
The source electrode of described the 6th NMOS pipe connects described earth terminal, and the drain electrode of described the 6th NMOS pipe connects the first input end of described biasing circuit;
The source electrode of described the 7th NMOS pipe connects described earth terminal, and the drain electrode of described the 7th NMOS pipe connects the second input end of described biasing circuit.
Preferably, described biasing circuit comprises: the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe, the 8th NMOS pipe, the 9th NMOS pipe and the 3rd resistance;
Wherein, the source electrode of described the 9th PMOS pipe connects described supply voltage, the grid of described the 9th PMOS pipe connects the drain electrode of described the 6th NMOS pipe and grid and the drain electrode of described the tenth PMOS pipe as the first input end of described biasing circuit, and the drain electrode of described the 9th PMOS pipe connects the source electrode of described the 11 PMOS pipe;
The source electrode of described the tenth PMOS pipe connects described supply voltage, the grid of described the tenth PMOS pipe all is connected the source electrode of described the 12 PMOS pipe with drain electrode, and the grid of described the tenth PMOS pipe connects the grid of a described PMOS pipe as the first output terminal of described biasing circuit;
The drain electrode of described the 11 PMOS pipe is connected the grid of described the 5th NMOS pipe and an end of described the 3rd resistance with connected the 3rd input end as described biasing circuit of the grid of described the 8th NMOS pipe, the grid of described the 11 PMOS pipe is connected and as the second input end of described biasing circuit, is connected the drain electrode of described the 7th NMOS pipe with drain electrode with the grid of described the 12 PMOS pipe, and the grid of described the 11 PMOS pipe is connected the grid of described the 4th PMOS pipe and the grid of described the 5th PMOS pipe with the grid of described the 12 PMOS pipe with connected the second output terminal as described biasing circuit of drain electrode,
The drain electrode of described the 8th NMOS pipe connects the other end of described the 3rd resistance and the grid of described the 9th NMOS pipe, and the source electrode of described the 8th NMOS pipe connects described earth terminal;
The source electrode of described the 9th NMOS pipe connects described earth terminal.
Compared with prior art, technical scheme provided by the utility model has the following advantages:
Many output reference voltages provided by the utility model source, at band-gap reference, produce in circuit, directly the base stage of the first horizontal NPN triode is connected with the base stage of the second horizontal NPN triode, the emitter of the first horizontal NPN triode is connected by the first resistance with the emitter of the second horizontal NPN triode, wherein, the base voltage of two horizontal NPN triodes equates, the voltage difference of the emitter of the emitter of the first horizontal NPN triode and the second horizontal NPN triode is applied on the first resistance, obtains negative temperature coefficient voltage.Therefore many output reference voltages source of providing of the utility model does not need to adopt operational amplifier, has saved chip area, has reduced complexity and the design difficulty of design, has avoided computing to put the impact of the offset voltage of amplifier on the precision of output voltage.And the utility model comprises first vertical NPN triode and second vertical NPN triode, and vertically the current amplification factor of NPN triode is very large, has further improved the precision of the bandgap voltage reference of output.
Simultaneously, many output reference voltages provided by the utility model source not only can provide the bandgap voltage reference lower than the output voltage of existing bandgap voltage reference, but also can obtain by a plurality of output ports of low pressure output-stage circuit the low pressure benchmark of a plurality of lower other numerical value.
The accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of many output reference voltages source circuit structure schematic diagram that Fig. 1 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making under the creative work prerequisite the every other embodiment obtained, and all belong to the scope of the utility model protection.
It should be noted that; the utility model is described in detail in conjunction with schematic diagram; when the utility model embodiment is described in detail in detail; for ease of explanation; the accompanying drawing of indication device structure can be disobeyed general ratio and be done local the amplification; and described schematic diagram is example, it should not limit the scope of the utility model protection at this.The three-dimensional space that should comprise in addition, length, width and height in actual fabrication.
As described in background, existing bandgap voltage reference adopts operational amplifier, makes design complicated, and power consumption is larger, can take larger chip area simultaneously, is unfavorable for improving the integrated level of integrated circuit and reducing production costs; And the open-loop gain of operational amplifier, PARR(Power Supply Rejection Ratio, Power Supply Rejection Ratio) all can affect precision and the stability of bandgap voltage reference.
Based on this, the present embodiment provides a kind of many output reference voltages source, the problems referred to above that exist to overcome prior art, as shown in Figure 1, a kind of many output reference voltages source provided for the present embodiment, comprise start-up circuit 100, and the biasing circuit 200 be connected with described start-up circuit 100 outputs, also comprise: the band-gap reference be connected with described biasing circuit 200 outputs produces circuit 300, and be connected with the bandgap voltage reference output terminal Vref of described band-gap reference generation circuit, and the low pressure output-stage circuit 400 with a plurality of output ports formed by a plurality of metal-oxide-semiconductors, described band-gap reference produces circuit 300 and comprises the first current source 301, second current source the 302, first horizontal NPN triode Q1, the second horizontal NPN triode Q2, first vertical NPN triode Q3, second vertical NPN triode Q4, the first resistance R 1 and the second resistance R 2, wherein, described the first current source 301 size of current provided and size of current ratio that described the second current source 302 provides is 1:2,
The input end of described the first current source 301 all is connected power source voltage Vcc with the input end of described the second current source 302, the output terminal of described the first current source 301 connects the collector of the described first horizontal NPN triode Q1, and the output terminal of described the second current source 302 connects the collector of the described second horizontal NPN triode Q2;
The collector of described first vertical NPN triode Q3 connects described power source voltage Vcc, the emitter of described first vertical NPN triode Q3 and the emitter of the described first horizontal NPN triode Q1 all are connected an end of described the first resistance R 1, the emitter of the described second horizontal NPN triode Q2 all is connected the other end of described the first resistance R 1 and an end of described the second resistance R 2 with the emitter of described second vertical NPN triode Q4, and described the second resistance R 2 connects earth terminal;
The base stage of the base stage of the base stage of described first vertical NPN triode Q3, the described first horizontal NPN triode Q1 and the described second horizontal NPN triode Q2 all is connected with the base stage of described second vertical NPN triode Q4, and the collector of described second vertical NPN triode Q4 connects described supply voltage V
CC, the base stage of described second vertical NPN triode Q4 is as described bandgap voltage reference output terminal V
ref.
The present embodiment is preferred, and above-mentioned the first current source 301 comprises a PMOS pipe MP1 and the 4th PMOS pipe MP4; Above-mentioned the second current source 302 comprises the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3 and the 5th PMOS pipe MP5, and wherein, the substrate of PMOS pipe connects high level, and the substrate of NMOS pipe connects low level;
Wherein, the source electrode of a described PMOS pipe MP1 connects described power source voltage Vcc as the input end of described the first current source 301, described the 2nd PMOS of the first output terminal, connection that the grid MP1 of a described PMOS pipe connects described biasing circuit 200 manages the grid of MP2 and is connected the grid that described the 3rd PMOS manages MP3, and the drain electrode of a described PMOS pipe MP1 connects the source electrode that described the 4th PMOS manages MP4;
The source electrode that described the 2nd PMOS manages MP2 is connected described power source voltage Vcc with the connected input end as described the second current source 302 of source electrode of described the 3rd PMOS pipe MP3, and the drain electrode of described the 2nd PMOS pipe MP2 all is connected with the drain electrode of described the 3rd PMOS pipe MP3 the source electrode that described the 5th PMOS manages MP5;
The grid of described the 4th POMS pipe MP4 and the grid of described the 5th PMOS pipe MP5 all are connected the second output terminal of described biasing circuit 200, and the drain electrode of described the 4th PMOS pipe MP4 is as the collector of the output terminal connection described first horizontal NPN triode Q1 of described the first current source 301;
The drain electrode of described the 5th PMOS pipe MP5 connects the collector of the described second horizontal NPN triode Q2 as the output terminal of described the second current source 302.
Above-mentioned band-gap reference generation circuit: Q1, the Q2 that for the present embodiment, provide are horizontal triodes, and Q3, Q4 are vertical triodes.Wherein, because the first current source size of current provided and the size of current ratio that described the second current source provides are 1:2, so the collector current of Q2 is the twice of the collector current of Q1, the emitter current of same Q2 is the twice I of the emitter current of Q1
Q2=2I
Q1.
And Q3 parasitizes Q1, namely Q3 copies the electric current of Q1; Q4 parasitizes Q2, and namely Q4 copies the electric current of Q2, so the emitter current I of Q1
Q1Emitter current I with Q3
Q3Identical, the emitter current I of Q2
Q2Emitter current I with Q4
Q4Identical, further obtain: I
Q2=I
Q4=2I
Q1=2I
Q3.
Therefore, the voltage V of R1
R1Computing formula be:
V
R1=V
BE2-V
BE1=V
TLn(2I
0/ I
S)-V
TLn(I
0/ I
S)=V
TLn2 (formula 1)
Wherein, V
BE2For the base-emitter voltage drop of Q2, V
BE1For the base-emitter voltage drop of Q1, V
TFor thermal voltage, I
0For flowing through transistorized electric current, I
SFor transistorized saturation current.
Flow through the electric current I of the second resistance R 2
R2For flowing through the electric current I of the first resistance R 1
R1(I
R1=I
Q1+ I
Q3) with the emitter current I of Q2
Q2Emitter current I with Q4
Q4Sum, flow through the electric current I of the second resistance R 2
R2Computing formula be:
I
R2=I
R1+ I
Q2+ I
Q4=3I
R1=3V
TLn2/R1 (formula 2)
Output node using the base stage of Q4 as bandgap voltage reference, output voltage V
refComputing formula be:
V
ref=V
BE4+ I
R2R2=V
BE4+ 3R2V
TLn2/R1 (formula 3)
Wherein, V
BE4For the base stage of Q4 and the voltage difference between emitter.
Therefore, the band-gap reference in many output reference voltages source that the present embodiment provides produces circuit, only needs to regulate R1, R2 and can obtain stable output voltage.Simultaneously, the bandgap voltage reference of many output reference voltages provided by the utility model source output is lower than the voltage of existing bandgap voltage reference output, and the bandgap voltage reference simulation result of many output reference voltages provided by the utility model source output is about 1.16V.
Above-mentioned band-gap reference produces circuit, directly the base stage of the first horizontal NPN triode is connected with the base stage of the second horizontal NPN triode, the emitter of the first horizontal NPN triode is connected by the first resistance with the emitter of the second horizontal NPN triode, wherein, the base voltage of two horizontal NPN triodes equates, the voltage difference of the emitter of the emitter of the first horizontal NPN triode and the second horizontal NPN triode is applied on the first resistance, obtains negative temperature coefficient voltage.Therefore many output reference voltages source of providing of the utility model does not need to adopt operational amplifier, has saved chip area, has reduced complexity and the design difficulty of design, has avoided computing to put the impact of the offset voltage of amplifier on the precision of output voltage.And the utility model comprises first vertical NPN triode and second vertical NPN triode, and vertically the current amplification factor of NPN triode is very large, has further improved the precision of the bandgap voltage reference of output.
Simultaneously, many output reference voltages provided by the utility model source not only can provide the bandgap voltage reference lower than the output voltage of existing bandgap voltage reference, but also can obtain by a plurality of output ports of low pressure output-stage circuit the low pressure benchmark of a plurality of lower other numerical value.
The low pressure output-stage circuit 400 that the present embodiment provides comprises: the 6th PMOS pipe MP6, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the 4th NMOS pipe MN4, wherein, described the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3 and the 4th NMOS pipe MN4 are operated in the subthreshold value zone;
The grid of described the 6th PMOS pipe MP6 connects the grid of described the 3rd PMOS pipe MP3, and then provide running parameter by biasing circuit 200, the source electrode of described the 6th PMOS pipe MP6 connects described power source voltage Vcc, and the drain electrode of described the 6th PMOS pipe MP6 connects grid and the drain electrode of a described NMOS pipe MN1;
The grid of a described NMOS pipe MN1 all is connected described bandgap voltage reference output terminal with drain electrode, the source electrode of a described NMOS pipe MN1 connects drain electrode and the grid of described the 2nd NMOS pipe MN2, the drain electrode of described the 2nd NMOS pipe MN2 is connected with grid, and the source electrode of described the 2nd NMOS pipe MN2 connects drain electrode and the grid of described the 3rd NMOS pipe MN3;
The drain electrode of described the 3rd NMOS pipe MN3 is connected with grid, and the source electrode of described the 3rd NMOS pipe MN3 connects drain electrode and the grid of described the 4th NMOS pipe MN4;
The drain electrode of described the 4th NMOS pipe MN4 is connected with grid, the source electrode of described the 4th NMOS pipe MN4 connects described earth terminal, the drain electrode of wherein, the drain electrode of described the 2nd NMOS pipe, described the 3rd NMOS pipe and the drain electrode of described the 4th NMOS pipe are respectively as the first output terminal, the second output terminal and the 3rd output terminal of described low pressure output-stage circuit.
The low pressure output-stage circuit 400 provided for the present embodiment: wherein, NMOS pipe MN2, MN3, MN4 form the low pressure output stage, by regulating breadth length ratio, make three NMOS pipes be operated in the subthreshold value zone, thereby Q4 base stage output voltage is carried out to dividing potential drop, finally export the low pressure benchmark.By selecting different nodes as output terminal, or the breadth length ratio of regulating MN2, MN3, MN4, just can obtain the low pressure benchmark of different numerical value.The drain electrode of for example choosing MN4 in Fig. 1, as output terminal, can obtain the low pressure benchmark of 160mV.The metal-oxide-semiconductor that the low pressure output-stage circuit utilization that the present embodiment provides is operated in the subthreshold value zone carries out dividing potential drop, simple in structure, and low in energy consumption, precision is high, takies chip area little.
Preferably, the start-up circuit in above-described embodiment 100 can or be filled with the current type start-up circuit for the drawing and pressing type start-up circuit.
Concrete, the start-up circuit 100 that the present embodiment provides is the drawing and pressing type start-up circuit, comprise: the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7, wherein, described the 7th NMOS pipe MN7 is the NMOS of falling breadth length ratio pipe;
The source electrode of described the 7th PMOS pipe MP7 connects described power source voltage Vcc, and the grid of described the 7th PMOS pipe MP7 all is connected with drain electrode the source electrode that described the 8th PMOS manages MP8;
The drain electrode of described the 8th PMOS pipe MP8 connects grid, and the grid of described the 8th PMOS pipe MP8 connects grid and described the 5th NMOS pipe MN5 drain electrode of the grid of described the 6th NMOS pipe MN6, described the 7th NMOS pipe MN7 simultaneously;
The source electrode of described the 5th NMOS pipe MN5 connects described earth terminal, and the grid of described the 5th NMOS pipe MN5 connects the 3rd input end of described biasing circuit 200;
The source electrode of described the 6th NMOS pipe MN6 connects described earth terminal, and the drain electrode of described the 6th NMOS pipe MN6 connects the first input end of described biasing circuit 200;
The source electrode of described the 7th NMOS pipe MN7 connects described earth terminal, and the drain electrode of described the 7th NMOS pipe MN7 connects the second input end of described biasing circuit 200.
Wherein above-mentioned drawing and pressing type start-up circuit principle of work is: in many output reference voltages source, power on wink namely, the MP7 that the diode mode connects, MP8 conducting, supply voltage V
CCBe sent to the grid of MN7, the grid potential of MN7 raises gradually, finally makes the MN7 conducting, and then the grid of MP9, MP10, MP11, MP12 obtains operating voltage, and whole many output reference voltages source circuit is opened.After the working stability of many output reference voltages source, the MN5 conducting, because MN7 is the device of falling the breadth length ratio, the conducting resistance of MN7 is very large, makes the grid voltage of MN7 very little, and final MN7 closes, start-up circuit breaks away from many output reference voltages source, and many output reference voltages source remains on normal working point.
The preferred described biasing circuit 200 of the present embodiment comprises: the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9 and the 3rd resistance R 3; This biasing circuit 200 is the bootstrapping biasing circuit with supply independent.
Wherein, the source electrode of described the 9th PMOS pipe MP9 connects described power source voltage Vcc, the grid of described the 9th PMOS pipe MP9 connects the drain electrode of described the 6th NMOS pipe MN6 and grid and the drain electrode of described the tenth PMOS pipe MP10 as the first input end of described biasing circuit 200, and the drain electrode of described the 9th PMOS pipe MP9 connects the source electrode of described the 11 PMOS pipe MP11;
The grid of described the tenth PMOS pipe MP10 connects described power source voltage Vcc, the grid of described the tenth PMOS pipe MP10 all is connected with drain electrode the source electrode that described the 12 PMOS manages MP12, and the grid of described the tenth PMOS pipe MP10 connects the grid of a described PMOS pipe MP1 as the first output terminal of described biasing circuit 200;
The drain electrode of described the 11 PMOS pipe MP11 is connected the grid of described the 5th NMOS pipe MN5 and an end of described the 3rd resistance R 3 with connected the 3rd input end as described biasing circuit 200 of grid of described the 8th NMOS pipe MN8, the grid of described the 11 PMOS pipe MP11 is connected with drain electrode and as the second input end of described biasing circuit 200, is connected the drain electrode of described the 7th NMOS pipe MN7 with the grid of described the 12 PMOS pipe MP12, and the grid of described the 11 PMOS pipe MP11 is connected the grid of described the 4th PMOS pipe MP4 and the grid of described the 5th PMOS pipe MP5 with the grid of described the 12 PMOS pipe MP12 with connected the second output terminal as described biasing circuit 200 of drain electrode,
The drain electrode of described the 8th NMOS pipe MN8 connects the other end of described the 3rd resistance R 3 and the grid of described the 9th NMOS pipe MN9, and the source electrode of described the 8th NMOS pipe MN8 connects described earth terminal;
The source electrode of described the 9th NMOS pipe MN9 connects described earth terminal.
For above-mentioned and bootstrapping biasing circuit supply independent, for producing circuit, band-gap reference provides applicable running parameter.The breadth length ratio of MN9 be MN8 breadth length ratio m doubly, make the electric current of MN8, MN9 be respectively I
8, I
9, ignore the channel modulation effect, the electric current I of MN8
8Electric current I with MN9
9The computing formula that concerns be:
Wherein, β=μ
nC
Ox(W/L)/2, μ
nFor electron transfer rate, C
OxFor unit area gate oxide electric capacity, W/L is breadth length ratio, V
On8For the MN8 grid-source voltage.
Order
Obtain the value of R3:
Make I
8=I
9, obtain the value of m.
Therefore, as shown from the above formula, by regulating the breadth length ratio of MN8 and MN9, just can realize the accurate proportioning of current mirror, thereby improve the circuit power rejection ratio.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the utility model.Multiple modification to these embodiment will be apparent for those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from spirit or scope of the present utility model, realization in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (5)
1. output reference voltage source more than a kind, comprise start-up circuit and the biasing circuit be connected with described start-up circuit output, it is characterized in that, also comprise: the band-gap reference that is connected with described biasing circuit output produces circuit and is connected with the bandgap voltage reference output terminal that described band-gap reference produces circuit, and the low pressure output-stage circuit with a plurality of output ports be comprised of a plurality of metal-oxide-semiconductors; Described band-gap reference produces circuit and comprises the first current source, the second current source, the first horizontal NPN triode, the second horizontal NPN triode, first vertical NPN triode, second vertical NPN triode, the first resistance and the second resistance, wherein, described the first current source size of current provided and size of current ratio that described the second current source provides is 1:2;
The input end of described the first current source all is connected supply voltage with the input end of described the second current source, the output terminal of described the first current source connects the collector of the described first horizontal NPN triode, and the output terminal of described the second current source connects the collector of the described second horizontal NPN triode;
The collector of described first vertical NPN triode connects described supply voltage, the emitter of described first vertical NPN triode and the emitter of the described first horizontal NPN triode all are connected an end of described the first resistance, the emitter of the described second horizontal NPN triode all is connected the other end of described the first resistance and an end of described the second resistance with the emitter of described second vertical NPN triode, and described the second resistance connects earth terminal;
The base stage of the base stage of the base stage of described first vertical NPN triode, the described first horizontal NPN triode and the described second horizontal NPN triode all is connected with the base stage of described second vertical NPN triode, the collector of described second vertical NPN triode connects described supply voltage, and the base stage of described second vertical NPN triode is as described bandgap voltage reference output terminal.
2. many output reference voltages according to claim 1 source, is characterized in that, described the first current source comprises a PMOS pipe and the 4th PMOS pipe; Described the second current source comprises the 2nd PMOS pipe, the 3rd PMOS pipe and the 5th PMOS pipe;
Wherein, the source electrode of a described PMOS pipe connects described supply voltage as the input end of described the first current source, the grid of a described PMOS pipe connects the first output terminal of described biasing circuit, the grid and the grid that is connected described the 3rd PMOS pipe of described the 2nd PMOS pipe of connection, and the drain electrode of a described PMOS pipe connects the source electrode of described the 4th PMOS pipe;
The input end that the source electrode of the source electrode of described the 2nd PMOS pipe and described the 3rd PMOS pipe is connected as described the second current source is connected described supply voltage, and the drain electrode of described the 2nd PMOS pipe and the drain electrode of described the 3rd PMOS pipe all are connected the source electrode of described the 5th PMOS pipe;
The grid of described the 4th POMS pipe and the grid of described the 5th PMOS pipe all are connected the second output terminal of described biasing circuit, and the drain electrode of described the 4th PMOS pipe connects the collector of the described first horizontal NPN triode as the output terminal of described the first current source;
The drain electrode of described the 5th PMOS pipe connects the collector of the described second horizontal NPN triode as the output terminal of described the second current source.
3. many output reference voltages according to claim 2 source, it is characterized in that, described low pressure output-stage circuit comprises: the 6th PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe, wherein, described the 2nd NMOS pipe, described the 3rd NMOS pipe and described the 4th NMOS pipe are operated in the subthreshold value zone;
The grid of described the 6th PMOS pipe connects the grid of described the 3rd PMOS pipe, and the source electrode of described the 6th PMOS pipe connects described supply voltage, and the drain electrode of described the 6th PMOS pipe connects grid and the drain electrode of a described NMOS pipe;
The grid of a described NMOS pipe all is connected described bandgap voltage reference output terminal with drain electrode, the source electrode of a described NMOS pipe connects drain electrode and the grid of described the 2nd NMOS pipe, the drain electrode of described the 2nd NMOS pipe is connected with grid, and the source electrode of described the 2nd NMOS pipe connects drain electrode and the grid of described the 3rd NMOS pipe;
The drain electrode of described the 3rd NMOS pipe is connected with grid, and the source electrode of described the 3rd NMOS pipe connects drain electrode and the grid of described the 4th NMOS pipe;
The drain electrode of described the 4th NMOS pipe is connected with grid, the source electrode of described the 4th NMOS pipe connects described earth terminal, the drain electrode of wherein, the drain electrode of described the 2nd NMOS pipe, described the 3rd NMOS pipe and the drain electrode of described the 4th NMOS pipe are respectively as the first output terminal, the second output terminal and the 3rd output terminal of described low pressure output-stage circuit.
4. many output reference voltages according to claim 2 source, it is characterized in that, described start-up circuit comprises: the 7th PMOS pipe, the 8th PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe, and wherein, described the 7th NMOS pipe is the NMOS of falling breadth length ratio pipe;
The source electrode of described the 7th PMOS pipe connects described supply voltage, and the grid of described the 7th PMOS pipe all is connected the source electrode of described the 8th PMOS pipe with draining;
The drain electrode link grid of described the 8th PMOS pipe, the grid of described the 8th PMOS pipe connect grid and described the 5th NMOS pipe drain electrode of the grid of described the 6th NMOS pipe, described the 7th NMOS pipe simultaneously;
The source electrode of described the 5th NMOS pipe connects described earth terminal, and the grid of described the 5th NMOS pipe connects the 3rd input end of described biasing circuit;
The source electrode of described the 6th NMOS pipe connects described earth terminal, and the drain electrode of described the 6th NMOS pipe connects the first input end of described biasing circuit;
The source electrode of described the 7th NMOS pipe connects described earth terminal, and the drain electrode of described the 7th NMOS pipe connects the second input end of described biasing circuit.
5. many output reference voltages according to claim 4 source, is characterized in that, described biasing circuit comprises: the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe, the 8th NMOS pipe, the 9th NMOS pipe and the 3rd resistance;
Wherein, the source electrode of described the 9th PMOS pipe connects described supply voltage, the grid of described the 9th PMOS pipe connects the drain electrode of described the 6th NMOS pipe and grid and the drain electrode of described the tenth PMOS pipe as the first input end of described biasing circuit, and the drain electrode of described the 9th PMOS pipe connects the source electrode of described the 11 PMOS pipe;
The source electrode of described the tenth PMOS pipe connects described supply voltage, the grid of described the tenth PMOS pipe all is connected the source electrode of described the 12 PMOS pipe with drain electrode, and the grid of described the tenth PMOS pipe connects the grid of a described PMOS pipe as the first output terminal of described biasing circuit;
The drain electrode of described the 11 PMOS pipe is connected the grid of described the 5th NMOS pipe and an end of described the 3rd resistance with connected the 3rd input end as described biasing circuit of the grid of described the 8th NMOS pipe, the grid of described the 11 PMOS pipe is connected and as the second input end of described biasing circuit, is connected the drain electrode of described the 7th NMOS pipe with drain electrode with the grid of described the 12 PMOS pipe, and the grid of described the 11 PMOS pipe is connected the grid of described the 4th PMOS pipe and the grid of described the 5th PMOS pipe with the grid of described the 12 PMOS pipe with connected the second output terminal as described biasing circuit of drain electrode,
The drain electrode of described the 8th NMOS pipe connects the other end of described the 3rd resistance and the grid of described the 9th NMOS pipe, and the source electrode of described the 8th NMOS pipe connects described earth terminal;
The source electrode of described the 9th NMOS pipe connects described earth terminal.
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| CN2013203187716U CN203311292U (en) | 2013-06-04 | 2013-06-04 | Multi-output reference voltage source |
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| CN2013203187716U CN203311292U (en) | 2013-06-04 | 2013-06-04 | Multi-output reference voltage source |
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| CN104090626A (en) * | 2014-07-03 | 2014-10-08 | 电子科技大学 | High-precision multiple-output voltage buffer |
| CN105511540A (en) * | 2016-01-04 | 2016-04-20 | 东南大学 | Band-gap reference starting circuit with super-low leakage current |
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| CN107967022A (en) * | 2018-01-19 | 2018-04-27 | 桂林电子科技大学 | A kind of dual output Low Drift Temperature reference voltage source |
| CN107967022B (en) * | 2018-01-19 | 2023-11-03 | 桂林电子科技大学 | Dual-output low-temperature drift reference voltage source |
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| CN109347323B (en) * | 2018-11-28 | 2020-08-11 | 湖南国科微电子股份有限公司 | Power supply circuit, direct current power supply and electronic device |
| CN111722665A (en) * | 2020-06-10 | 2020-09-29 | 重庆邮电大学 | Unit current source circuit applied to high-speed high-precision current steering DAC |
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Address after: 215347 7th floor, IIR complex, 1699 Weicheng South Road, Kunshan City, Suzhou City, Jiangsu Province Patentee after: Kunshan Microelectronics Technology Research Institute Address before: Kunshan Industrial Research Institute, 1699 Weicheng South Road, Kunshan City, Suzhou City, Jiangsu Province Patentee before: KUNSHAN BRANCH, INSTITUTE OF MICROELECTRONICS OF CHINESE ACADEMY OF SCIENCES |
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Granted publication date: 20131127 |