CN102354245A - Band gap voltage reference source - Google Patents

Abstract

The invention discloses a band gap voltage reference source. The band gap voltage reference source comprises a biasing circuit, a start circuit and a first-order reference circuit, and is characterized by also comprising a temperature compensation circuit and an error amplifier circuit, wherein the temperature compensation circuit comprises an NPN transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a fifth resistor, a sixth resistor and a seventh resistor. In the band gap voltage reference source provided by the invention, temperature compensation is realized, namely a reference voltage is obtained by adding a collector current and the drain current of a metal oxide semiconductor (MOS) transistor in a sub-threshold region of a bipolar device into a conventional first-order temperature compensation band gap reference circuit, so that an output reference voltage has a smaller temperature coefficient.

Description

A kind of bandgap reference voltage source

Technical field

The invention belongs to electronic technology field, be specifically related to the design of a kind of voltage-reference (Voltage Reference).

Background technology

Voltage-reference is widely used in oscillator, phaselocked loop (PLL; Phase Locked Loop) and in various simulations such as data converter and the hybrid digital-analog integrated circuit; Its temperature coefficient (TC; Temperature Coefficient) and Power Supply Rejection Ratio (PSRR, Power Supply Rejection Ratio) determined the quality of system performance to a great extent.

Traditional based on V _BEWith thermal voltage V _TEach other the bandgap reference voltage source of compensation is used more extensively, as shown in Figure 1, because the clamping action of error amplifier, makes V _XWith V _Y2 voltage is equal basically, i.e. V _X=V _Y=V _BE2, simultaneously, the electric current in the circuit of both sides also equates, then has: $I_X=I_Y=\frac{V_{\mathrm{BE}2}-V_{\mathrm{BE}1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}=\frac{V_T\mathrm{<figure-callout\; id="1"\; label="ln\; N\; R"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">ln</figure-callout>}N}{R_{}}.$

Since

the current is proportional to absolute temperature (PTAT, Proporational? To? Absolute? Temperature) current, which is mirrored through the current mirror, then it became a bias current of the chip.

According to the expression formula of electric current, the expression formula that can draw band gap voltage is: $V_{\mathrm{BG}}=I_Y{R}_2=\frac{R_1}{R_1}{V}_T\ln N+V_{\mathrm{BE}2}.$

Because V _TBe positive temperature coefficient (PTC), simultaneously V _BE2Be negative temperature coefficient, reasonably adjustment factor

Size, can realize at a certain temperature that just benchmark is zero with variation of temperature, thereby vary with temperature very little reference voltage for entire chip provides one.

Yet because V _BENon-linear, only carry out first compensation phase, the temperature coefficient of voltage-reference is bigger.

Summary of the invention

The objective of the invention is to have proposed a kind of bandgap reference voltage source in order to solve the problem that existing first compensation phase bandgap reference voltage source exists.

Technical scheme of the present invention is: a kind of bandgap reference voltage source comprises: comprising: biasing circuit, start-up circuit and single order reference circuit; It is characterized in that; Also comprise; Temperature-compensation circuit and error amplifier circuit; Wherein, Described biasing circuit is that described bandgap reference voltage source provides bias voltage; Described start-up circuit is used to make single order reference circuit operate as normal; Said single order reference circuit produces the reference voltage of low-temperature coefficient; Described temperature-compensation circuit is used for the single order reference circuit is carried out temperature-compensating, and said error amplifier circuit is used for stablizing the operating point of single order reference circuit;

Said single order reference circuit comprises NPN pipe, the 2nd NPN pipe, PMOS pipe, the 2nd PMOS pipe, first resistance, second resistance, the 3rd resistance and the 4th resistance;

Described temperature-compensation circuit comprises the 3rd NPN pipe, NMOS pipe, the 5th resistance, the 6th resistance and the 7th resistance;

Described start-up circuit comprises the 4th NPN pipe, the 5th NPN pipe, the 6th NPN pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 8th resistance, the 9th resistance and the tenth resistance;

Concrete annexation is following:

The base stage of the one NPN pipe links to each other with the emitter stage of the 4th NPN pipe of the base stage of the 2nd NPN pipe, said start-up circuit; Simultaneously as the benchmark output voltage; The one NPN pipe links to each other with an end of first resistance and second resistance respectively with the colelctor electrode of the 2nd NPN pipe; NPN pipe links to each other with positive input with the negative input of error amplifier circuit respectively with the colelctor electrode of the 2nd NPN pipe simultaneously; The other end of first resistance and second resistance links to each other with the drain electrode of the 2nd PMOS pipe; The source electrode of the 2nd PMOS pipe links to each other with external power source; Grid links to each other with the grid of the 4th PMOS pipe of said start-up circuit; The source electrode of the one PMOS pipe links to each other with the drain electrode of the 2nd PMOS pipe; Grid be connected in said start-up circuit the 8th resistance and the 9th resistance between; Drain electrode links to each other with ground; The emitter stage of the one NPN pipe links to each other with an end of the 3rd resistance, and the other end of the 3rd resistance is by the 4th resistance eutral grounding;

The 5th resistance, the 6th resistance and the 7th resistance are connected between the base stage and ground that a NPN manages and the 2nd NPN manages in the single order reference circuit in turn; The 2nd NPN pipe collector links to each other in the collector of the 3rd NPN pipe and the single order reference circuit, and the base stage of the 3rd NPN pipe has common that end that is connected continuous with the 6th resistance and the 7th resistance; The drain electrode of the one NMOS pipe links to each other with the collector of the 3rd NPN pipe QN6; Grid has common that end that is connected to link to each other with the 5th resistance and the 6th resistance; The emitter of the 3rd NPN pipe links to each other with the source electrode of NMOS pipe, and has common that end that is connected continuous with the 3rd resistance in the single order reference circuit with the 4th resistance;

The base stage and the colelctor electrode short circuit of the 5th NPN pipe; And link to each other with the emitter stage of the 6th NPN pipe; The emitter stage of the 5th NPN pipe links to each other with ground; The base stage and the colelctor electrode short circuit of the 6th NPN pipe; And be connected to the base stage of the 4th NPN pipe and the drain electrode of the 4th PMOS pipe pipe; The grid of the 4th PMOS pipe links to each other with an output of biasing circuit; Be connected in the grid of the 2nd PMOS pipe of single order reference circuit simultaneously; The 8th resistance, the 9th resistance and the tenth resistance are connected between the emitter stage and ground of the 4th NPN pipe in turn; The colelctor electrode of the 4th NPN pipe links to each other with the drain electrode of the 3rd PMOS pipe; The grid of the 3rd PMOS pipe and drain electrode short circuit, the 3rd PMOS pipe links to each other with external power source with the source electrode of the 4th PMOS pipe.

Beneficial effect of the present invention: bandgap voltage reference of the present invention is through joining the collector current of bipolar device and the metal-oxide-semiconductor leakage current of sub-threshold region in traditional single order temperature compensation bandgap reference circuit; Promptly realize temperature compensation through pipe of the 3rd NPN in the temperature-compensation circuit and NMOS pipe; Obtain reference voltage; Use this technology, can be so that output reference voltage has less temperature coefficient.

Description of drawings

Fig. 1 is traditional bandgap reference voltage source structure synoptic diagram.

Fig. 2 is the electrical block diagram in bandgap reference voltage of the present invention source.

Fig. 3 is an error amplifier circuit structural representation of the present invention.

Fig. 4 is bandgap reference voltage of the present invention source I _{C_QN3}Temperature characterisitic and dI _{C_QN3}The temperature characterisitic synoptic diagram of/dT.

Fig. 5 is bandgap reference voltage of the present invention source I _{DS_MN1}Temperature characterisitic and dI _{DS_MN1}The temperature characterisitic synoptic diagram of/dT.

Fig. 6 is the temperature characterisitic synoptic diagram of bandgap reference voltage of the present invention source output voltage.

Fig. 7 is synoptic diagram start-up time in bandgap reference voltage of the present invention source.

Fig. 8 is the Power Supply Rejection Ratio synoptic diagram in bandgap reference voltage of the present invention source.

Fig. 9 is the synoptic diagram that concerns of the output voltage in bandgap reference voltage of the present invention source and supply voltage.

Embodiment

Below in conjunction with accompanying drawing and concrete embodiment the present invention is done further elaboration.

Bandgap reference voltage of the present invention source as shown in Figure 2; Comprise: biasing circuit, start-up circuit, single order reference circuit, temperature-compensation circuit and error amplifier circuit; Wherein, Described biasing circuit is that described bandgap reference voltage source provides bias voltage; Described start-up circuit is used to make single order reference circuit operate as normal; Said single order reference circuit produces the reference voltage of low-temperature coefficient; Described temperature-compensation circuit is used for the single order reference circuit is carried out temperature compensation, and said error amplifier circuit is used for stablizing the working point of single order reference circuit.

Here, the single order reference circuit comprises NPN pipe QN1, the 2nd NPN pipe QN2, PMOS pipe MP1, the 2nd PMOS pipe MP2, first resistance R 1, second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4.

Here, temperature-compensation circuit comprises the 3rd NPN pipe QN3, NMOS pipe MN1, the 5th resistance R 5, the 6th resistance R 6 and the 7th resistance R 7;

Here, start-up circuit comprises the 4th NPN pipe QN4, the 5th NPN pipe QN5, the 6th NPN pipe QN6, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 8th resistance R 8, the 9th resistance R 9 and the tenth resistance R 10;

Concrete annexation is following:

The base stage of the one NPN pipe QN1 links to each other with the emitter stage of the 4th NPN pipe QN4 of the base stage of the 2nd NPN pipe QN2, start-up circuit; Simultaneously as the benchmark output voltage; The one NPN pipe QN1 links to each other with the end of first resistance R 1 with second resistance R 2 respectively with the colelctor electrode of the 2nd NPN pipe QN2; NPN pipe QN1 links to each other with positive input V1 with the negative input V2 of error amplifier circuit respectively with the colelctor electrode of the 2nd NPN pipe QN2 simultaneously; The other end of first resistance R 1 and second resistance R 2 links to each other with the drain electrode of the 2nd PMOS pipe MP2; The source electrode of the 2nd PMOS pipe MP2 links to each other with external power source; Grid links to each other with the grid of the 4th PMOS pipe MP4 of start-up circuit; The source electrode of the one PMOS pipe MP1 links to each other with the drain electrode of the 2nd PMOS pipe MP2; Grid be connected in start-up circuit the 8th resistance R 8 and the 9th resistance R 9 between; Drain electrode links to each other with ground; The emitter stage of the one NPN pipe QN1 links to each other with an end of the 3rd resistance R 3, and the other end of the 3rd resistance R 3 is by the 4th resistance R 4 ground connection;

The 5th resistance R 5, the 6th resistance R 6 and the 7th resistance R 7 are connected in turn that NPN pipe QN1 manages between the base stage and ground of QN2 with the 2nd NPN in the single order reference circuit; The 2nd NPN pipe collector QN2 links to each other in the collector of the 3rd NPN pipe QN3 and the single order reference circuit, and the base stage of the 3rd NPN pipe QN3 has common that end that is connected continuous with the 6th resistance R 6 and the 7th resistance R 7; The drain electrode of the one NMOS pipe MN1 links to each other with the collector of the 3rd NPN pipe QN3; Grid has common that end that is connected to link to each other with the 5th resistance R 5 and the 6th resistance R 6; The source electrode of the emitter of the 3rd NPN pipe QN3 and NMOS pipe MN1 links to each other, and has common that end that is connected continuous with the 3rd resistance R 3 in the single order reference circuit with the 4th resistance R 4;

Base stage and the colelctor electrode short circuit of the 5th NPN pipe QN5; And link to each other with the emitter stage of the 6th NPN pipe QN6; The emitter stage of the 5th NPN pipe QN5 links to each other with ground; Base stage and the colelctor electrode short circuit of the 6th NPN pipe QN6; And be connected to the base stage of the 4th NPN pipe QN4 and the drain electrode of the 4th PMOS pipe MP4; The grid of the 4th PMOS pipe MP4 links to each other with an output of biasing circuit; Be connected in the grid of the 2nd PMOS pipe MP2 of single order reference circuit simultaneously; The 8th resistance R 8, the 9th resistance R 9 and the tenth resistance R 9 are connected between the emitter stage and ground of the 4th NPN pipe QN4 in turn; The colelctor electrode of the 4th NPN pipe QN4 links to each other with the drain electrode of the 3rd PMOS pipe MP3; The grid of the 3rd PMOS pipe MP3 and drain electrode short circuit, the 3rd PMOS pipe MP3 links to each other with external power source with the source electrode of the 4th PMOS pipe MP4.

Start-up circuit makes and single order reference circuit operate as normal produces the benchmark output voltage.Start-up circuit only plays a role when voltage-reference powers on, and after voltage-reference started completion, start-up circuit quit work, and has avoided the influence of start-up circuit to the back circuit.

Biasing circuit comprises: NPN pipe QN8, QN9, QN10, QN11 and QN12, and PMOS pipe MP6, MP7, MP8, MP9, MP10 and MP0, NMOS manages MN2, resistance R 11 and R12.Wherein, QN8, QN9, QN10, QN11, QN12 and R11 are used for producing the PTAT electric current, and MP6, MP7, MP8, MP9 and MN2 are used for the PTAT electric current that mirror image produces and come bias current to other circuit to be provided with this; MP0 is for starting pipe, and VBIAS connects the grid of MP0 as input end, and the grid voltage VB1 of MP9 and MP10, MP6 and MP7, MN2, VB2, VB3 are that error amplifier circuit and start-up circuit provide bias voltage as the output terminal of biasing circuit.

Here error amplifier circuit can adopt following a kind of scheme; Specifically as shown in Figure 3; Comprise: NPN pipe QAN1, QAN2, QAN3, QAN4, QAN5 and QAN6; PNP pipe QAP1 and QAP2; PMOS pipe MAP1, MAP2, MAP3, MAP4, MAP5, MAP6, MAP7 and MP5; NMOS pipe MAN1, MAN2, MAN3 and MAN4, resistance R AP1, RAP2, RAP3 and RAP4, capacitor C 0.Wherein, The source electrode of MAP1, MAP3, MAP5 and MAP7 links to each other with power supply; Grid links to each other; And be connected in the VB2 point of biasing circuit; The drain electrode of MAP1, MAP3 and MAP5 links to each other with the source electrode of MAP2, MAP4 and MAP6 respectively; The grid of MAP2, MAP4 and MAP6 links to each other; And be connected in the VB3 point of biasing circuit; The drain electrode of MP7 links to each other with the drain electrode of MAN4, and as the output terminal of error amplifier circuit, the source electrode of MAN4 links to each other with ground; Grid links to each other with the drain electrode of MAN3; The source ground of MAN1, MAN2 and MAN3, grid links to each other, and is connected to the VB1 point of biasing circuit; The base stage of QAN1 and QAN2 is the input end of error amplifier circuit; Collector links to each other with power supply; The emitter of QAN1 and the base stage of QAP1; The drain electrode of MAN1 links to each other; The emitter of QAN2 and the base stage of QAP2; The drain electrode of MAN2 links to each other; The emitter of QAP1 and QAP2 links to each other; And connection links to each other with the drain electrode of MAP2; The emitter of the collector of QAP1 (being the SS point) and QAN3; The source electrode of MP4 links to each other; The collector of QAP2 links to each other with the emitter of QAN4; The base stage of QAN3 and QAN4; The emitter of QAN5 links to each other; The collector of QAN3 and QAN4 links to each other with the drain electrode of MAP4 and MAP6 respectively; The base stage of QAN5 links to each other with the emitter of QAN3; Collector links to each other with power supply; Resistance R AP1; RAP2; RAP3 connects respectively and QAN3; Between the emitter and ground of QAN4 and QAN5; The base stage of QAN6; The collector of emitter and QAN4; The drain electrode of MAN3 links to each other, and resistance R A4 and capacitor C 0 are connected between the drain electrode of source electrode and MAN4 of base stage MP5 of QAN6 in turn, and the drain electrode of MP5 links to each other with external power source.

As a preferable scheme, the grid of the pipe of the PMOS in error amplifier circuit MP5 grid with the 3rd PMOS pipe MP3 of start-up circuit linked to each other, like this, when just powering on, introduce offset current to error amplifier circuit, shorten start-up time with this.

Also have NPN pipe QN7, NMOS pipe MN0 and capacitor C 1 to be connected in this bandgap reference voltage source in addition; Wherein the collector of QN7 connects external power source; Base stage links to each other with the error amplifier circuit output terminal; Emitter links to each other with the MN0 drain electrode; MN0 source ground, grid are connected in the grid of MAN4 in the error amplifier circuit.C1 one end links to each other with ground, the output of another termination voltage-reference.Here, QN7 and MN0 are as the output buffer stage of voltage-reference, and C0 is as filter capacitor.

Set forth from the following aspects respectively.

1. the whole principle explanation of voltage-reference of the present invention:

Do not consider base current, error amplifier circuit makes the V1=V2 so the output voltage V of voltage-reference _REFFor:

$V_{\mathrm{REF}}\&ap;V_{\mathrm{BE}2}+\frac{{2R}_4}{R_3}{V}_T\ln N\frac{I_{C1}-I_{\mathrm{DS}\_\mathrm{MN}1}-I_{C\_\mathrm{QN}3}}{{\mathrm{<figure-callout\; id="1"\; label="I\; C"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_C}+I_{\mathrm{DS}\_\mathrm{MN}1}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4+I_{C\_\mathrm{QN}3}{R}_4---\left(1\right)$

Wherein, N is the ratio of the emitter area of QN1 and QN2, V _TBe thermal voltage, I _{DS_MN1}Be the leakage current of MN2, I _{C_QN3}Be the emitter current of QN3, all simultaneously resistance is all realized with same material.Wherein the BE junction voltage is:

V _BE＝V _G0+mV _T-(η-α)V _Tln _T (2)

$V_T\ln =\frac{k}{q}[\left({T-T}_0\right)+\frac{1}{2}{(T-T_0)}^2-\frac{1}{6}{(T-T_0)}^3+\frac{1}{12}{\left({T-T}_0\right)}^4]---\left(3\right)$

Can know the output voltage V of voltage-reference by Fig. 2 and formula (2), (3) _REFFor:

$V_{\mathrm{REF}}={\mathrm{<figure-callout\; id="0"\; label="V\; G"\; filenames="HDA0000081264900000022.png"\; state="\{\{state\}\}">V</figure-callout>}}_G+{\mathrm{mV}}_T-(\mathrm{\&eta;}-\mathrm{\&alpha;})V_T\ln T+\frac{{2R}_4}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}+V_T\ln N\frac{I_{C1}-I_{\mathrm{DS}\_\mathrm{MN}1}-I_{C\_\mathrm{QN}3}}{{\mathrm{<figure-callout\; id="1"\; label="I\; C"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_C}+I_{\mathrm{DS}\_\mathrm{MN}1}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4+I_{C\_\mathrm{QN}3}{R}_4---\left(4\right)$

The m here is temperature independent constant, and α is I _CAbout the exponent number in the expression formula of temperature, R ₃, R ₄Be respectively the resistance of the 3rd resistance R 3 and the 4th resistance R 4, V _TBe thermal voltage, V _T=kT/q, V _G0Be the intrinsic band gap voltage of silicon when 0K, η is a constant between 3 and 4, generally is about 3.45.Can know V from (3) _TLnT demonstrates V _BEHigh-order nonlinear temperature item, and the single order temperature compensation only compensation temperature T once, therefore need carry out high-order temperature compensated.Can get (4) differentiate:

$\frac{{\&PartialD;V}_{\mathrm{REF}}}{\&PartialD;T}=m\frac{k}{q}-(\mathrm{\&eta;}-\mathrm{\&alpha;})-\frac{k}{q}(1+\ln T)+\frac{{2R}_4}{R_3}\frac{k}{q}\ln N\frac{I_{C1}-I_{\mathrm{DS}\_\mathrm{MN}1}-I_{C\_\mathrm{QN}3}}{I_{C1}}$ (5)

$+\frac{{2R}_4}{R_3}{V}_T\frac{1}{I_{C1}-I_{\mathrm{DS}\_\mathrm{MN}1}-I_{C\_\mathrm{QN}3}}(-\frac{{\&PartialD;I}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\&PartialD;T}-\frac{{\&PartialD;I}_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}}{\&PartialD;T})+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4\frac{{\&PartialD;I}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\&PartialD;T}+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4\frac{{\&PartialD;I}_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}}{\&PartialD;T}$

Because I _{DS_MN1}And I _{C_QN3}Be far smaller than the collector current of QN1 and QN2, because of I _C1-I _{DS_MN1}-I _{C_QN3}≈ I _C1So following formula can be approximated to be:

$\frac{{\&PartialD;V}_{\mathrm{REF}}}{\&PartialD;T}=m\frac{k}{q}-(\mathrm{\&eta;}-\mathrm{\&alpha;})\frac{k}{q}(1+\ln T)+\frac{{2R}_4}{R_3}\frac{k}{q}\ln N-R_4(\frac{{2V}_T}{R_3{\mathrm{<figure-callout\; id="1"\; label="I\; C"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_C}\frac{{\&PartialD;I}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\&PartialD;T}-1)-R_4(\frac{{2V}_T}{R_3{\mathrm{<figure-callout\; id="1"\; label="I\; C"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_C}\frac{{\&PartialD;I}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\&PartialD;T}-1)---\left(6\right)$

Band-gap reference through to the single order temperature compensation carries out temperature compensation, can obtain three extreme points, promptly at T ₁, T ₂, T ₃The time temperature coefficient be zero, T wherein ₁＜T ₂＜T ₃, order:

$f_1\left(T\right)=m\frac{k}{q}-(\mathrm{\&eta;}-\mathrm{\&alpha;})\frac{k}{q}(1+\ln T)+\frac{{2R}_4}{R_3}\frac{k}{q}\ln N---\left(7\right)$

$f_2\left(T\right)=\frac{{\&PartialD;I}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\&PartialD;T}{R}_4(\frac{{2V}_T}{R_3{I}_{\mathrm{PTAT}}}-1)+\frac{{\&PartialD;I}_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}}{\&PartialD;T}{R}_4(\frac{{2V}_T}{R_3{I}_{\mathrm{PTAT}}}-1)---\left(8\right)$

At T ₁And T ₃Point is zero, is f ₁(T ₁)=f ₂(T ₁), f ₁(T ₂)=f ₂(T ₂), f ₁(T ₃)=f ₂(T ₃), above three formulas of simultaneous can obtain

(back will be introduced in detail) and Satisfy above-mentioned three formulas.

2. the temperature characterisitic of bipolar devices collector current:

Curvature compensation realizes that through MN1 and QN3 wherein the collector current of QN3 is I _{C_QN3}For:

$I_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}=I_{\mathrm{ES}3}[\exp \left(\frac{q{V}_{\mathrm{BE}3}}{\mathrm{kT}}\right)-1]---\left(9\right)$

Wherein, the base voltage of QN3 is and V _REFProportional, be temperature independent voltage, and the PTAT voltage that its emitter voltage PTAT electric current that to be the single order reference circuit produce produces on resistance, think the voltage of positive temperature coefficient so V _BE3Be the voltage that becomes negative temperature coefficient with temperature.

$I_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}=I_{\mathrm{ES}3}[\exp \left(\frac{q(\frac{R_7}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_5+R_6+R_7}{V}_{\mathrm{REF}}-{2I}_{\mathrm{PTAT}2}{R}_4)}{\mathrm{kT}}\right)-1]---\left(10\right)$

And I _ES3For the anti-saturation current partially time of emitter junction, be generally a constant, can be write as:

${\mathrm{<figure-callout\; id="3"\; label="I\; ES"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{ES}}={\mathrm{ET}}^{\mathrm{\&gamma;}}\exp (-\frac{{\mathrm{qV}}_G}{\mathrm{kT}})---\left(11\right)$

Wherein, E is temperature independent constant, γ=4-n, and n is relevant with the doped level of base stage.Can get by (10), (11) and Fig. 2:

$I_{C\_\mathrm{<figure-callout\; id="3"\; label="QN"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">QN</figure-callout>}3}\&ap;{\mathrm{ET}}^{\mathrm{\&gamma;}}\exp [-\frac{q(V_G-\frac{R_7}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_5+R_6+R_7}{V}_{\mathrm{REF}}+{2I}_{\mathrm{PTAT}2}{R}_4)}{\mathrm{kT}}]---\left(12\right)$

Wherein, V _GBe approximately 1.2V, $\frac{R_7}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_5+R_6+R_7}{V}_{\mathrm{REF}}-2I_{\mathrm{PTAT}2}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4<1.2V,$ So:

$V_G-\frac{R_7}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_5+R_6+R_7}{V}_{\mathrm{REF}}+{2I}_{\mathrm{PTAT}2}{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_4>0,$ So I _{C_QN3}Increase with temperature increases.

The present invention carries out the used QN3 current I of temperature compensation _{C_QN3}And dI _{C_QN3}The temperature characterisitic simulation curve of/dT can find out in whole temperature range as shown in Figure 4, and temperature coefficient is being for just, and raises and increase gradually with temperature.

3. the temperature characterisitic of the metal-oxide-semiconductor leakage current of sub-threshold region:

MN1 is operated in weak inversion regime, and the leakage current of MN1 is:

$I_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}=\frac{W}{L}\mathrm{\&mu;}\left(T_0\right){\left(\frac{T}{T_0}\right)}^{-n}{\left(\frac{\mathrm{kT}}{q}\right)}^3{C}_D\exp \left(\frac{q}{\mathrm{kT}}\frac{V_{\mathrm{GS}\_\mathrm{MN}1}-V_{\mathrm{TH}}}{n}\right)[1-\exp (-\frac{{\mathrm{qV}}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\mathrm{kT}})]---\left(13\right)$

Wherein, μ _nBe electron mobility, C _DBe the depletion-layer capacitance under the raceway groove, and n=1+C _D/ C _OX, C _OXCapacitive oxide for the unit area from the grid to the raceway groove.

Work as V _{DS_MN1}During kT/q, formula (13) can be approximated to be:

$I_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}\&ap;\frac{W}{L}\mathrm{\&mu;}\left(T_0\right){\left(\frac{T}{T_0}\right)}^{-n}{\left(\frac{\mathrm{kT}}{q}\right)}^2{C}_D\exp \left(\frac{q}{\mathrm{kT}}\frac{V_{\mathrm{GS}\_\mathrm{MN}1}-V_{\mathrm{TH}}}{n}\right)---\left(14\right)$

$V_{\mathrm{GS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}=\frac{R_6+R_7}{{\mathrm{<figure-callout\; id="5"\; label="R"\; filenames="HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_5+R_6+R_7}{V}_{\mathrm{REF}}-\frac{{2R}_4}{R_3}{V}_T\ln N---\left(15\right)$

With formula (15) substitution (14) and carry out differentiate and can get:

$\frac{{\mathrm{dI}}_{\mathrm{DS}\_\mathrm{<figure-callout\; id="1"\; label="MN"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">MN</figure-callout>}1}}{\mathrm{dT}}=\frac{W}{L}{C}_D{\left(\frac{k}{q}\right)}^2\mathrm{\&mu;}\left(T_0\right)\frac{1}{T_0^{-n}}\exp \left(\frac{q(A-V_{\mathrm{TH}})}{\mathrm{nkT}}\right)T^{-n}[(2-n)T-\frac{\mathrm{qT}}{\mathrm{kn}}\frac{{\&PartialD;V}_{\mathrm{TH}}}{\&PartialD;T}-\frac{q}{\mathrm{kn}}(A-V_{\mathrm{TH}})]---\left(16\right)$

$V_t={\mathrm{\&phi;}}_{\mathrm{ms}}+{2\mathrm{\&phi;}}_f-\frac{Q_{\mathrm{ss}}}{C_{\mathrm{ox}}}+\mathrm{\&gamma;}(\sqrt{2{\mathrm{\&phi;}}_f+V_{\mathrm{SB}}}-\sqrt{{2\mathrm{\&phi;}}_f})---\left(17\right)$

$\frac{{\mathrm{dV}}_t}{\mathrm{dT}}=-\frac{1}{T}(\frac{E_g}{2q}-{\mathrm{\&phi;}}_f)(2+\frac{\mathrm{\&gamma;}}{\sqrt{{2\mathrm{\&phi;}}_f}})---\left(18\right)$

Therefore, threshold voltage and temperature are not linear relationships, and absolute value temperature coefficient can reduce along with the increase of temperature.Can find out, (2-n) T＞0,

With the rising of temperature, (2-n) T increases gradually, Reduce gradually, and reduce the speed that speed increases greater than (2-n) T,

Remain unchanged, can obtain like Fig. 5 thus about I _{DS_MN1}And dI _{DS_MN1}The simulation curve figure of/dT, when temperature lower (through being measured as-38 ℃), temperature coefficient is for just; When temperature raise, temperature coefficient was for negative.

4. error amplifier circuit analysis:

As can be seen from Figure 3; Error amplifier circuit (amplifier) adopts collapsible two-layer configuration; The input end of error amplifier circuit adopts emitter follower that input voltage is reduced a BE junction voltage; And then the input that input voltage is connected to amplifier is to pipe QAP1 and QAP2, to satisfy the input voltage range of amplifier.The effect of QAN5 is amplifier to be exported from both-end become single-ended output, and the effect of QAN5 and resistance R A3 is the electric current that increases on the QAN5, prevents that the electric current of QAN5 is zero in some cases, can not accomplish both-end and change single-ended.The gain of error amplifier circuit is big more, and its clamping performance is good more, and more little by the caused systematic error of finite gain, wherein the DC current gain of error amplifier circuit is:

A _V＝A _V1A _V2＝g _mg _mq[g _mr _op3r _op4||r _oq(g _mqR _A1||r _oq)]r _op7r _0n4 (19)

Wherein, A _V1And A _V2Be respectively the gain of the error amplifier circuit first order and the second level, g _mAnd g _MqBe respectively the mutual conductance of metal-oxide-semiconductor and bipolar transistor, r _OqBe the output resistance of bipolar transistor, r _Op3, r _Op4, r _Op7And r _On4Be respectively the output resistance of MAP3, MAP4, MAP7 and MAN4.

Here, capacitor C 0 is a Miller capacitance, is used to realize the limit separation, guarantees that loop has enough phase margins, realizes that circuit is stable; Resistance R A4 is a zero compensation resistance, is used to offset the influence to loop stability at RHP zero point; The high-gain of two stage amplifer has also guaranteed the high PSRR of voltage-reference.

5. biasing circuit explanation:

Inject when QN8 and QN9 base stage have electric current, make MP6 and MP7 place branch road break away from 1 degeneracy point and begin operate as normal,, set up normal working point for the single order reference circuit provides one PTAT electric current, wherein:

V _BEQN8+V _BEQN11＝V _BEQN10+V _BEQN9+V _R11 (20)

Ignore base current, I _CQN8=I _CQN10, I _CQN9=I _CQN11And the parallelly connected number of QN9 and QN10 is to be respectively QN8 and QN11 3 times, then has:

${\mathrm{\&Delta;V}}_{\mathrm{BE}}=V_{\mathrm{BEQN}8}-{\mathrm{<figure-callout\; id="10"\; label="V\; BEQN"\; filenames="HDA0000081264900000032.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BEQN}}+V_{\mathrm{BEQN}11}-V_{\mathrm{BEQN}9}=V_T\ln \left(\frac{I_{\mathrm{SQN}10}}{I_{\mathrm{SQN}8}}\right)+V_T\ln \left(\frac{I_{\mathrm{SQN}9}}{I_{\mathrm{SQN}11}}\right)={2\mathrm{<figure-callout\; id="3"\; label="V\; T\; ln"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">V</figure-callout>}}_T\ln 3=V_{R11}---\left(21\right)$

Can get: $I_{\mathrm{PTAT}1}=I_{R11}=\frac{V_{R11}}{R_{11}}=\frac{{2V}_T\ln 3}{R_{11}}---\left(22\right)$

Can find out that from following formula the last electric current of R11 is the PTAT electric current, then the mirror image of this electric current through MP6 act as other branch road provides bias current.Being mirrored to single order reference circuit electric current through MP2 is KI _PTAT1, wherein K is the ratio of the breadth length ratio of MP2 and MP6.Have the analysis of front to know, the single order reference circuit produces other one PTAT electric current and is:

$I_{\mathrm{PTAT}2}=I_{R3}=\frac{V_{\mathrm{BEQN}2}-V_{\mathrm{BEQN}1}}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{BE}}}{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA0000081264900000012.png,HDA0000081264900000033.png"\; state="\{\{state\}\}">R</figure-callout>}}_3}=\frac{V_T\ln 8}{R_3}---\left(23\right)$

Then the electric current through MP2 is 2I _PTAT2, when the electric current that on MP2, produces when two strands of PATA electric currents is unequal, need the design flow equalizing circuit, so that reference source can produce a stable working point.Therefore MP1 promptly realizes current-sharing, makes the KI that mirror image obtains on MP2 _PTAT12I with the generation of single order reference circuit _PTAT2Equate.Work as KI _PTAT1＞2I _PTAT2, then unnecessary electric current can flow among the MP1.

6. start-up course explanation:

At first be to inject the base stage of one electric current to QN8 and QN9 through the MP0 pipe, biasing circuit starts, and make MP8 and MP9 place branch road and MP10 and the branch road conducting of QN12 place, and other part of benchmark provides bias voltage.

After biasing circuit started, MP4 managed conducting, made this road conducting, and the QN6 collector voltage is 2V _BE, because this moment, the single order reference circuit turn-offed, V _REFBe zero, so QN4 pipe conducting this moment, start-up circuit injects one electric current can for the single order reference circuit like this, makes the single order reference circuit break away from odd-job and makes state.

Simultaneously; Because QN6 conducting; Make MP3 belong to the branch road conducting; The electric current of MP5 mirror image MP3 injects one offset current can for the node SS of error amplifier; The electric current of resistance R A1 is greater than the electric current of resistance R A2 at this moment, and this situation is equivalent to negative terminal voltage V1 and is lower than anode V2, through the amplification of amplifier; VREF voltage can be drawn high, thereby accelerates the start-up time of voltage-reference.Wherein, the offset voltage Δ B of introducing _EEFor:

${\mathrm{\&Delta;V}}_{\mathrm{BE}}=V_{\mathrm{BEQAP}1}-V_{\mathrm{BEQAP}2}=V_T\ln \left(\frac{I_{\mathrm{CQAP}1}}{I_{\mathrm{CQAP}2}}\right)=V_T\ln \left(\frac{{\mathrm{<figure-callout\; id="1"\; label="I\; PTAT"\; filenames="HDA0000081264900000011.png,HDA0000081264900000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{PTAT}}+K_2{I}_{\mathrm{PTAT}1}}{I_{\mathrm{PTAT}1}}\right)=V_T\ln (1+K_2)---\left(24\right)$

K wherein ₂For injecting the I that is injected into SS through MP5 _PTAT1The electric current multiple.After amplifying through error amplifier circuit, input offset voltage outputs to the base stage of QN1 and QN2, the startup of accelerating potential reference source.

After VREF was stable, because the base voltage of QN4 pipe is constant, and emitter voltage rose to VREF; Make QN4 turn-off, start-up circuit quits work, and MP5 turn-offs; Do not have again electric current to be injected in the error amplifier circuit, the error amplifier circuit operate as normal, start-up course is accomplished.

Fig. 6 is the temperature characteristics of voltage-reference output voltage when supply voltage is respectively 3.0V, 4.5V, 5.5V, and wherein horizontal ordinate is a temperature, and ordinate is the benchmark output voltage; Fig. 7 is the voltage-reference output voltage curve of start-up time, and wherein horizontal ordinate is the time, and ordinate is the output voltage of voltage-reference; Fig. 8 is the supply voltage rejection characteristic of voltage-reference, and horizontal ordinate is a frequency, and ordinate is the value of PSRR, can see being lower than at this voltage-reference that PSRR is 87dB in the 10K scope, at 10K～100K all greater than 60dB; Fig. 9 is the situation of change of voltage-reference output voltage with supply voltage, and wherein horizontal ordinate is a supply voltage, and ordinate is the voltage-reference output voltage.

At input voltage 3.6～5.5V, temperature range is under-40 ℃～125 ℃, carries out emulation with Hspice.The result shows, is that-40 ℃～125 ℃ these bandgap reference voltage sources have reached 1.74ppm/ ℃ temperature coefficient in temperature range, and supply-voltage rejection ratio is 87dB during low frequency, and only be 8us start-up time, and line regulation is 0.032mV/V.

Bandgap reference voltage of the present invention source mainly contains following two characteristics:

1. utilize the temperature characterisitic of metal-oxide-semiconductor leakage current of collector current and the sub-threshold region of bipolar device that traditional single order band-gap reference is carried out curvature compensation and reduce temperature coefficient; Be specially in whole temperature range, replace single extreme point through the point that on benchmark output voltage curve, produces a plurality of zero warm coefficients.

2. the stable operating point effect is not only played in the design of error amplifier circuit, can reduce the start-up time of voltage-reference simultaneously.

Claims (3)

1. bandgap reference voltage source; Comprise: biasing circuit, start-up circuit and single order reference circuit; It is characterized in that; Also comprise; Temperature-compensation circuit and error amplifier circuit; Wherein, Described biasing circuit is that described bandgap reference voltage source provides bias voltage; Described start-up circuit is used to make single order reference circuit operate as normal; Said single order reference circuit produces the reference voltage of low-temperature coefficient; Described temperature-compensation circuit is used for the single order reference circuit is carried out temperature compensation, and said error amplifier circuit is used for stablizing the working point of single order reference circuit;

Said single order reference circuit comprises NPN pipe, the 2nd NPN pipe, PMOS pipe, the 2nd PMOS pipe, first resistance, second resistance, the 3rd resistance and the 4th resistance;

Described temperature-compensation circuit comprises the 3rd NPN pipe, NMOS pipe, the 5th resistance, the 6th resistance and the 7th resistance;

Described start-up circuit comprises the 4th NPN pipe, the 5th NPN pipe, the 6th NPN pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 8th resistance, the 9th resistance and the tenth resistance;

Concrete annexation is following:

The base stage of the one NPN pipe links to each other with the emitter stage of the 4th NPN pipe of the base stage of the 2nd NPN pipe, said start-up circuit; Simultaneously as the benchmark output voltage; The one NPN pipe links to each other with an end of first resistance and second resistance respectively with the colelctor electrode of the 2nd NPN pipe; NPN pipe links to each other with positive input with the negative input of error amplifier circuit respectively with the colelctor electrode of the 2nd NPN pipe simultaneously; The other end of first resistance and second resistance links to each other with the drain electrode of the 2nd PMOS pipe; The source electrode of the 2nd PMOS pipe links to each other with external power source; Grid links to each other with the grid of the 4th PMOS pipe of said start-up circuit; The source electrode of the one PMOS pipe links to each other with the drain electrode of the 2nd PMOS pipe; Grid be connected in said start-up circuit the 8th resistance and the 9th resistance between; Drain electrode links to each other with ground; The emitter stage of the one NPN pipe links to each other with an end of the 3rd resistance, and the other end of the 3rd resistance is by the 4th resistance eutral grounding;

The 5th resistance, the 6th resistance and the 7th resistance are connected between the base stage and ground that a NPN manages and the 2nd NPN manages in the single order reference circuit in turn; The 2nd NPN pipe collector links to each other in the collector of the 3rd NPN pipe and the single order reference circuit, and the base stage of the 3rd NPN pipe has common that end that is connected continuous with the 6th resistance and the 7th resistance; The drain electrode of the one NMOS pipe links to each other with the collector of the 3rd NPN pipe QN6; Grid has common that end that is connected to link to each other with the 5th resistance and the 6th resistance; The emitter of the 3rd NPN pipe links to each other with the source electrode of NMOS pipe, and has common that end that is connected continuous with the 3rd resistance in the single order reference circuit with the 4th resistance;

The base stage and the colelctor electrode short circuit of the 5th NPN pipe; And link to each other with the emitter stage of the 6th NPN pipe; The emitter stage of the 5th NPN pipe links to each other with ground; The base stage and the colelctor electrode short circuit of the 6th NPN pipe; And be connected to the base stage of the 4th NPN pipe and the drain electrode of the 4th PMOS pipe pipe; The grid of the 4th PMOS pipe links to each other with an output of biasing circuit; Be connected in the grid of the 2nd PMOS pipe of single order reference circuit simultaneously; The 8th resistance, the 9th resistance and the tenth resistance are connected between the emitter stage and ground of the 4th NPN pipe in turn; The colelctor electrode of the 4th NPN pipe links to each other with the drain electrode of the 3rd PMOS pipe; The grid of the 3rd PMOS pipe and drain electrode short circuit, the 3rd PMOS pipe links to each other with external power source with the source electrode of the 4th PMOS pipe.

2. bandgap reference voltage according to claim 1 source; It is characterized in that; Described error amplifier circuit comprises: NPN pipe QAN1, QAN2, QAN3, QAN4, QAN5 and QAN6, PNP pipe QAP1 and QAP2, PMOS pipe MAP1, MAP2, MAP3, MAP4, MAP5, MAP6, MAP7 and MP5; NMOS pipe MAN1, MAN2, MAN3 and MAN4; Resistance R AP1, RAP2, RAP3 and RAP4, capacitor C 0, wherein; The source electrode of MAP1, MAP3, MAP5 and MAP7 links to each other with power supply, and grid links to each other; The drain electrode of MAP1, MAP3 and MAP5 links to each other with the source electrode of MAP2, MAP4 and MAP6 respectively; The grid of MAP2, MAP4 and MAP6 links to each other; The drain electrode of MP7 links to each other with the drain electrode of MAN4; And as the output terminal of error amplifier circuit; The source electrode of MAN4 links to each other with ground; Grid links to each other with the drain electrode of MAN3, the source ground of MAN1, MAN2 and MAN3, and grid links to each other; The base stage of QAN1 and QAN2 is the input end of error amplifier circuit; Collector links to each other with power supply; The emitter of QAN1 and the base stage of QAP1; The drain electrode of MAN1 links to each other; The emitter of QAN2 and the base stage of QAP2; The drain electrode of MAN2 links to each other; The emitter of QAP1 and QAP2 links to each other; And connection links to each other with the drain electrode of MAP2; The collector of QAP1 and the emitter of QAN3; The source electrode of MP4 links to each other; The collector of QAP2 links to each other with the emitter of QAN4; The base stage of QAN3 and QAN4; The emitter of QAN5 links to each other; The collector of QAN3 and QAN4 links to each other with the drain electrode of MAP4 and MAP6 respectively; The base stage of QAN5 links to each other with the emitter of QAN3; Collector links to each other with power supply; Resistance R AP1; RAP2; RAP3 connects respectively and QAN3; Between the emitter and ground of QAN4 and QAN5; The base stage of QAN6; The collector of emitter and QAN4; The drain electrode of MAN3 links to each other, and resistance R A4 and capacitor C 0 are connected between the drain electrode of source electrode and MAN4 of base stage MP5 of QAN6 in turn, and the drain electrode of MP5 links to each other with external power source.

3. bandgap reference voltage according to claim 2 source is characterized in that, the PMOS pipe MP5 grid in the described error amplifier circuit links to each other with the grid of described start-up circuit the 3rd PMOS pipe.

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