CN112928998B

CN112928998B - Bipolar transistor amplifier

Info

Publication number: CN112928998B
Application number: CN202110153677.9A
Authority: CN
Inventors: 甄志芳
Original assignee: Suzhou Sharp Microelectronics Technology Co ltd
Current assignee: Suzhou Sharp Microelectronics Technology Co ltd
Priority date: 2021-02-04
Filing date: 2021-02-04
Publication date: 2023-11-17
Anticipated expiration: 2041-02-04
Also published as: CN112928998A

Abstract

The application discloses a bipolar transistor amplifier which comprises a bipolar transistor amplifying circuit, an amplifier input pair tube virtual mirror image pair tube, an input pair tube, a mirror image tube bias current circuit, a virtual mirror image pair tube base current generating and mirror image circuit and an amplifier input pair tube working point tracking circuit. The voltages of the base electrode, the collector electrode and the emitter electrode of the input pair tube virtual mirror image pair tube of the amplifier are consistent with the voltages of the corresponding nodes of the input pair tube, so that the beta values of the input pair tube virtual mirror image pair tube of the amplifier and the input pair tube can be guaranteed to be matched accurately, the voltage is not influenced by factors such as working voltage, process angle, temperature and input common mode, and finally the base current of the input pair tube virtual mirror image pair tube can be guaranteed to be equal to the base current of the input pair tube accurately.

Description

Bipolar transistor amplifier

Technical Field

The application belongs to the technical field of electronics, and particularly relates to a bipolar input pair-transistor amplifier design method for realizing ultralow external input bias current through an internal input current bias technology.

Background

Universal amplifiers have a significant role in today's electronic circuit design. Common amplifiers mainly comprise a CMOS input pair transistor amplifier, a bipolar crystal type input pair transistor amplifier, a JFET input pair transistor amplifier and the like.

The amplifier which takes the CMOS device as the input pair tube has the advantages of high input impedance, small input bias current and the like; however, the CMOS amplifier is limited by the characteristics of poor matching, high noise and the like of the CMOS device, and generally has the challenges of direct loss and increase, poor flicker noise, low gain bandwidth and the like; bipolar transistors have the advantages of good matching, low noise, high speed, etc., but bipolar devices require base bias current, so bipolar amplifiers typically require external circuitry to provide input bias current, limiting their application in high impedance or high precision signal processing links; JFET amplifiers have good matching and noise characteristics, while also having the advantages of high input impedance and no need for bias current, but are often incompatible with JFET devices in either normal standard CMOS processes or bipolar processes, and JFET amplifiers need to be produced with special process designs and therefore do not have cost advantages.

From the beginning of the 80 th century of the 20 th century, companies such as ADI and TI gradually introduce an input base current bias technology into a bipolar operational amplifier, so that bias of an input base current of an operational amplifier inside a chip is realized, the operational amplifier is not required to extract or fan out current from the outside, and the bipolar operational amplifier with high input impedance and low input bias current is realized. Fig. 1 is a circuit diagram of an ADI mass production chip OP497, which adopts an internal input current bias technology to realize ultra-low external input current of 150pA at maximum. In order to ensure the accuracy of the mirror current of the internal bias circuit, the amplifier adopts special bipolar devices such as ultra-low base width modulation effect (early effect) bipolar devices and multi-emitter transistors, and the devices are realized on the own special process line of ADI company, but the devices with the characteristics cannot be realized in common standard bipolar industry or BCD process.

Fig. 2 shows an internal current bias circuit according to the application of chinese patent CN 206671935U. The circuit has a plurality of problems that the internal current bias circuit cannot accurately copy the bias current required by the base electrode of the input pair tube, the bias effect is finally influenced, and the reduction of the external input current is limited. The main problems are as follows:

1. mirror image proportion error of current mirror composed of MOS tubes M6 and M7: because of the poor matching characteristic of the MOS device, the matching precision of the current mirror is poor, and the ideal internal current bias requires that the current proportion of the transistors P1, P2 and P3 is an accurate set current proportion, the matching error of the MOS current mirror can directly limit the internal bias effect.

2. Mirror image proportion error of the current mirror formed by the MOS tubes M1, M2 and M3: the internal current bias requirements M1, M2 exactly match the current of M3, and as with the principle described above, the poor matching characteristics of MOS devices directly limit the internal bias effect.

3. The precise mirroring requirements of bipolar transistors P3 and P1, P2: according to the principle of an input current bias circuit, the P3 transistor needs to accurately track the working states of P1 and P2, so that accurate copying of P3 to P1 and P2 base currents is realized. In the method, the base electrode and the emitter electrode of the P3 transistor are used for tracking the working points of the P1 and P2 transistors, but the collector electrode of the P3 transistor is completely irrelevant to the P1 and P2 transistors. For a transistor with an ultralow base width modulation effect, the working point tracking is not important, but for a common standard BCD process, beta is obviously influenced by Vce voltage due to the base width modulation effect of the bipolar transistor, so that the mirror image precision of P3 base current to P1 and P2 base currents is limited, and the effect of internal current bias is finally influenced.

Disclosure of Invention

In order to overcome the problems existing in the background art, the application provides a bipolar amplifier for realizing ultralow external bias current.

The application discloses a bipolar transistor amplifier, which comprises:

the bipolar transistor amplifying circuit comprises a bipolar input pair tube and an output load circuit, and is used for realizing an amplifier;

the amplifier input pair tube virtual mirror image pair tube, the collector electrodes of the virtual mirror image pair tube are respectively connected with the collector electrodes of the input pair tube and are used for mirroring the working current of the input pair tube.

More preferably, the bipolar transistor amplifying circuit comprises bipolar input pair transistors QD1 and QD2 and an output load circuit, wherein the common emitter of QD1 and QD2 is used as a voltage node Vtail;

when the input pair transistor is an NPN transistor, vtail=Vcmi-Vben; the collectors of QD1 and QD2 are connected with a power supply through an output load;

when the input pair transistor is a PNP transistor, vtail=vcmi+vbep; the collectors of QD1 and QD2 are connected to ground through an output load.

Specifically, the amplifier input pair tube virtual mirror pair tube comprises bipolar transistors QDC1 and QDC2 which are the same as QD1 and QD2, and collector nodes Va and Vb of the two transistors are correspondingly connected with QD1 and QD2 respectively so as to ensure that the mirror pair tube and the input pair tube have the same collector working voltage; the QDC1 and QDC2 are used as a common base electrode of the voltage node Vcm, and the common emitter is used as a voltage node Vtrck4.

More preferably, the device also comprises an input pair transistor and a virtual mirror pair transistor bias current circuit thereof, and specifically comprises a current mirror composed of bipolar transistors QC1, QC2 and QC3, wherein QC1, QC2 and QC3 share a base, and a collector of QC2 is connected with a common emitter of the input pair transistor; the collector electrode of QC3 is connected with the public emitter electrode of the virtual mirror image pair tube;

when the input pair transistors are NPN transistors, the emitters of QC1, QC2 and QC3 are connected with the ground, and the collector of QC1 is connected with an input current source;

when the input pair transistors are PNP transistors, the emitters of QC1, QC2 and QC3 are connected with a power supply, and the collector of QC1 is connected with an input current drain.

Specifically, the input pair transistor and the virtual mirror pair transistor bias current circuit thereof further comprise a first MOS transistor for carrying out base current bias on a current mirror formed by QC1, QC2 and QC 3; the grid electrode of the first MOS tube is connected with the collector electrode of QC1, and the source electrode of the first MOS tube is connected with the public base electrodes of QC1, QC2 and QC 3; the first MOS tube ensures that the current values of QC2 and QC3 images are not influenced by the base current of the bipolar device;

when the input pair tube is an NPN transistor, the first MOS tube is an NMOS tube, and the drain electrode of the first MOS tube is connected with a power supply;

when the input pair tube is a PNP transistor, the first MOS tube is a PMOS tube, and the drain electrode of the first MOS tube is connected with the ground.

More preferably, the circuit further comprises a virtual mirror pair transistor base current generating and mirror circuit, and specifically comprises a current mirror formed by bipolar transistors QBC1, QBC2 and QBC3, wherein the common base of the QBC1, QBC2 and QBC3 is used as a voltage node Vtrck3, the collectors of the QBC2 and QBC3 are respectively connected with the base of the input pair transistors QD2 and QD1, and the common emitter of the QBC1, QBC2 and QBC3 is used as a Vtrck node of the amplifier input pair transistor operating point tracking circuit; the collector electrode of the OBC1 is connected with the public base electrode of the virtual mirror image pair tube; wherein QBC1 is used to drive the base currents of QDC1 and QDC2, QBC2 and QBC3 mirror the currents respectively and are used to bias the base currents of amplifier input pair transistors QD2 and QD 1.

Specifically, the virtual mirror image pair transistor base current generation and mirror image circuit further comprises a second MOS tube, wherein the grid electrode of the second MOS tube is connected with the collector electrode of the QBC1, the source electrode of the second MOS tube is connected with the public base electrode of the QBC1, the QBC2 and the QBC3, the second MOS tube ensures that the mirror image current values of QC2 and QC3 are not influenced by the base current of the bipolar device, and therefore accurate mirror image is realized on the virtual mirror image pair transistor base current;

when the input pair tube is an NPN transistor, the second MOS tube is a PMOS tube, and the drain electrode of the second MOS tube is connected with the ground;

when the input pair tube is a PNP transistor, the second MOS tube is an NMOS tube, and the drain electrode of the second MOS tube is connected with a power supply.

More preferably, the circuit also comprises an amplifier input pair pipe working point tracking circuit, and the circuit comprises a third MOS pipe, wherein the grid electrode of the third MOS pipe is connected with the common emitter of the input pair pipe;

when the input pair tube is an NPN transistor, the third MOS tube is a PMOS tube, and the drain electrode of the third MOS tube is connected with the ground;

when the input pair tube is a PNP transistor, the third MOS tube is an NMOS tube, and the drain electrode of the third MOS tube is connected with a power supply.

Specifically, the amplifier input pair transistor working point tracking circuit further comprises bipolar transistors QT1 and QT2, and a source follower is formed by a third MOS transistor, the QT1 and the QT 2; the source electrode of the third MOS tube is connected with the QT1 emitter electrode; the source electrode of the third MOS transistor is used as a voltage node Vtrck1; the emitter of QT2 is connected with the Vtrck node, and the common base and the common collector of QT1 and QT2 are interconnected to serve as a voltage node Vtrck2;

the source follower is used for tracking the common mode voltage of the input pair pipe input of the amplifier, wherein;

when the input pair transistors are NPN transistors, QT1 is an NPN transistor, and QT2 is a PNP transistor; assuming that the input common-mode voltage vcmi=vip=vin, there is a tracking node vtrck=vcmi-vben+vthp+vben+vbep=vcmi+vthp+vbep;

when the input pair transistors are PNP type transistors, QT1 is a PNP type transistor, and QT2 is an NPN type transistor; assuming that the input common-mode voltage vcmi=vip=vin, there is a tracking node vtrck=vcmi+vbep-Vthn-Vbep-vben=vcmi-Vthn-Vben.

Wherein: vcmi, the input common mode voltage is used as an operational amplifier, and when the input is virtual ground, vcmi=vip=vin; vip, the base voltage is input to the non-inverting terminal; vin is the reverse end input base voltage; vben is the BE junction voltage of the NPN transistor; vbep is the BE junction voltage of the PNP transistor; vthp, turn-on voltage of PMOS transistor; vthn, the turn-on voltage of the NMOS transistor.

The beneficial effects of the application are that

1. In the application, the voltages of the base electrode, the collector electrode and the emitter electrode of the pair tube virtual mirror image pair tube QDC1 and QDC2 of the amplifier are consistent with the voltages of the corresponding nodes of the pair tube of the input stage, so that the accurate matching of beta values of QD1, QD2 and QDC1, QDC2 can be ensured, the influence of factors such as working voltage, process angle, temperature and input common mode is avoided, and finally the base currents of QDC1 and QDC2 can be ensured to be exactly equal to the base currents of QD1 and QD 2.

2. Meanwhile, the common mode voltage of input signals is tracked in real time through the amplifier input pair transistor working point tracking circuit (comprising a source follower consisting of bipolar transistors QT1 and QT2 and a third MOS tube) and fed back to the base and the emitter of QDC1 and QDC2, so that the base voltages Vcm of QDC1 and QDC2 track the input common mode voltage of QD1 and QD2, the emitter voltages Vtrck4 track the emitter voltages Vtail of QD1 and QD2, and finally the QDC1 and QDC2 accurately track the working points of the input pair transistors QD1 and QD2 in real time.

3. More preferably, collector currents of QC2 and QC3 in the input pair transistors and the mirror image tube bias current circuit thereof bias the input pair transistors QD1 and QD2 and the virtual mirror image pair transistors QDC1 and QDC2 respectively, and in order to realize the designed accurate current mirror image proportion, the current mirror is realized by adopting a bipolar device, and compared with a CMOS device, the bipolar transistor has excellent matching characteristics, so that the accuracy of emitter current proportion of QC2 and QC3 can be ensured. Meanwhile, in order to overcome the influence of bipolar transistor base current on the mirror image precision of a current mirror, base current bias is carried out on base nodes of QC1, QC2 and QC3 through a source follower realized by a first MOS tube, and the problem that the absolute value of mirror image current is influenced by current extracted from collector electrodes of QC1 by three transistor base electrodes is avoided.

4. More preferably, emitters of QBC1, QBC2 and QBC3 transistors in the virtual mirror pair transistor base current generation and mirror circuit are commonly connected to a Vtrck node of the amplifier stage input pair transistor working point tracking circuit so as to realize dynamic tracking of the voltage Vcm of the amplifier input pair transistor virtual mirror pair transistor base node to the input pair transistor common-mode voltage Vcmi; wherein,

when the input pair transistors are NPN transistors, vcm=vtrck-Vbep-vthp=vcmi, while vtrck4=vcm-vben=vcmi-vben=vtail;

when the input pair transistor is a PNP type transistor, vcm=vtrck+vben+vthn=vcmi, while vtrck4=vcm+vbep=vcmi+vbep=vtail.

The virtual mirror image is also realized by adopting bipolar transistors to the current mirror composed of QBC1, QBC2 and QBC3 in the tube base current generating and mirror image circuit, and the source-stage follower realized by adopting the second MOS tube is also used for carrying out base current bias, so that the collector currents of QBC2 and QBC3, namely the base current sum of QDC1 and QDC2, are accurately mirrored according to the design proportion. In a common standard BCD process with a low beta value of a bipolar transistor, a bipolar device is utilized to realize accurate matching of a current mirror, and a source follower realized by a MOS tube is utilized to carry out base current bias so as to avoid the influence of base current on the mirror proportion of the bipolar transistor current mirror, so that the bipolar transistor is a key technology for realizing accurate input current bias and ultralow external input current bias.

Drawings

FIG. 1 is a circuit diagram of an ADI mass production chip OP497 in the prior art

FIG. 2 is a circuit configuration diagram of an internal current bias circuit described in the background art

FIG. 3 is a circuit configuration diagram of an NPN input-to-tube amplifier and an internal current bias circuit thereof in an embodiment

FIG. 4 is a circuit configuration diagram of PNP input-to-tube amplifier and its internal current bias circuit in the embodiment

FIG. 5 (a) is a circuit configuration diagram of a current mirror in a comparative example

FIG. 5 (b) is a circuit block diagram of an NPN current mirror with NMOS source follower bias in an embodiment

Detailed Description

The application is further illustrated below with reference to examples, but the scope of the application is not limited thereto:

fig. 3 shows an amplifier of an NPN input stage implemented on the basis of the method according to the application and its input current biasing circuit. Fig. 4 shows an amplifier of a PNP input stage implemented based on the method of the application and its input current bias circuit. The circuit implementation method described in the present application will be described in detail with reference to the specific embodiment by taking the circuit shown in fig. 3 as an example.

Ensuring QDC1, QDC2 to be consistent with the respective node operating points of QD1, QD2, respectively, is a critical factor in achieving accurate current biasing. In the circuit shown in fig. 2, the transistor P3 realizes dynamic tracking of the base voltage and the emitter voltage of the transistors P1 and P2, but the collector voltage of P3 is irrelevant to the collector voltages of P1 and P2, and in the conventional standard BCD process, due to the base width modulation effect of the bipolar transistor, the β value is affected by the transistor Vce, so that the β values of P3 and P1 and P2 are affected by the operating state and are different, so that the virtual mirror pair transistors QD1 and QD2 cannot accurately mirror the operating currents of QD1 and QD2, and the generated internal bias current is deviated.

As one of the core innovation points of the application, the virtual mirror tube adopts a differential pair tube mode, the collectors of QDC1 and QDC2 are respectively connected with the collectors of QD1 and QD2, and then the base and emitter voltages of QDC1 and QDC2 are input into the pair tube working point tracking circuit through the amplifier, so that the base common mode voltage and emitter voltage of QD1 and QD2 are dynamically tracked in real time, the working voltages of each node of QDC1 and QDC2 are respectively consistent with the working voltages of QD1 and QD2 in real time, the mirror image results of QDC1 and QDC2 on QD1 and QD2 are not influenced by factors such as input common mode voltage, power supply voltage, working temperature and the like, and the ideal input current biasing effect is finally realized.

The working principle of the amplifier input pair transistor working point tracking circuit is as follows: let the input common mode voltage vcmi=vip=vin, with vtail=vip-Vben, and the PMOS device PMS2 constitutes the source follower, with vtrck1=vtail+vthp; transistors connected through two diodes QT1, QT2, respectively, can obtain vtrck=vtrck1+vben+vbep=vip+vthp+vbep; after Vbep of QBC1 is reduced, base voltages vtrck3=vtrck-vbep=vip+vthp of QBC1, QBC2 are obtained; then, after the voltage drop of the source follower PMS1, base voltages Vcm=vtrck3-vthp=vip of QDC1 and QDC2 are obtained; similarly vtrck4=vcm-vben=vip-Vben; the method can be summarized as follows: vcm=vip=vin=vcmi, vtrac4=vtail, the bases of QD1 and QD1 are combined and connected to the common point Va, the bases of QD2 and QD2 are combined and connected to the common point Vb, the working voltages of the nodes of QD1 and QD1 are consistent, the working voltages of the nodes of QD2 and QD2 are consistent, and finally accurate mirror images of QD1 and QD2 by QD1 and QD2 are realized, so that the accuracy of internal bias current is ensured.

In the figure, NPN transistors QD1, QD2 form an amplifier input pair, and when the input pair does not include an internal input current bias circuit, the base current of the pair needs to be extracted from an external circuit, and when the external signal link is a high impedance node or a precision signal processing node, the external input current can seriously affect the normal operation of the whole signal link. After the internal input current bias circuit is added, the base bias current required by normal operation of the QD1 and the QD2 is generated by the internal bias circuit without an external circuit, so that the high input impedance and the low input bias current of the bipolar input pair transistor amplifier are realized, and the application range of the bipolar amplifier is expanded.

In the figure, the amplifier input pair virtual mirror pair tube consists of QDC1 and QDC2, and it is assumed that the emitter bias currents of QD1 and QD2 and QD1 and QD2, that is, collector current ratios of current mirrors QC1, QC3 and QC2 are 1:1:2, that is, icqc2=2xcqc3=2xcqc1; if the operating point voltages of QD1, QD2 are exactly the same as QD1, QD2, the sum of the base currents of QD1, QD2 is equal to the base currents of QD1, QD2, i.e. ibqdc1+ibqdc2=ibqd1=ibqd2=icqc 1/(1+β).

The virtual mirror collects the base currents of QDC1 and QDC2 at the collectors of QBC1 in the pair-tube base current generating and mirroring circuit, that is, icqbc1=ibqdc1+ibqd2=ibqd2, and the accurate mirror image of the currents is realized through QBC2 and QBC3, according to the aforesaid arrangement icqc2=2xc3, the mirror image ratio of QBC1, QBC2 and QBC3 is set to 1:1:1, and there is icqbc2=icqbc3=icqbc1=ibqd2=ibqd2, wherein the collector currents Icqbc2 and Icqbc3 of QBC2 and QBC3 are fed back to the bases of QD2 and QD3 respectively, that is, the base current bias of the NPN input stage is completed. After the internal current bias circuit is added, the base bias current of the input stage of the NPN amplifier is not required to be extracted from an external circuit, so that the influence on an external signal link is avoided.

To achieve accurate internal input current bias, many non-ideal factors in the actual process manufacturing process need to be addressed, one of which is the mirror scale accuracy of the current mirror. In the background art, the bias current mirror circuit and the base current mirror circuit shown in fig. 2 are realized by adopting MOS devices, and because the matching characteristics of the MOS devices are poor, the current mirror realized by the conventional MOS devices is difficult to realize high-precision current mirror, and the requirement of the ultra-low input current bias circuit cannot be met. The conventional NPN current mirror cannot realize accurate current mirror due to the base current, and as shown in fig. 5 (a), there is Ibq1 =ic 1/(β+4), ibq2 =2×ibq1, ibq3= Ibq1; the corresponding is icq2=2icq1=2icq3=2ic1×β/(β+4), i.e. ic2=2ic3=2ic1×β/(β+4), where the current mirror image ratio is no longer 1:2:1 as expected by the design due to the base current. To eliminate the effect of the base current, an NMOS transistor source follower NMS1 is added to the NPN current mirror. As shown in fig. 5 (b), NMS1 provides a feedback path for QC1, while its source output can drive the base currents of QC1, QC2, QC 3; because of the high resistance characteristics of the NMS1 gate, it is not necessary to draw current from Ic 1. Thus, ibqc1=ic1/β, ibqc2=2xibqc1, ibqc3=ibqc1, and further, ibqc2=βxibqc2=2xic1, ic3=βxibqc3=ic1; the mirror ratio required for the design to achieve i1:i2:i3=1:2:1 is finally achieved.

The input pair transistor and the mirror image transistor bias current circuit and the virtual mirror image pair transistor base current generation and mirror image circuit both adopt the bipolar current mirror with the MOS source follower to bias the base current. The source follower realized by the MOS device biases the base current of the NPN current mirror, thereby not only effectively utilizing the advantage of good matching characteristic of the NPN device, but also overcoming the influence of the base current on the mirror image proportion of the current mirror, being a key technology for realizing accurate base current bias, and being one of the core innovation points of the application.

Based on the above principle, the amplifier of the PNP input stage shown in fig. 4 and its internal input current bias circuit can be designed, which is also within the protection scope of the present application.

The specific embodiments described herein are offered by way of example only to illustrate the spirit of the application. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the application or exceeding the scope of the application as defined in the accompanying claims.

Claims

1. A bipolar transistor amplifier, comprising:

the collector electrodes of the virtual mirror image geminate transistors are respectively connected with the collector electrodes of the input geminate transistors and are used for mirroring the working current of the input geminate transistors;

the bipolar transistor amplifier further comprises a virtual mirror image pair transistor base electrode current generating and mirror image circuit, and specifically comprises a current mirror formed by bipolar transistors QBC1, QBC2 and QBC3, wherein the base electrodes of the QBC1, QBC2 and QBC3 are shared, the collector electrodes of the QBC2 and QBC3 are respectively connected with the base electrodes of the input pair transistors QD2 and QD1, and the common emitter electrodes of the QBC1, QBC2 and QBC3 are used as the Vtrck nodes of the amplifier input pair transistor operating point tracking circuit; the collector electrode of the QBC1 is connected with the common base electrode of the virtual mirror image pair tube; wherein QBC1 is used to drive the base currents of QDC1 and QDC2, QBC2 and QBC3 mirror the currents respectively and are used to bias the base currents of amplifier input pair transistors QD2 and QD 1.

2. The amplifier of claim 1, wherein the bipolar transistor amplifier circuit comprises bipolar input pair transistors QD1 and QD2 and an output load circuit, QD1 and QD2 common emitters;

when the input pair transistors are NPN transistors, collectors of the QD1 and the QD2 are connected with a power supply through an output load;

when the input pair transistor is a PNP transistor, the collectors of QD1 and QD2 are connected to ground through an output load.

3. The amplifier according to claim 1, wherein the amplifier input pair tube virtual mirror pair tube comprises bipolar transistors QDC1 and QDC2 of the same type as QD1 and QD2, and collector nodes Va and Vb of the two transistors are respectively connected to QD1 and QD2 in correspondence to ensure that the mirror pair tube and the input pair tube have the same collector operating voltage; the QDC1 and QDC2 share a base and a common emitter.

4. The amplifier according to claim 1, further comprising an input pair transistor and a virtual mirror pair transistor bias current circuit thereof, specifically comprising a current mirror composed of bipolar transistors QC1, QC2, and QC3, QC1, QC2, and QC3 common base, and collector of QC2 connected to common emitter of the input pair transistor; the collector electrode of QC3 is connected with the public emitter electrode of the virtual mirror image pair tube;

5. The amplifier according to claim 4, wherein the input pair transistor and the virtual mirror pair transistor bias current circuit thereof further comprise a first MOS transistor for base current biasing of a current mirror composed of QC1, QC2 and QC 3; the grid electrode of the first MOS tube is connected with the collector electrode of QC1, and the source electrode of the first MOS tube is connected with the public base electrodes of QC1, QC2 and QC 3; the first MOS tube ensures that the current values of QC2 and QC3 images are not influenced by the base current of the bipolar device;

6. The amplifier of claim 1, wherein the virtual mirror pair transistor base current generation and mirror circuit further comprises a second MOS transistor, a gate of the second MOS transistor is connected to a collector of QBC1, and a source of the second MOS transistor is connected to a common base of QBC1, QBC2, QBC3, the second MOS transistor ensuring that QC2 and QC3 mirror current values are not affected by bipolar device base currents, thereby implementing accurate mirroring on the virtual mirror pair transistor base currents;

7. The amplifier of claim 1, further comprising an amplifier input pair tube operating point tracking circuit comprising a third MOS tube, a gate of the third MOS tube being connected to a common emitter of the input pair tube;

8. The amplifier according to claim 7, wherein the amplifier input pair-transistor operating point tracking circuit further comprises bipolar transistors QT1 and QT2, and the third MOS transistor and QT1, QT2 form a source follower; the source electrode of the third MOS tube is connected with the QT1 emitter electrode; the emitter of QT2 is connected with the input of an amplifier and is connected with the Vtrck node of a pipeline working point tracking circuit, and the common base electrode and the common collector electrode of QT1 and QT2 are interconnected;

when the input pair transistors are NPN transistors, QT1 is an NPN transistor, and QT2 is a PNP transistor;

when the input pair transistor is a PNP type transistor, QT1 is a PNP type transistor, and QT2 is an NPN type transistor.