CN112825476B

CN112825476B - Operational amplifier

Info

Publication number: CN112825476B
Application number: CN201911141031.8A
Authority: CN
Inventors: 张利地; 张海冰
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2019-11-20
Filing date: 2019-11-20
Publication date: 2022-10-14
Anticipated expiration: 2039-11-20
Also published as: CN112825476A

Abstract

The application discloses an operational amplifier, including differential input circuit and cascode amplifier circuit, wherein, differential input circuit includes differential transistor pair, cascode transistor pair and supplementary operational amplifier circuit, cascode transistor pair is connected with differential transistor pair, supplementary operational amplifier circuit is through the control terminal voltage of control cascode transistor pair to be located the source drain voltage clamp of differential transistor pair at a constant voltage value, guarantee that the transconductance of differential transistor pair does not change along with the change of common mode input voltage, show the common mode rejection ratio that has improved operational amplifier.

Description

Operational amplifier

Technical Field

The present invention relates to the field of integrated circuit technology, and more particularly, to an operational amplifier.

Background

The operational amplifier is widely applied to the control of electronic circuits, and has various requirements on various indexes of the operational amplifier such as input offset voltage, input offset current, power supply rejection ratio, common mode rejection ratio and the like according to the specific application environment of the operational amplifier. Fig. 1 shows a circuit schematic of a prior art operational amplifier. The operational amplifier can be further divided into a single-stage operational amplifier, a two-stage operational amplifier, a multi-stage operational amplifier, and the like. As shown in fig. 1, a general operational amplifier 100 of a single-stage operational amplifier is composed of a differential input circuit 110 and a cascode amplification circuit 120. The differential input circuit 110 is configured to obtain a differential current signal according to the differential input signals VIP and VIN, and the cascode circuit 120 obtains a differential amplified signal Vout according to the differential current signal. The differential input circuit 110 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a current source 111. The first PMOS transistor MP1 and the second PMOS transistor MP2 form a differential transistor pair, that is, the first ends of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to each other, the first ends of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the second end of the current source 111, and the first end of the current source 111 is connected to the positive power source terminal VDD. The control terminal of the first PMOS transistor MP1 receives the differential input signal VIP, and the control terminal of the second PMOS transistor MP2 receives the differential input signal VIN. The second ends of the first PMOS transistor MP1 and the second PMOS transistor MP2 output two paths of differential current signals, respectively.

The common-mode rejection ratio of an operational amplifier is typically dependent on the transconductance of the differential transistor pair in the differential input circuit changing when the input common-mode voltage changes. In the operational amplifier 100 of the prior art, when the input common mode voltage changes, the source-drain voltages Vds of the first PMOS transistor MP1 and the second PMOS transistor MP2 also change, which causes the transconductance of the differential transistor pair to change, and thus the common mode rejection is relatively poor.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide an operational amplifier, which ensures that the transconductance of a differential transistor pair does not change with the change of a common-mode input voltage, and significantly improves the common-mode rejection ratio of the operational amplifier.

According to an aspect of the present invention, there is provided an operational amplifier including a differential input circuit and a cascode circuit, wherein the differential input circuit includes: the differential input circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein the first PMOS tube and the second PMOS tube form a differential transistor pair, and control ends of the first PMOS tube and the second PMOS tube are used for inputting differential input signals; the first ends of the third PMOS tube and the fourth PMOS tube are respectively connected to the second ends of the first PMOS tube and the second PMOS tube, the control ends of the third PMOS tube and the fourth PMOS tube are connected with each other, and the second ends of the third PMOS tube and the fourth PMOS tube respectively output two paths of differential current signals; and the auxiliary operational amplifier circuit controls the control end voltage of the third PMOS tube and the fourth PMOS tube to enable the source drain voltage clamp of the first PMOS tube and the source drain voltage clamp of the second PMOS tube to be at a preset voltage.

Preferably, the auxiliary operational amplifier circuit comprises a first inverting input end, a second inverting input end, a positive phase input end and an output end, the first inverting input end of the auxiliary operational amplifier circuit is connected with the second end of the first PMOS transistor, the second inverting input end of the auxiliary operational amplifier circuit is connected with the second end of the second PMOS transistor, the positive phase input end of the auxiliary operational amplifier circuit is used for receiving the preset voltage, and the output end of the auxiliary operational amplifier circuit is connected with the control ends of the third PMOS transistor and the fourth PMOS transistor.

Preferably, the operational amplifier further includes a first current source, a first end of the first current source is connected to the positive power supply terminal, and a second end of the first current source is connected to the first ends of the first PMOS transistor and the second PMOS transistor.

Preferably, the operational amplifier further comprises a first resistor and a second current source connected in series between the second end of the first current source and the ground in sequence, wherein an intermediate node of the first resistor and the second current source is connected to the non-inverting input terminal of the auxiliary operational amplifier circuit to provide the preset voltage.

Preferably, the cascode circuit includes: the fifth PMOS tube, the seventh PMOS tube, the first NMOS tube and the third NMOS tube are connected between the positive power supply end and the ground in series; and a sixth PMOS transistor, an eighth PMOS transistor, a second NMOS transistor, and a fourth NMOS transistor connected in series between the positive power supply terminal and ground, wherein control terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to each other and receive a first bias voltage, control terminals of the seventh PMOS transistor and the eighth PMOS transistor are connected to each other and receive a second bias voltage, control terminals of the first NMOS transistor and the second NMOS transistor are connected to each other and receive a third bias voltage, control terminals of the third NMOS transistor and the fourth NMOS transistor are connected to each other and to a first terminal of the first NMOS transistor, second terminals of the first NMOS transistor and the second NMOS transistor are connected to second terminals of the third PMOS transistor and the fourth PMOS transistor, respectively, to receive the differential current signal, and a first terminal of the second NMOS transistor is configured to output a differential amplified signal.

According to another aspect of the present invention, there is provided an operational amplifier including a differential input circuit and a cascode amplification circuit, wherein the differential input circuit includes: the control ends of the fifth NMOS tube and the sixth NMOS tube are used for inputting differential input signals; the second ends of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the first ends of the fifth NMOS tube and the sixth NMOS tube, the control ends of the seventh NMOS tube and the eighth NMOS tube are connected with each other, and the first ends of the seventh NMOS tube and the eighth NMOS tube respectively output two paths of differential current signals; and the auxiliary operational amplifier circuit controls the control end voltages of the seventh NMOS tube and the eighth NMOS tube so as to position the source-drain voltage clamp of the fifth NMOS tube and the sixth NMOS tube at a preset voltage.

Preferably, the auxiliary operational amplifier circuit comprises a first inverting input end, a second inverting input end, a positive phase input end and an output end, the first inverting input end of the auxiliary operational amplifier circuit is connected with the first end of the fifth NMOS transistor, the second inverting input end of the auxiliary operational amplifier circuit is connected with the first end of the sixth NMOS transistor, the positive phase input end of the auxiliary operational amplifier circuit is used for receiving the preset voltage, and the output end of the auxiliary operational amplifier circuit is connected with the control ends of the seventh NMOS transistor and the eighth NMOS transistor.

Preferably, the operational amplifier further includes a third current source, a first end of the third current source is connected to the second ends of the fifth NMOS transistor and the sixth NMOS transistor, and a second end of the third current source is grounded.

Preferably, the operational amplifier further comprises a fourth current source and a second resistor connected in series between a positive power supply terminal and ground in sequence, wherein a middle node of the fourth current source and the second resistor is connected with a non-inverting input terminal of the auxiliary operational amplifier circuit to provide the preset voltage.

Preferably, the cascode amplification circuit includes: the fifth PMOS tube, the seventh PMOS tube, the first NMOS tube and the third NMOS tube are connected between the positive power supply end and the ground in series; and a sixth PMOS transistor, an eighth PMOS transistor, a second NMOS transistor, and a fourth NMOS transistor connected in series between the positive power supply terminal and ground, wherein control terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to each other and receive a first bias voltage, control terminals of the seventh PMOS transistor and the eighth PMOS transistor are connected to each other and receive a second bias voltage, control terminals of the first NMOS transistor and the second NMOS transistor are connected to each other and receive a third bias voltage, control terminals of the third NMOS transistor and the fourth NMOS transistor are connected to each other and to the first terminal of the first NMOS transistor, second terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to the first terminals of the seventh NMOS transistor and the eighth NMOS transistor, respectively, to receive the differential current signal, and the first terminal of the second NMOS transistor is configured to output a differential amplified signal.

The operational amplifier of the embodiment of the invention has the following beneficial effects.

The operational amplifier comprises a differential input circuit and a cascode amplifying circuit, wherein the differential input circuit comprises a differential transistor pair, a cascode transistor pair and an auxiliary operational amplifier circuit, the cascode transistor pair is connected with the differential transistor pair, and the auxiliary operational amplifier circuit controls the voltage of a control end of the cascode transistor pair to clamp a source voltage and a drain voltage of the differential transistor pair at a constant voltage value, so that transconductance of the differential transistor pair is ensured not to change along with the change of a common-mode input voltage, and the common-mode rejection ratio of the operational amplifier is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a circuit schematic of an operational amplifier according to the prior art;

FIG. 2 shows a circuit schematic of an operational amplifier according to a first embodiment of the invention;

fig. 3 shows a circuit schematic of another operational amplifier according to a second embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

In the present application, a Metal Oxide Semiconductor field effect transistor (MOS transistor) includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOS transistor, a current flows from the first terminal to the second terminal. The first end, the second end and the control end of a PMOS (P-type Metal Oxide Semiconductor field effect transistor) are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of an NMOS (N-type Metal Oxide Semiconductor field effect transistor) are respectively a drain electrode, a source electrode and a grid electrode.

The invention is further illustrated with reference to the following figures and examples.

Fig. 2 shows a circuit schematic of an operational amplifier according to a first embodiment of the invention. As shown in fig. 2, the operational amplifier 200 includes a differential input circuit 210 and a cascode amplification circuit 220. The differential input circuit 210 is also called a pre-stage circuit, and is generally a two-terminal input high-performance differential amplifier circuit, and its input terminals are used for inputting differential input signals VIP and VIN. The cascode circuit 220 is a main amplifying circuit of the operational amplifier, and functions to obtain a differential amplified signal Vout according to the two differential current signals of the differential input circuit 210.

Specifically, the differential input circuit 210 includes first to fourth PMOS transistors MP1 to MP4, a current source 211, and an auxiliary operational amplifier circuit 213. The first PMOS transistor MP1 and the second PMOS transistor MP2 form a differential transistor pair, that is, the first ends of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to each other, the first ends of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the second end of the current source 211, and the first end of the current source 211 is connected to the positive power source terminal VDD. The control terminals of the first PMOS transistor MP1 and the second PMOS transistor MP2 are respectively used for receiving the differential input signals VIP and VIN. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 form a cascode transistor pair, that is, the control ends of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to each other, the first ends of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively connected to the second ends of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the second ends of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively used for outputting two paths of differential current signals.

The auxiliary operational amplifier circuit 213 clamps the source-drain voltage Vds of the first PMOS transistor MP1 and the second PMOS transistor MP2 to a constant voltage value by controlling the control terminal voltages of the third PMOS transistor MP3 and the fourth PMOS transistor MP4, so that when the input common-mode voltage changes, the transconductance of the first PMOS transistor MP1 and the second PMOS transistor MP2 does not change, and the common-mode rejection ratio of the operational amplifier is improved.

Further, the auxiliary operational amplifier circuit 213 includes a first inverting input terminal, a second inverting input terminal, a non-inverting input terminal, and an output terminal. The first inverting input end and the second end of the first PMOS transistor MP1 are connected to the node a, the second inverting input end and the second end of the second PMOS transistor MP2 are connected to the node B, the normal phase input end is used for receiving the preset voltage, and the output end is connected to the control ends of the third PMOS transistor MP3 and the fourth PMOS transistor MP 4. The auxiliary operational amplifier circuit 213 adjusts the control terminal voltages of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 according to the voltage difference between the voltages of the node a and the node B and the preset voltage, so as to maintain the voltages of the node a and the node B at a preset value, thereby clamping the source-drain voltage Vds of the first PMOS transistor MP1 and the second PMOS transistor MP2 at a constant voltage value.

Further, the differential input circuit 210 further includes a first resistor R1 and a current source 212 connected in series between the second terminal of the current source 211 and the ground in sequence. The intermediate node of the first resistor R1 and the current source 212 is connected to the non-inverting input terminal of the auxiliary operational amplifier circuit 213 to provide the predetermined voltage. The auxiliary operational amplifier circuit 213 clamps the source-drain voltage Vds of the first PMOS transistor MP1 and the second PMOS transistor MP2 to:

Vds＝R1×I1

wherein, R1 is a resistance value of the first resistor R1, and I1 is a current provided by the current source 212.

The cascode circuit 220 includes fifth to eighth PMOS transistors MP5 to MP8 and first to fourth NMOS transistors MN1 to MN4.

The fifth PMOS tube MP5, the seventh PMOS tube MP7, the first NMOS tube MN1 and the third NMOS tube MN3 are sequentially connected in series with a first branch circuit between the positive power supply end VDD and the ground. In the on state of the fourth transistor, the current flows from the positive power supply terminal VDD to the ground through the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the first NMOS transistor MN1, and the third NMOS transistor MN 3.

A sixth PMOS transistor MP6, an eighth PMOS transistor MP8, a second NMOS transistor MN2, and a fourth MOS transistor MN4 are sequentially connected in series in a second branch between the positive power supply terminal VDD and ground. In the on state of the fourth transistor, the current flows from the positive power supply terminal VDD to the ground through the sixth PMOS transistor MP6, the eighth PMOS transistor MP8, the second NMOS transistor MN2, and the fourth MOS transistor MN4.

The control ends of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with each other, and the control ends of the first NMOS transistor and the second NMOS transistor receive the bias voltage Vb3. The second end of the first NMOS transistor MN1 is connected to the second end of the third PMOS transistor MP3 to receive the differential current signal output by the third PMOS transistor MP3, the second end of the second NMOS transistor MN2 is connected to the second end of the fourth PMOS transistor MP4 to receive the differential current signal output by the fourth PMOS transistor MP4, and the first end of the second NMOS transistor MN2 is configured to output the differential amplification signal Vout.

The second end of the first NMOS tube MN1 is connected with the first end of the third NMOS tube MN3, and the second end of the second NMOS tube MN2 is connected with the first end of the fourth NMOS tube MN4. Second ends of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both grounded or provided with a negative power supply terminal VSS. The control ends of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected with each other, and the control ends of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the first end of the first NMOS transistor MN 1.

The first end of the first NMOS transistor MN1 is connected to the second end of the seventh PMOS transistor MP7, and the first end of the first NMOS transistor MN2 is connected to the second end of the eighth PMOS transistor MP 8. The control terminals of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to each other, and both receive the bias voltage Vb2.

A first end of the seventh PMOS transistor MP7 is connected to a second end of the fifth PMOS transistor MP5, and a first end of the eighth PMOS transistor MP8 is connected to a second end of the sixth PMOS transistor MP 6. First terminals of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the positive power supply terminal VDD. The control terminals of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to each other, and both receive the bias voltage Vb1.

Fig. 3 shows a circuit schematic of another operational amplifier according to a second embodiment of the invention. As shown in fig. 3, the operational amplifier 300 includes a differential input circuit 310 and a cascode amplification circuit 320.

The differential input circuit 310 includes fifth to eighth NMOS transistors MN5 to MN8, a current source 311, and an auxiliary operational amplifier circuit 313. The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 form a differential transistor pair, that is, the second ends of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to each other, the second ends of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are both connected to the first end of the current source 311, and the second end of the current source 311 is grounded. The control terminals of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are respectively configured to receive the differential input signals VIP and VIN. The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 form a cascode transistor pair, that is, control ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are connected to each other, second ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are connected to first ends of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, respectively, and the first ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are used for outputting two paths of differential current signals, respectively.

The auxiliary operational amplifier circuit 313 clamps the source-drain voltages Vds of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 to a constant voltage value by controlling the control terminal voltages of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, so that when the input common-mode voltage changes, the transconductance of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 does not change, and the common-mode rejection ratio of the operational amplifier is improved.

Further, the auxiliary operational amplifier circuit 313 includes a first inverting input terminal, a second inverting input terminal, a non-inverting input terminal, and an output terminal. The first inverting input end and the first end of the fifth NMOS transistor MN5 are connected to the node A, the second inverting input end and the first end of the sixth NMOS transistor MN6 are connected to the node B, the positive phase input end is used for receiving the preset voltage, and the output end is connected with the control ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN 8. The auxiliary operational amplifier circuit 213 adjusts the voltage at the control ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 according to the voltage difference between the voltages at the node a and the node B and the preset voltage, so as to maintain the voltages at the node a and the node B at a preset value, and clamp the source-drain voltage Vds of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 at a constant voltage value.

Further, the differential input circuit 310 further includes a current source 312 and a second resistor R2 sequentially connected in series between the positive power supply terminal VDD and ground. The intermediate node of the current source 312 and the second resistor R2 is connected to the non-inverting input terminal of the auxiliary operational amplifier circuit 313 to provide the predetermined voltage. The auxiliary operational amplifier circuit 313 clamps the source-drain voltages Vds of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 to:

Vds＝R2×I2

where R2 is the resistance of the second resistor R2, and I2 is the current provided by the current source 312.

Similarly, the cascode amplification circuit 320 includes fifth to eighth PMOS transistors MP5 to MP8 and first to fourth NMOS transistors MN1 to MN4.

The fifth PMOS tube MP5, the seventh PMOS tube MP7, the first NMOS tube MN1 and the third NMOS tube MN3 are sequentially connected in series with the first branch circuit between the positive power supply end VDD and the ground. In the on state of the fourth transistor, the current flows from the positive power supply terminal VDD to the ground through the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the first NMOS transistor MN1, and the third NMOS transistor MN 3.

The control ends of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to each other and both receive the bias voltage Vb1, the first ends of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the positive power supply end VDD, and the second ends of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are respectively connected to the first ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 to respectively receive two paths of differential current signals.

The second end of the fifth PMOS transistor MP5 is connected to the first end of the seventh PMOS transistor MP7, and the second end of the sixth PMOS transistor MP6 is connected to the first end of the eighth PMOS transistor MP 8. The control terminals of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to each other, and both receive the bias voltage Vb2.

The second end of the seventh PMOS transistor MP7 is connected to the first end of the first NMOS transistor MN1, and the second end of the eighth PMOS transistor MP8 is connected to the first end of the second NMOS transistor MN 2. The control ends of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected with each other, and the control ends of the first NMOS transistor and the second NMOS transistor receive the bias voltage Vb3. The first end of the second NMOS transistor MN2 is configured to output the differential amplified signal Vout.

In summary, the operational amplifier of the present invention includes a differential input circuit and a cascode amplifying circuit, where the differential input circuit includes a differential transistor pair, a cascode transistor pair, and an auxiliary operational amplifier circuit, the cascode transistor pair is connected to the differential transistor pair, and the auxiliary operational amplifier circuit clamps source-drain voltages of the differential transistor pair at a constant voltage value by controlling a control terminal voltage of the cascode transistor pair, so as to ensure that transconductance of the differential transistor pair does not change with a change of a common mode input voltage, and improve a common mode rejection ratio of the operational amplifier.

In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.

Claims

1. An operational amplifier comprising a differential input circuit and a cascode amplification circuit, wherein the differential input circuit comprises:

the differential input circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein the first PMOS tube and the second PMOS tube form a differential transistor pair, the first ends of the first PMOS tube and the second PMOS tube are connected with each other, and the control ends of the first PMOS tube and the second PMOS tube are used for inputting differential input signals;

the first ends of the third PMOS tube and the fourth PMOS tube are respectively connected to the second ends of the first PMOS tube and the second PMOS tube, the control ends of the third PMOS tube and the fourth PMOS tube are connected with each other, and the second ends of the third PMOS tube and the fourth PMOS tube respectively output two paths of differential current signals;

the first resistor and the second current source are sequentially connected between the first ends of the first PMOS tube and the second PMOS tube and the ground in series; and

the auxiliary operational amplifier circuit controls the control end voltages of the third PMOS tube and the fourth PMOS tube to enable a source-drain voltage clamp of the first PMOS tube and the second PMOS tube to be at a preset voltage,

and the middle node of the first resistor and the second current source is connected with the non-inverting input end of the auxiliary operational amplifier circuit to provide the preset voltage.

2. The operational amplifier of claim 1, wherein the auxiliary operational amplifier circuit comprises first and second inverting inputs, a non-inverting input, and an output,

a first inverting input end of the auxiliary operational amplifier circuit is connected with a second end of the first PMOS tube,

a second inverting input end of the auxiliary operational amplifier circuit is connected with a second end of the second PMOS tube,

the positive phase input end of the auxiliary operational amplifier circuit is used for receiving the preset voltage,

and the output end of the auxiliary operational amplifier circuit is connected with the control ends of the third PMOS tube and the fourth PMOS tube.

3. The operational amplifier of claim 2, further comprising a first current source having a first terminal connected to a positive power supply terminal and a second terminal connected to the first ends of the first and second PMOS transistors.

4. The operational amplifier of claim 1, wherein the cascode amplification circuit comprises:

the fifth PMOS tube, the seventh PMOS tube, the first NMOS tube and the third NMOS tube are connected between the positive power supply end and the ground in series; and

a sixth PMOS tube, an eighth PMOS tube, a second NMOS tube and a fourth NMOS tube which are connected in series between the positive power supply end and the ground,

wherein control ends of the fifth PMOS tube and the sixth PMOS tube are connected with each other and receive a first bias voltage,

the control ends of the seventh PMOS tube and the eighth PMOS tube are connected with each other and receive a second bias voltage,

the control ends of the first NMOS tube and the second NMOS tube are connected with each other and receive a third bias voltage,

the control ends of the third NMOS tube and the fourth NMOS tube are connected with each other and connected with the first end of the first NMOS tube,

the second ends of the first NMOS tube and the second NMOS tube are respectively connected to the second ends of the third PMOS tube and the fourth PMOS tube to receive the differential current signal, and the first end of the second NMOS tube is used for outputting a differential amplification signal.

5. An operational amplifier comprising a differential input circuit and a cascode amplification circuit, wherein the differential input circuit comprises:

the control ends of the fifth NMOS tube and the sixth NMOS tube are used for inputting differential input signals;

the second ends of the seventh NMOS tube and the eighth NMOS tube are respectively connected to the first ends of the fifth NMOS tube and the sixth NMOS tube, the control ends of the seventh NMOS tube and the eighth NMOS tube are connected with each other, and the first ends of the seventh NMOS tube and the eighth NMOS tube respectively output two paths of differential current signals;

the fourth current source and the second resistor are sequentially connected between the positive power supply end and the ground in series; and

the auxiliary operational amplifier circuit controls the control end voltage of the seventh NMOS tube and the control end voltage of the eighth NMOS tube to enable a source drain voltage clamp of the fifth NMOS tube and the sixth NMOS tube to be at a preset voltage,

and the middle node of the fourth current source and the second resistor is connected with the non-inverting input end of the auxiliary operational amplifier circuit to provide the preset voltage.

6. The operational amplifier of claim 5, wherein the auxiliary operational amplifier circuit comprises first and second inverting inputs, a non-inverting input, and an output,

a first inverting input end of the auxiliary operational amplifier circuit is connected with a first end of the fifth NMOS transistor,

a second inverting input end of the auxiliary operational amplifier circuit is connected with a first end of the sixth NMOS transistor,

and the output end of the auxiliary operational amplifier circuit is connected with the control ends of the seventh NMOS tube and the eighth NMOS tube.

7. The operational amplifier of claim 6, further comprising a third current source, wherein a first terminal of the third current source is connected to the second terminals of the fifth NMOS transistor and the sixth NMOS transistor, and wherein a second terminal of the third current source is connected to ground.

8. The operational amplifier of claim 5, wherein the cascode amplification circuit comprises:

a sixth PMOS tube, an eighth PMOS tube, a second NMOS tube and a fourth NMOS tube which are connected in series between the positive power supply terminal and the ground,

the control ends of the third NMOS transistor and the fourth NMOS transistor are connected with each other and connected with the first end of the first NMOS transistor,

the second ends of the fifth PMOS tube and the sixth PMOS tube are respectively connected to the first ends of the seventh NMOS tube and the eighth NMOS tube to receive the differential current signal, and the first end of the second NMOS tube is used for outputting a differential amplification signal.