CN116973618B - Current sampling circuit - Google Patents
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- CN116973618B CN116973618B CN202311237879.7A CN202311237879A CN116973618B CN 116973618 B CN116973618 B CN 116973618B CN 202311237879 A CN202311237879 A CN 202311237879A CN 116973618 B CN116973618 B CN 116973618B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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Abstract
The invention provides a current sampling circuit, comprising: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the sampling resistor. The invention can sample the current in positive and negative directions at the same time. In addition, the invention has rail-to-rail input range, namely, the wide input range sampling from the power supply to the ground can be realized.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a current sampling circuit.
Background
With the development of sensor systems, sampling circuits in integrated chips are increasingly used in various everyday scenarios. The sensor system converts the physical quantity into a voltage or current signal, then the chip samples the electrical signal, and finally outputs the electrical signal to the terminal.
Among the electrical signals, the voltage signal can be directly collected by the ADC, and the current signal needs to be sampled by the current first to convert the current outside the chip into a signal which can be directly perceived by the chip. The practical implementation methods are various, including sampling of off-chip devices and sampling of off-chip devices, the former has no extra loss, but the sampling precision is lower; the latter is generally to connect sampling resistor in series on the current path, calculate the electric current indirectly through the voltage difference of sampling resistor both ends, the precision is higher. FIG. 1 shows a simple off-chip resistor sampling method, and the main problem of the sampling circuit is that the negative current, i.e. the current I, cannot be sampled L In the case of the V2 node flowing to the V1 node, the sampling circuit cannot realize wide input range sampling from the power supply to the ground, and when V1 and V2 are in the region close to the power supply or the ground, the sampling current is distorted.
Therefore, how to optimize the sampling circuit, at least to solve one of the problems, is a focus of attention of the person skilled in the art.
Disclosure of Invention
The invention aims to provide a current sampling circuit which can sample current in positive and negative directions simultaneously.
In order to achieve the above object, the present invention provides a current sampling circuit including:
the first PMOS tube, the second PMOS tube, the third PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the sampling resistor;
the grid electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are commonly connected, and the source electrodes are connected to the reference ground; the grid electrode and the drain electrode of the first NMOS tube are short-circuited and connected with a power supply;
the gates of the first PMOS tube and the second PMOS tube are connected together, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second PMOS tube and the drain electrode of the third NMOS tube are connected and connected with the grid electrode of the third PMOS tube, and the source electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube;
the fourth resistor, the second resistor, the sampling resistor, the first resistor and the third resistor are sequentially connected between the source electrode of the second PMOS tube and the source electrode of the fifth NMOS tube; the source electrode of the first PMOS tube is connected between the first resistor and the third resistor;
the gates of the fifth NMOS tube and the sixth NMOS tube are connected together; the source electrode of the sixth NMOS tube is connected between the fourth resistor and the second resistor and is connected with the source electrode of the seventh NMOS tube;
the sources of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are all connected with a voltage input end; the gates of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are commonly connected, and the gate and the drain of the fifth PMOS tube are short and connected to the reference ground; the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is connected with the grid electrode of the seventh NMOS tube; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube;
the gates of the eighth PMOS tube and the ninth PMOS tube are connected together, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the seventh NMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrodes and the drain electrodes of the first PMOS tube, the sixth NMOS tube and the eighth PMOS tube are all short-circuited;
the current to be sampled flows through the sampling resistor, and the drain end of the third PMOS tube outputs the sampling current;
the sampling circuit further comprises a fourth PMOS tube, a fourth NMOS tube, a first amplifier and a second amplifier;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube;
the positive electrode input end of the first amplifier is connected with the drain electrode of the first PMOS tube, the negative electrode input end of the first amplifier is connected with the drain electrode of the third NMOS tube, and the output end of the first amplifier is connected with the grid electrode of the fourth NMOS tube;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube;
the positive electrode input end of the second amplifier is connected with the drain electrode of the seventh PMOS tube, the negative electrode input end of the second amplifier is connected with the drain electrode of the sixth PMOS tube, and the output end of the second amplifier is connected with the grid electrode of the fourth PMOS tube.
In an alternative scheme, the first PMOS transistor and the second PMOS transistor have the same size, and the second NMOS transistor and the third NMOS transistor have the same size.
In an alternative scheme, the fifth NMOS transistor and the sixth NMOS transistor have the same size, and the sixth PMOS transistor and the seventh PMOS transistor have the same size.
In an alternative scheme, the resistance values of the first resistor and the second resistor are the same, and the resistance values of the third resistor and the fourth resistor are the same.
The invention has the beneficial effects that:
the invention can sample positive and negative direction current at the same time, and can realize continuous sampling of wide input range from power supply to ground by using a rail-to-rail input range.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 is a circuit diagram of a sampling circuit in the prior art.
Fig. 2 is a circuit diagram of a sampling circuit according to an embodiment of the invention.
Fig. 3 is a circuit diagram in the dashed box in fig. 2.
Fig. 4 is a circuit diagram of the improvement of fig. 3.
Fig. 5 is a circuit diagram of a sampling circuit according to another embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
Referring to fig. 2, the present embodiment provides a current sampling circuit, including:
first PMOS tube M P1 A second PMOS tube M P2 Third PMOS tube M P3 Fifth PMOS tube M P5 Sixth PMOS tube M P6 Seventh PMOS tube M P7 Eighth PMOS tube M P8 Ninth PMOS tube M P9 First NMOS tube M N1 Second NMOS tube M N2 Third NMOS tube M N3 Fifth NMOS tube M N5 Sixth NMOS tube M N6 Seventh NMOS tube M N7 A first resistor R 1 A second resistor R 2 Third resistor R 3 Fourth resistor R 4 Sampling resistor R SNS ；
The first NMOS tube M N1 The second NMOS tube M N2 The third NMOS tube M N3 The grid electrodes of the three are commonly connected, and the source electrodes are connected with the ground GND; the gate and drain of the first NMOS transistor MN1 are short-circuited and connected to a power supply VDD, and the current flowing into the drain of the first NMOS transistor MN1 is I 1 ；
The first PMOS tube M P1 And the second PMOS tube M P2 The grid electrode of the first PMOS tube M is connected together P1 And the second NMOS tube M N2 Is connected with the drain electrode of the transistor; the second PMOS tube M P2 And the third NMOS tube M N3 The drain electrode of the third PMOS tube M is connected with and connected with P3 A gate of the third PMOS tube M P3 The source electrode of the transistor is connected with the first PMOS transistor M P1 A source of (a);
the second PMOS tube M P2 Source of (a) to the fifth NMOS transistor M N5 The sources of the fourth resistor R are connected in sequence 4 The second resistor R 2 The sampling resistor R SNS The first resistor R 1 And the third resistor R 3 The method comprises the steps of carrying out a first treatment on the surface of the The first PMOS tube M P1 Is connected to the first resistor R 1 And the third resistor R 3 Between them;
the fifth NMOS tube M N5 And the sixth NMOS tube M N6 Is connected with the grid electrode of the transistor; the sixth NMOS tube M N6 Is connected to the fourth resistor R 4 And the second resistor R 2 Is connected with the seventh NMOS tube M N7 A source of (a);
the fifth PMOS tube M P5 The sixth PMOS tube M P6 The seventh PMOS tube M P7 The eighth PMOS tube M P8 The ninth PMOS tube M P9 The sources of (a) are connected to a voltage input terminal (a system input voltage VIN); the fifth PMOS tube MP5 and the sixth PMOS tube M P6 The seventh PMOS tube M P7 The gates of the three are connected together, the fifth PMOS tube M P5 The gate and drain of (A) are short and connected to the reference ground, and flow into the fifth PMOS tube M P5 The current of the drain electrode is I2; the drain electrode of the sixth PMOS tube MP6 is connected to the drain electrode of the fifth NMOS tube MN5 and to the seventh NMOS tube M N7 A gate electrode of (a); the seventh PMOS tube M P7 Is connected to the drain of the sixth NMOS transistor M N6 A drain electrode of (2);
the eighth PMOS tube M P8 And the ninth PMOS tube M P9 The grid electrode of the eighth PMOS tube M is connected together P8 Is connected to the seventh NMOS transistor M N7 The drain electrode of the ninth PMOS tube M P9 The drain electrode of the third PMOS tube M is connected with P3 A drain electrode of (2);
the first PMOS tube M P1 The sixth NMOS tube M N6 And the eighth PMOS tube M P8 The grid electrode and the drain electrode of the transistor are short-circuited;
the current to be sampled flows through the sampling resistor R SNS The third PMOS tube M P3 Is used for outputting sampling current I at the drain terminal of (1) SNS 。
In this embodiment, the first PMOS tube M P1 A second PMOS tube M P2 Second NMOS tube M N2 Third NMOS tube M N3 Third PMOS tube M P3 Constitutes a common-gate input operational amplifier with an input range of VOV+VGS-VIN (VOV is the second NMOS transistor M N2 And a third NMOS tube M N3 Overdrive voltage of the composed circuit, VGS is MOS transistor gate-source voltage differenceWherein the first PMOS tube M P1 And a second PMOS tube M P2 The second NMOS tube M has the same size N2 And a third NMOS tube M N3 The sizes are the same; fifth NMOS tube M N5 Sixth NMOS tube M N6 Sixth PMOS tube M P6 Seventh PMOS tube M P7 Seventh NMOS tube M N7 Forms a common gate input operational amplifier with an input range of 0-VIN-VOV-VGS, wherein the fifth NMOS tube M N5 And a sixth NMOS tube M N6 The size is the same, the sixth PMOS tube M P6 And a seventh PMOS tube M P7 The dimensions are the same. The combination of the two op-amps achieves a rail-to-rail input range. I 1 =I 2 As the bias current of the two sampling op-amps.
When the current I needs to be sampled L Flow through sampling resistor R SNS At the time, the resistor R is sampled SNS The voltage difference between the voltages V1 and V2 at both ends is
R 1 =R 2 The resistance is consistent, under the clamping action of the two operational amplifiers, the current directions are opposite to counteractDifferential pressure such that v3=v4. The current on the first resistor R1 flows through the third PMOS tube M P3 Finally, the first part of sampling current I is converted SNS1 The method comprises the steps of carrying out a first treatment on the surface of the The current on the second resistor R2 flows through the seventh NMOS transistor M N7 And pass through an eighth PMOS tube M of the current mirror P8 And a ninth PMOS tube M P9 Conversion to a second partial sample current I SNS2 . First partial sample current I SNS1 And a second part of the sampling current I SNS2 Adding at the output end to obtain the final sampling current I SNS 。
Resistance value R 3 =R 4 As an offset resistor, the sampling circuit can work normally in negative current. Because of I 1 =I 2 So the third resistor R 3 And a fourth resistor R 4 The offset voltages brought are the same. When (when)At 0, V 3 And V 4 The voltage difference between them is
Consider an offset resistance (third resistance R 3 Or a fourth resistor R 4 ) The sampled output current is
Thus, the current I is sampled at negative current SNS There is still an output current. When I L <At 0, as long as-I L ×R 1 <I 1 ×R 3 The sampling circuit still belongs to the working state and does not stop working.
Example 2
Referring to fig. 3 and 4, in embodiment 1, the current sampling circuit is shown at V 3 And V 4 The operating point is easily in an abnormal state when it is near VTH, which is the threshold voltage of the MOG tube, as shown in fig. 3. With a first PMOS tube M P1 A second PMOS tube M P2 Second NMOS tube M N2 Third NMOS tube M N3 Third PMOS tube M P3 The operational amplifier is composed of, for example, V 3 And V 4 When about VTH, the second NMOS transistor M N2 First PMOS tube M short-circuited by grid and drain P1 Squeezing the drain-source voltage into a deep linear region, thereby forming a second NMOS transistor M N2 And a first PMOS tube M P1 Is much smaller than I 1 . Meanwhile, a third NMOS tube M N3 The drain voltage of the third NMOS transistor M is not squeezed N3 Is greater than the second NMOS tube M N2 Current (I) D2 <I D3 ) An unexpected offset is thus formed, resulting in a deviation of the last output sample current from the expected value.
In order to solve the above problems, referring to fig. 5, in this embodiment, the sampling circuit further includes a fourth PMOS transistor M P4 First, theFour NMOS tubes M N4 A first amplifier OP1 and a second amplifier OP2; the fourth NMOS tube M N4 Is connected to the third NMOS tube M N3 The drain electrode of the fourth NMOS tube M N4 The drain electrode of the second PMOS tube M is connected with P2 A drain electrode of (2); the positive input end of the first amplifier OP1 is connected to the drain electrode of the first PMOS tube MP1, and the negative input end is connected to the third NMOS tube M N3 The output end of the second NMOS transistor is connected with the drain electrode of the fourth NMOS transistor M N4 A gate electrode of (a); the fourth PMOS tube M P4 The source electrode of the transistor is connected with the sixth PMOS tube M P6 The drain electrode of the fourth PMOS tube M P4 Is connected with the drain electrode of the fifth NMOS tube M N5 A drain electrode of (2); the positive input end of the second amplifier OP2 is connected to the seventh PMOS tube M P7 The negative electrode input end is connected with the drain electrode of the sixth PMOS tube M P6 The output end of the transistor is connected with the drain electrode of the fourth PMOS tube M P4 Is formed on the substrate.
Referring to FIG. 4, the first amplifier OP1 is a P-pair common source stage input operational amplifier, and a fourth NMOS transistor M N4 Together, a current correction mechanism is formed when the second NMOS transistor M N2 Into the deep linear region, the first amplifier OP1 and the fourth NMOS tube M N4 Coaction to make the third NMOS transistor M N3 Also enter into the deep linear region, and the second NMOS transistor M N2 And a third NMOS tube M N3 Is approximately equal. At this time, the second NMOS transistor M N2 And a third NMOS tube M N3 Is much smaller than current I 1 . It should be noted that the second NMOS transistor M is ensured N2 And a third NMOS tube M N3 The total sampled output current is accurate. Because the higher gain of the upper and lower common-gate operational amplifiers plays the leading role, the second NMOS tube M N2 And a third NMOS tube M N3 Under the condition of small current, the common gate operational amplifier under the current is hardly operated. At this time, the second NMOS transistor M N2 And a third NMOS tube M N3 The current is smaller than the fifth NMOS tube M of the upper common-gate operational amplifier N5 And a sixth NMOS tube M N6 A fifth NMOS transistor M N5 And a sixth NMOS tube M N6 Excessive current flowing from the first resistor R 1 And a second resistor R 2 And the differential input voltage of the sampling resistor is not affected.
Second amplifier OP2 and fourth PMOS tube M P4 With a first amplifier OP1 and a fourth NMOS tube M N4 Similar efficacy is only when V 3 And V 4 And (c) VIN-VTH.
The invention can sample positive and negative direction current at the same time, and has rail-to-rail input range, namely, the continuous sampling of wide input range from power supply to ground can be realized. The sampling circuit can be manufactured by a semiconductor integrated process.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (4)
1. A current sampling circuit, comprising:
the first PMOS tube, the second PMOS tube, the third PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the sampling resistor;
the grid electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are commonly connected, and the source electrodes are connected to the reference ground; the grid electrode and the drain electrode of the first NMOS tube are short-circuited and connected with a power supply;
the gates of the first PMOS tube and the second PMOS tube are connected together, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second PMOS tube and the drain electrode of the third NMOS tube are connected and connected with the grid electrode of the third PMOS tube, and the source electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube;
the fourth resistor, the second resistor, the sampling resistor, the first resistor and the third resistor are sequentially connected between the source electrode of the second PMOS tube and the source electrode of the fifth NMOS tube; the source electrode of the first PMOS tube is connected between the first resistor and the third resistor;
the gates of the fifth NMOS tube and the sixth NMOS tube are connected together; the source electrode of the sixth NMOS tube is connected between the fourth resistor and the second resistor and is connected with the source electrode of the seventh NMOS tube;
the sources of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are all connected with a voltage input end; the gates of the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are commonly connected, and the gate and the drain of the fifth PMOS tube are short and connected to the reference ground; the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is connected with the grid electrode of the seventh NMOS tube; the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube;
the gates of the eighth PMOS tube and the ninth PMOS tube are connected together, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the seventh NMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrodes and the drain electrodes of the first PMOS tube, the sixth NMOS tube and the eighth PMOS tube are all short-circuited;
the current to be sampled flows through the sampling resistor, and the drain end of the third PMOS tube outputs the sampling current;
the sampling circuit further comprises a fourth PMOS tube, a fourth NMOS tube, a first amplifier and a second amplifier;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube;
the positive electrode input end of the first amplifier is connected with the drain electrode of the first PMOS tube, the negative electrode input end of the first amplifier is connected with the drain electrode of the third NMOS tube, and the output end of the first amplifier is connected with the grid electrode of the fourth NMOS tube;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube;
the positive electrode input end of the second amplifier is connected with the drain electrode of the seventh PMOS tube, the negative electrode input end of the second amplifier is connected with the drain electrode of the sixth PMOS tube, and the output end of the second amplifier is connected with the grid electrode of the fourth PMOS tube.
2. The current sampling circuit of claim 1 wherein said first PMOS transistor is the same size as said second PMOS transistor, and wherein said second NMOS transistor is the same size as said third NMOS transistor.
3. The current sampling circuit of claim 1 wherein said fifth NMOS transistor and said sixth NMOS transistor are the same size, and wherein said sixth PMOS transistor and said seventh PMOS transistor are the same size.
4. The current sampling circuit of claim 1 wherein the first resistor and the second resistor have the same resistance and the third resistor and the fourth resistor have the same resistance.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007071750A (en) * | 2005-09-08 | 2007-03-22 | Ntt Data Ex Techno Corp | Current measuring circuit |
| CN102426285A (en) * | 2011-09-14 | 2012-04-25 | 深圳航天科技创新研究院 | Current sensor used for bidirectional current sampling |
| CN103376346A (en) * | 2012-04-26 | 2013-10-30 | 比亚迪股份有限公司 | Low-side current detecting system |
| CN105486912A (en) * | 2015-12-22 | 2016-04-13 | 上海爱信诺航芯电子科技有限公司 | High precision rapid over-current detection circuit for low dropout regulator |
| CN107607770A (en) * | 2016-09-15 | 2018-01-19 | 成都芯源系统有限公司 | Current sampling circuit, switch circuit and current sampling method |
| CN107942120A (en) * | 2017-10-17 | 2018-04-20 | 深圳南云微电子有限公司 | Current detection circuit and electric current detecting method |
| CN109164867A (en) * | 2018-11-16 | 2019-01-08 | 西安电子科技大学 | Full MOS reference current generating circuit |
| CN110082584A (en) * | 2019-05-24 | 2019-08-02 | 深圳市思远半导体有限公司 | Low-voltage wide bandwidth high speed current sampling circuit |
| CN110632381A (en) * | 2019-11-12 | 2019-12-31 | 上海艾为电子技术股份有限公司 | Current detection circuit, chip and current detection method for loudspeaker protection |
| CN111273079A (en) * | 2018-12-04 | 2020-06-12 | 深圳市艾华迪技术有限公司 | Fluxgate direct current sensor circuit and method based on double-pulse width measurement |
| CN114252684A (en) * | 2021-12-28 | 2022-03-29 | 新际芯(北京)科技有限公司 | High-speed current sampling circuit based on buck converter |
| CN216160725U (en) * | 2021-09-15 | 2022-04-01 | 深圳和而泰智能控制股份有限公司 | Current sampling circuit and battery |
| CN114384304A (en) * | 2021-12-13 | 2022-04-22 | 宜矽源半导体南京有限公司 | High-voltage high-precision current sampling circuit |
| CN116087582A (en) * | 2023-04-07 | 2023-05-09 | 成都芯翼科技有限公司 | Voltage input side protection circuit, current detection amplifier and voltage detection amplifier |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102169381B1 (en) * | 2014-04-17 | 2020-10-23 | 삼성전자주식회사 | Dc-dc converter and electronic system comprising the same |
-
2023
- 2023-09-25 CN CN202311237879.7A patent/CN116973618B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007071750A (en) * | 2005-09-08 | 2007-03-22 | Ntt Data Ex Techno Corp | Current measuring circuit |
| CN102426285A (en) * | 2011-09-14 | 2012-04-25 | 深圳航天科技创新研究院 | Current sensor used for bidirectional current sampling |
| CN103376346A (en) * | 2012-04-26 | 2013-10-30 | 比亚迪股份有限公司 | Low-side current detecting system |
| CN105486912A (en) * | 2015-12-22 | 2016-04-13 | 上海爱信诺航芯电子科技有限公司 | High precision rapid over-current detection circuit for low dropout regulator |
| CN107607770A (en) * | 2016-09-15 | 2018-01-19 | 成都芯源系统有限公司 | Current sampling circuit, switch circuit and current sampling method |
| CN107942120A (en) * | 2017-10-17 | 2018-04-20 | 深圳南云微电子有限公司 | Current detection circuit and electric current detecting method |
| CN109164867A (en) * | 2018-11-16 | 2019-01-08 | 西安电子科技大学 | Full MOS reference current generating circuit |
| CN111273079A (en) * | 2018-12-04 | 2020-06-12 | 深圳市艾华迪技术有限公司 | Fluxgate direct current sensor circuit and method based on double-pulse width measurement |
| CN110082584A (en) * | 2019-05-24 | 2019-08-02 | 深圳市思远半导体有限公司 | Low-voltage wide bandwidth high speed current sampling circuit |
| CN110632381A (en) * | 2019-11-12 | 2019-12-31 | 上海艾为电子技术股份有限公司 | Current detection circuit, chip and current detection method for loudspeaker protection |
| CN216160725U (en) * | 2021-09-15 | 2022-04-01 | 深圳和而泰智能控制股份有限公司 | Current sampling circuit and battery |
| CN114384304A (en) * | 2021-12-13 | 2022-04-22 | 宜矽源半导体南京有限公司 | High-voltage high-precision current sampling circuit |
| CN114252684A (en) * | 2021-12-28 | 2022-03-29 | 新际芯(北京)科技有限公司 | High-speed current sampling circuit based on buck converter |
| CN116087582A (en) * | 2023-04-07 | 2023-05-09 | 成都芯翼科技有限公司 | Voltage input side protection circuit, current detection amplifier and voltage detection amplifier |
Non-Patent Citations (2)
| Title |
|---|
| 基于MOSFET导通电阻的无刷直流电机相电流采样技术研究;杨天 等;物联网技术(第3期);第44-47页 * |
| 电流模式开关电源中电流检测电路的分析与设计;俞德军 等;中国集成电路(第11期);第46-49页 * |
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| CN116973618A (en) | 2023-10-31 |
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