CN112821875B

CN112821875B - Amplifier circuit

Info

Publication number: CN112821875B
Application number: CN201911121883.0A
Authority: CN
Inventors: 刘三林; 刘志
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2024-05-31
Anticipated expiration: 2039-11-15
Also published as: CN112821875A

Abstract

The invention provides an amplifier circuit, and relates to the field of electronics. The amplifier circuit includes: the device comprises a folding cascode input module, a floating current source closed loop module, a bias circuit module and an output module; the folding cascode input module is used for providing an input signal for the amplifier circuit; the floating current source closed loop module is used for inhibiting output impedance from decreasing and controlling the quiescent current of the amplifier output stage circuit; the bias circuit module is used for providing bias voltage and controlling the quiescent current of the amplifier output stage circuit; the output module is used for outputting the current generated by the amplifier circuit. The amplifier circuit of the invention not only precisely controls the quiescent current of the output stage circuit, but also improves the output impedance of the differential input stage of the amplifier, and finally improves the gain and the power supply rejection ratio of the amplifier. The whole amplifier circuit has fewer components, lower cost, strong compatibility and high operation reliability, and greatly enriches the choice of using AB class amplifiers by users.

Description

Amplifier circuit

Technical Field

The invention relates to the field of electronics, in particular to an amplifier circuit.

Background

The operational amplifier is an important component of analog circuitry, and is used to construct circuits for various functions such as signal amplification, signal filtering, power amplification, etc., when the operational amplifier needs to drive a small resistor and a large capacitor, the output stage is usually biased in class a (class AB or class-AB), the quiescent current of the class AB amplifier is small, and a very large output current can be generated to the load, which has the advantages of high efficiency and small distortion. Typically high performance class AB amplifiers require very high gain and power supply rejection ratios.

At present, due to the characteristics of internal elements, the coordination of all elements of a circuit and the like, the output current of the AB amplifier cannot be controlled accurately, particularly, the control of the quiescent current of the output current is difficult to control accurately, when the working power supply voltage changes, the quiescent current of the output current changes greatly, so that the power supply rejection ratio of the AB amplifier is reduced, and the distortion degree of the AB amplifier is increased.

Disclosure of Invention

In view of the above, the present invention provides an amplifier circuit that solves the above-described problems.

An embodiment of the present invention provides an amplifier circuit including:

The device comprises a folding cascode input module, a floating current source closed loop module, a bias circuit module and an output module;

the folding cascode input module, the floating current source closed loop module, the bias circuit module and the output module are connected with each other;

The folded cascode input module is used for providing an input signal for the amplifier circuit;

the floating current source closed loop module is used for inhibiting the output impedance of the folding cascode input module from decreasing and controlling the quiescent current of an output stage circuit in the amplifier circuit together with the bias circuit module;

the bias circuit module is used for providing bias voltage for the floating current source closed-loop module and controlling the quiescent current of an output stage circuit in the amplifier circuit together with the floating current source closed-loop module;

the output module is used for outputting the current generated by the amplifier circuit and compensating the frequency characteristic of the amplifier circuit;

The bias circuit module provides bias voltage for the grid electrode of the transistor in the floating current source closed loop module so that the output stage of the amplifier circuit is biased in class A and class B, and the bias circuit module and the floating current source closed loop module jointly control the static current of the transistor in the output module so as to control the static current of the output stage circuit in the amplifier circuit.

Optionally, the folded cascode input module includes: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube;

the first NMOS tube and the second NMOS tube form an input stage differential input pair tube for receiving external signals;

The third NMOS tube, the fourth NMOS tube, the eighth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube form a common-source common-gate current mirror load of a differential input stage circuit in the amplifier circuit so as to generate output current of the differential input stage circuit in the amplifier circuit and control drain voltage of an MOS tube in the floating current source closed loop module;

the first PMOS tube and the second PMOS tube form an input stage current mirror;

the third PMOS tube and the fourth PMOS tube form an input stage common-source common-gate structure; the input stage current mirror and the input stage cascode structure cooperate to generate an output current of a differential input stage circuit in the amplifier circuit.

Optionally, the floating current source closed loop module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube;

The tenth NMOS tube and the eleventh NMOS tube form a feedback level differential input pair tube;

The seventh PMOS tube and the eighth PMOS tube form a feedback stage current mirror load, the feedback stage differential input pair tube and the feedback stage current mirror load act together to control the drain voltage of the ninth NMOS tube, so that the drain voltage of the ninth NMOS tube is equal to the grid voltage of the ninth NMOS tube.

Optionally, the bias circuit module includes: a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube;

The twelfth NMOS tube, the thirteenth NMOS tube and the fixed current source act together to provide bias voltage for the ninth NMOS tube, and meanwhile, the drain-source voltage of the ninth NMOS tube is equal to the drain-source voltage of the thirteenth NMOS tube;

the fourteenth NMOS tube, the ninth PMOS tube, the tenth PMOS tube and the fixed current source act together to provide bias voltage for the fifth PMOS tube, and meanwhile drain-source voltage of the fifth PMOS tube is equal to drain-source voltage of the tenth PMOS tube.

Optionally, the output module includes: a fifteenth NMOS tube, an eleventh PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

The drain electrodes of the fifteenth NMOS tube and the eleventh PMOS tube are the output end of the amplifier circuit;

the first resistor and the first capacitor form a miller compensation structure for providing frequency compensation for the amplifier circuit;

The second resistor and the second capacitor form a miller compensation structure for providing frequency compensation for the amplifier circuit.

Optionally, the drain voltage of the ninth NMOS transistor acts on the gate of the sixth PMOS transistor through the feedback-stage differential input pair transistor and the feedback-stage current mirror load, so as to control the drain voltage of the sixth PMOS transistor, so that the drain voltage of the ninth NMOS transistor is equal to the gate voltage.

Optionally, the width-to-length ratio of the fourth NMOS is M, the width-to-length ratio of the eighth NMOS is N, the width-to-length ratio of the third NMOS is m+n, and the current on the branch formed by the fourth NMOS and the sixth NMOS is equal to the sum of the currents flowing through the ninth NMOS and the fifth PMOS.

Optionally, the drain-source voltage of the ninth NMOS transistor is equal to the drain-source voltage of the thirteenth NMOS transistor;

The ninth NMOS tube and the thirteenth NMOS tube are of multi-interdigital structures, and each interdigital structure has the same size.

Optionally, the drain-source voltage of the fifth PMOS transistor is equal to the drain-source voltage of the tenth PMOS transistor;

the fifth PMOS tube and the tenth PMOS tube are all in multi-interdigital structures, and each interdigital has the same size.

Optionally, the current on the branch formed by the fourth NMOS and the sixth NMOS is equal to the sum of the currents flowing through the ninth NMOS and the fifth PMOS;

the current on a branch formed by the seventh NMOS tube and the eighth NMOS tube directly flows through the sixth PMOS tube so that the floating current source closed-loop module is kept stable;

the magnitude of the current flowing through the ninth NMOS transistor and the magnitude of the current flowing through the fifth PMOS transistor dynamically change with the change of the load current of the amplifier circuit.

The invention provides an amplifier circuit, which utilizes a floating current source closed loop module to inhibit the output impedance of a folding cascode input module from being reduced, and controls the quiescent current of an output stage circuit in the amplifier circuit together with a bias circuit module; and simultaneously, the bias circuit module is used for providing bias voltage for the floating current source closed-loop module, and the static current of the output stage circuit in the amplifier circuit is controlled together with the floating current source closed-loop module. The circuit not only accurately controls the quiescent current, but also improves the output impedance of the differential input stage circuit of the amplifier, finally improves the gain and the power supply rejection ratio of the amplifier, has fewer components and parts, is low in cost and high in compatibility, has high operation reliability, and greatly enriches the choices of using AB-class amplifiers by users.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a typical class AB amplifier;

FIG. 2 is a block diagram of an amplifier circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an amplifier circuit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a circuit configuration of an amplifier circuit with auxiliary amplifier Au according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a bias circuit module in an amplifier circuit according to an embodiment of the invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The inventor finds that the current control on the static current of the output current of the class AB amplifier is difficult to achieve accurate control, and even if the static current is slightly increased, the static current can cause the power supply rejection ratio of the class AB amplifier to be reduced, so that the distortion degree of the class AB amplifier is increased, and the inventor further finds that the main reason for generating the problems is as follows: the above problems are caused by the transistor itself characteristic factor controlling the output current in the class AB amplifier.

Referring to fig. 1, a schematic circuit diagram of a typical class AB amplifier is shown, and the class AB amplifier circuit is formed by a differential input stage circuit, a class-AB bias generating circuit and an output stage circuit, wherein the differential input stage circuit is in a folded cascode structure, the structure has high output impedance and voltage gain, NMOS transistors M1 and M2 form differential input pair transistors, IB1 provides bias current for the differential pair, and NMOS transistor M9 and PMOS transistor M10 form a floating current source for controlling quiescent current of the output stage. The Class-AB bias circuit includes stacked diode-connected NMOS transistors M22, M23 and stacked diode-connected PMOS transistors M24, M25, which provide bias voltages for the floating current source transistors M9 and M10, respectively. The output stage circuit includes PMOS transistor M21 and NMOS transistor M20, and resistor Rc and capacitor Cc form a miller compensation structure to provide frequency compensation for the amplifier circuit.

In the conventional class AB amplifier circuit described above, the current flowing through the NMOS transistors M22, M23 is the fixed current source IB2, ideally the NMOS transistors M22, M20 are matched, M23, M9 are matched, and they have the same gate-source voltage Vgs, so the current flowing through the NMOS transistor M20 of the output stage is n×ib2, where N is the ratio of the width to length of the NMOS transistor M20 to the NMOS transistor M22, and the current flowing through the PMOS transistor M21 has the same control principle as this. The control accuracy of the quiescent current of the output current depends on the matching between transistors M9/M23, M22/M20, M10/M25 and M24/M21. However, the drain-source voltages Vds of the transistors M9 and M23, and M10 and M25 are different, and due to the channel length modulation effect, the control of the output stage current is not accurate enough, and when the power supply voltage changes, the drain-source voltages VdsM and VdsM10 of the transistors M9 and M10 also change, thereby causing the quiescent current of the output stage circuit to change greatly, which reduces the power supply rejection ratio of the class AB amplifier, and increases the distortion degree of the class AB amplifier.

On the other hand, in some high-voltage CMOS processes, since the drain voltage of the NMOS transistor M9 of the floating current source structure is high, the leakage (Ibd) between its drain and its own substrate is large, so that the output impedance of the differential input stage in the class AB amplifier circuit is reduced, the gain of the class AB amplifier is reduced, and this leakage is changed with the change of the supply voltage, which also reduces the supply rejection ratio of the class AB amplifier.

Based on the above problems, the inventor has intensively studied, and has combined the characteristics of a differential input structure and a current mirror structure, through a large number of field tests and simulation calculations, the amplifier circuit of the invention is creatively provided, the above problems are solved, and the whole amplifier circuit has fewer added components, lower cost and strong compatibility. The solution proposed by the inventors is explained and illustrated in detail below.

Referring to fig. 2, a schematic block diagram of an amplifier circuit according to an embodiment of the present invention is shown, which may specifically include:

a folded cascode input module 20, a floating current source closed loop module 30, a bias circuit module 40, and an output module 50.

The folded cascode input module 20, the floating current source closed loop module 30, the bias circuit module 40, and the output module 50 are connected to each other. Wherein the folded cascode input module 20 is configured to provide an input signal for a class AB amplifier circuit; the floating current source closed loop module 30 is used for suppressing the output impedance of the folded cascode input module 20 from decreasing, and controlling the quiescent current of the current output by the class AB amplifier circuit together with the bias circuit module 40; the bias circuit module 40 provides bias voltages to the gates of the transistors in the floating current source closed loop module 30 to bias the output stage of the class AB amplifier circuit in class a, and the bias circuit module 40 and the floating current source closed loop module 30 together control the quiescent current of the transistors in the output module 50, thereby controlling the quiescent current of the output stage circuit in the class AB amplifier circuit; the output module 50 is used for outputting the current generated by the class AB amplifier circuit and compensating the frequency characteristic of the class AB amplifier circuit.

Optionally, referring to fig. 3, a schematic diagram of an amplifier circuit according to an embodiment of the present invention is shown, where Au in the floating current source closed loop module 30 refers to an auxiliary amplifier, which forms the floating current source closed loop module 30 together with other transistors, and the specific structure thereof is described in detail in the following correspondence; similarly, the class-AB bias generation circuit in fig. 3 refers to the bias circuit module 40 in the amplifier circuit according to the embodiment of the present invention, and the specific structure thereof is described in detail below.

Referring to fig. 3, a folded cascode input module 20 in an amplifier circuit according to an embodiment of the present invention includes: the first NMOS transistor 201, the second NMOS transistor 202, the third NMOS transistor 203, the fourth NMOS transistor 204, the fifth NMOS transistor 205, the sixth NMOS transistor 206, the seventh NMOS transistor 207, the eighth NMOS transistor 208, the first PMOS transistor 211, the second PMOS transistor 212, the third PMOS transistor 213, the fourth PMOS transistor 214, the first fixed bias voltage terminal 209, the first fixed current source 210, the second fixed bias voltage terminal 216, and the third fixed bias voltage terminal 215.

The grid electrode of the first NMOS tube 201 is connected with a first external signal input end, and a signal received by the first external signal input end is generated by an external device and needs to be processed by an AB class amplifier circuit; the source electrode of the first NMOS tube 201 is connected with the source electrode of the second NMOS tube 202 and the first fixed current source 210 respectively; the drain electrode of the first NMOS tube 201 is connected with the drain electrode of the first PMOS tube 211 and the source electrode of the third PMOS tube 213 respectively; the gate of the second NMOS transistor 202 is connected to the second external signal input, and similarly, the signal received by the second external signal input is also a signal generated by an external device and processed by the class AB amplifier circuit, and the two signals may be the same signal source, a reference signal, a signal to be processed, or another signal. The source electrode of the second NMOS tube 202 is respectively connected with the source electrode of the first NMOS tube 201 and the first fixed current source 210; the drain electrode of the second NMOS transistor 202 is connected to the drain electrode of the second PMOS transistor 212 and the source electrode of the fourth PMOS transistor 214, respectively, and the first NMOS transistor 201 and the second NMOS transistor 202 form a differential input pair of the input stage circuit of the class AB amplifier circuit, and are configured to receive an external signal, and further generate a differential current signal of the input stage according to the external signal.

The gate of the third NMOS tube 203 is connected with the gate of the fourth NMOS tube 204, the gate of the eighth NMOS tube 208, the drain of the fifth NMOS tube 205 and the drain of the third PMOS tube 213 respectively; the source electrode of the third NMOS tube 203 is grounded; the drain electrode of the third NMOS tube 203 is connected with the source electrode of the fifth NMOS tube 205; the gate of the fourth NMOS transistor 204 is connected to the gate of the third NMOS transistor 203, the gate of the eighth NMOS transistor 208, the drain of the fifth NMOS transistor 205, and the drain of the third PMOS transistor 213, respectively; the source of the fourth NMOS tube 204 is grounded; the drain of the fourth NMOS tube 204 is connected to the source of the sixth NMOS tube 206; the gate of the fifth NMOS transistor 205 is connected to the gate of the sixth NMOS transistor 206, the gate of the seventh NMOS transistor 207, and the first fixed bias voltage terminal 209, respectively; the source electrode of the fifth NMOS tube 205 is connected with the drain electrode of the third NMOS tube 203; the drain electrode of the fifth NMOS tube 205 is respectively connected with the gate electrode of the third NMOS tube 203, the gate electrode of the fourth NMOS tube 204, the gate electrode of the eighth NMOS tube 208 and the drain electrode of the third PMOS tube 213; the gate of the sixth NMOS transistor 206 is connected to the gate of the fifth NMOS transistor 205, the gate of the seventh NMOS transistor 207, and the first fixed bias voltage terminal 209, respectively; the source of the sixth NMOS tube 206 is connected to the drain of the fourth NMOS tube 204; the drain electrode of the sixth NMOS tube 206 is connected with the floating current source closed loop module 30 and the output module 50 respectively; the gate of the seventh NMOS transistor 207 is connected to the gate of the fifth NMOS transistor 205, the gate of the sixth NMOS transistor 206, and the first fixed bias voltage terminal 209, respectively; the source of the seventh NMOS tube 207 is connected with the drain of the eighth NMOS tube 208; the drain electrode of the seventh NMOS tube 207 is connected with the floating current source closed loop module 30; the gate of the eighth NMOS transistor 208 is connected to the gate of the third NMOS transistor 203, the gate of the fourth NMOS transistor 204, the drain of the fifth NMOS transistor 205, and the drain of the third PMOS transistor 213, respectively; the source of the eighth NMOS transistor 208 is grounded; the drain of the eighth NMOS transistor 208 is connected to the source of the seventh NMOS transistor 207.

The third NMOS tube 203, the fourth NMOS tube 204, the eighth NMOS tube 208, the fifth NMOS tube 205, the sixth NMOS tube 206 and the seventh NMOS tube 207 form a common-source common-gate current mirror load of an input stage circuit in the class AB amplifier circuit; the cascode current mirror load of the input stage receives the currents provided by the first NMOS transistor 201 and the second NMOS transistor 202, and generates an output current of the input stage circuit in the class AB amplifier circuit according to the currents, and at the same time, the cascode current mirror load of the input stage controls the drain voltage of the ninth NMOS transistor in the floating current source closed loop module 30.

The grid electrode of the first PMOS tube 211 is respectively connected with the grid electrode of the second PMOS tube 212 and the third fixed bias voltage end 215; the source electrode of the first PMOS tube 211 is respectively connected with the working power supply VDD, the source electrode of the second PMOS tube 212, the bias circuit module 40 and the output module 50; the drain electrode of the first PMOS tube 211 is connected with the drain electrode of the first NMOS tube 201 and the source electrode of the third PMOS tube 213 respectively; the grid electrode of the second PMOS tube 212 is respectively connected with the grid electrode of the first PMOS tube 211 and the third fixed bias voltage end 215; the source of the second PMOS transistor 212 is connected to the source of the first PMOS transistor 211, the operating power supply VDD, the bias circuit module 40, and the output module 50, respectively; the drain electrode of the second PMOS tube 212 is connected with the drain electrode of the second NMOS tube 202 and the source electrode of the fourth PMOS tube 214 respectively; the gate of the third PMOS transistor 213 is connected to the gate of the fourth PMOS transistor 214 and the second fixed bias voltage terminal 216, respectively; the source electrode of the third PMOS tube 213 is connected with the drain electrode of the first PMOS tube 211 and the drain electrode of the first NMOS tube 201 respectively; the drain electrode of the third PMOS transistor 213 is connected to the drain electrode of the fifth NMOS transistor 205, the gate electrode of the third NMOS transistor 203, the gate electrode of the fourth NMOS transistor 204, and the gate electrode of the eighth NMOS transistor 208, respectively; the gate of the fourth PMOS transistor 214 is connected to the gate of the third PMOS transistor 213 and the second fixed bias voltage terminal 216, respectively; the source of the fourth PMOS tube 214 is connected with the drain of the second PMOS tube 212 and the drain of the second NMOS tube 202 respectively; the drain of the fourth PMOS transistor 214 is connected to the floating current source closed loop module 40.

The first PMOS transistor 211 and the second PMOS transistor 212 form an input stage current mirror in the class AB amplifier circuit; the third PMOS tube 213 and the fourth PMOS tube 214 form an input stage common-source common-gate structure; the input stage current mirror and the input stage cascode structure receive the currents provided by the first NMOS transistor 201 and the second NMOS transistor 202, and generate, according to the currents and through the combined action, currents of two branches of the differential input stage circuit, where the currents of the two branches are processed to obtain output currents of the input stage circuit in the AB class amplifier circuit, and a principle of generating a current signal by the circuit of the portion is the same as a principle of generating a current by the same portion of the current AB class amplifier, which is not repeated herein for brevity of the specification. It should be noted that, a branch in the cascode current mirror of the input stage may control the drain voltage of the ninth NMOS transistor in the floating current source closed loop module 30, which will be described in detail in the following correspondence.

Optionally, referring to fig. 3, the floating current source closed loop module 30 includes: the circuit structure of the amplifier circuit with the auxiliary amplifier Au according to the embodiment of the invention is shown in fig. 4, which includes: tenth NMOS tube 310, eleventh NMOS tube 311, seventh PMOS tube 307, eighth PMOS tube 308, and third fixed current source 312. Note that, in fig. 4, the folded cascode input module 20, the bias circuit module 40, and the output module 50 are the same as components in the same modules in fig. 3, and for brevity of the drawing, the components are not specifically identified.

Referring to fig. 4, in combination with fig. 3, the gate of the ninth NMOS transistor 309 is connected to the gates of the bias circuit module 40 and the eleventh NMOS transistor 311, respectively; the source of the ninth NMOS transistor 309 is connected to the drain of the sixth NMOS transistor 206, the drain of the fifth PMOS transistor 305, and the output module 50, respectively; the drain electrode of the ninth NMOS tube 309 is connected with the drain electrode of the seventh NMOS tube 207, the drain electrode of the sixth PMOS tube 306 and the gate electrode of the tenth NMOS tube 310 respectively; the gate of the tenth NMOS tube 310 is connected to the drain of the ninth NMOS tube 309; the source of the tenth NMOS tube 310 is connected to the source of the eleventh NMOS tube 311 and the third constant current source 312, respectively; the drain electrode of the tenth NMOS tube 310 is connected with the drain electrode of the seventh PMOS tube 307, the gate electrode of the seventh PMOS tube 307 and the gate electrode of the eighth PMOS tube 308 respectively; the gate of the eleventh NMOS transistor 311 is connected to the gate of the ninth NMOS transistor 309; the source of the eleventh NMOS transistor 311 is connected to the source of the tenth NMOS transistor 310 and the third constant current source 312, respectively; the drain of the eleventh NMOS tube 311 is connected to the drain of the eighth PMOS tube 308 and the gate of the sixth PMOS tube 306, respectively.

The grid electrode of the fifth PMOS tube 305 is connected with the bias circuit module 40; the source of the fifth PMOS transistor 305 is connected to the drain of the fourth PMOS transistor 214, the source of the sixth PMOS transistor 306, and the output module 50, respectively; the drain electrode of the fifth PMOS transistor 305 is connected to the source electrode of the ninth NMOS transistor 309, the drain electrode of the sixth NMOS transistor 206, and the output module 50, respectively; the grid electrode of the sixth PMOS tube 306 is respectively connected with the drain electrode of the eleventh NMOS tube 311 and the drain electrode of the eighth PMOS tube 308; the source of the sixth PMOS transistor 306 is connected to the drain of the fourth PMOS transistor 214, the source of the fifth PMOS transistor 305, and the output module 50, respectively; the drain electrode of the sixth PMOS transistor 306 is connected to the drain electrode of the ninth NMOS transistor 309, the drain electrode of the seventh NMOS transistor 207, and the gate electrode of the tenth NMOS transistor 310, respectively; the grid electrode of the seventh PMOS tube 307 is respectively connected with the drain electrode of the seventh PMOS tube 307, the grid electrode of the eighth PMOS tube 308 and the drain electrode of the tenth NMOS tube 310; the source of the seventh PMOS transistor 307 is connected to the source of the eighth PMOS transistor 308, the source of the first PMOS transistor 211, and the source of the second PMOS transistor 212, respectively; the drain electrode of the seventh PMOS transistor 307 is connected to the gate electrode of itself, the gate electrode of the eighth PMOS transistor 308, and the drain electrode of the tenth NMOS transistor 310, respectively; the gate of the eighth PMOS transistor 308 is connected to the gate of the seventh PMOS transistor 307, the drain of the seventh PMOS transistor 307, and the drain of the tenth NMOS transistor 310, respectively; the source of the eighth PMOS transistor 308 is connected to the source of the seventh PMOS transistor 307, the source of the first PMOS transistor 211, and the source of the second PMOS transistor 212, respectively; the drain of the eighth PMOS transistor 308 is connected to the gate of the sixth PMOS transistor 306 and the drain of the eleventh NMOS transistor 311, respectively.

The tenth NMOS transistor 310 and the eleventh NMOS transistor 311 form a feedback-stage differential input pair, the seventh PMOS transistor 307 and the eighth PMOS transistor 308 form a feedback-stage current mirror load, and the feedback-stage differential input pair and the feedback-stage current mirror load act together to realize the function of one amplifier, so that the drain voltage of the ninth NMOS transistor 309 is controlled to make the drain voltage of the ninth NMOS transistor 309 equal to the gate voltage thereof.

The principle of the above action is: the drain voltage and the gate voltage of the ninth NMOS transistor 309 are respectively used as the voltage signals of the positive input end and the negative input end of the differential input pair transistor, meanwhile, the drain voltage of the sixth PMOS transistor 306 is also used as the voltage signal of the positive input end of the differential input pair transistor, if the drain voltage of the ninth NMOS transistor 309 is higher, the higher drain voltage will increase the current value on the branch formed by the tenth NMOS transistor 310 and the seventh PMOS transistor 307, the sum of the current values on the branch formed by the tenth NMOS transistor 310 and the seventh PMOS transistor 307 and the current value of the eleventh NMOS transistor 311 and the current value of the eighth PMOS transistor 308 is equal to the current value of the third fixed current source 312, then when the current value on the branch formed by the tenth NMOS transistor 310 and the seventh PMOS transistor 307 is increased, naturally, the current value on the branch formed by the eleventh NMOS transistor 311 and the eighth PMOS transistor 308 is decreased, the drain voltage reflected to the gate voltage of the sixth PMOS transistor 306 is naturally increased, and the drain voltage of the NMOS transistor 306 is also decreased, and the drain voltage of the NMOS transistor 309 is also decreased, and the drain voltage of the ninth NMOS transistor 309 is equal to the drain voltage of the ninth NMOS transistor 308, and the drain voltage of the ninth NMOS transistor 309 is decreased, and the drain voltage of the ninth NMOS transistor is equal to the drain voltage of the ninth NMOS transistor 308 is also decreased. Even if the working voltage VDD changes, the above structure can still ensure that the drain voltage of the ninth NMOS transistor 309 is equal to the gate voltage thereof, so as to avoid the drain voltage of the ninth NMOS transistor 309 from being too high, reduce the leakage (I _bd) between the drain terminal of the ninth NMOS transistor 309 and the substrate, and finally avoid the problems of reduced output impedance, reduced gain, and reduced power supply rejection ratio of the differential input stage circuit in the AB class amplifier circuit.

In the above process, the current flowing through the branch formed by the fourth NMOS transistor 204 and the sixth NMOS transistor 206 is equal to the sum of the current flowing through the ninth NMOS transistor 309 and the current flowing through the fifth PMOS transistor 305, and since the current flowing through the branch formed by the fourth NMOS transistor 204 and the sixth NMOS transistor 206, the distribution ratio between the ninth NMOS transistor 309 and the fifth PMOS transistor 305 varies with the load of the amplifier circuit, under some load conditions, the current flowing through the fifth PMOS transistor 305 increases, the current flowing through the ninth NMOS transistor 309 decreases, and under other conditions, the current flowing through the fifth PMOS transistor 305 decreases, and the current flowing through the ninth NMOS transistor 309 increases. When the load resistance driven by the amplifier circuit is smaller or the load current is larger, the currents flowing through the ninth NMOS tube 309 and the fifth PMOS tube 305 will be unbalanced, and in an extreme case, all the currents flowing through the branches formed by the fourth NMOS tube 204 and the sixth NMOS tube 206 flow through the fifth PMOS tube 305 but not through the ninth NMOS tube 309, that is, the current flowing through the ninth NMOS tube 309 is 0, in this case, the current flowing through the sixth PMOS tube 306 will become extremely small, the extremely small current of the sixth PMOS tube 306 will cause the whole floating current source closed loop module 30 to be unstable, and oscillation is generated, in order to solve the problem, the seventh NMOS tube 207 and the eighth NMOS tube 208 are added in the folded cascode input module 20, and the currents on the branches formed by the seventh NMOS tube 207 and the eighth NMOS tube 208 directly flow through the sixth PMOS tube 306, so that the current of the sixth PMOS tube 306 is not extremely small, that is, the stability of the floating current source closed loop module 30 is ensured. Of course, in order to keep the current balance of the two branches of the differential input stage in the folded cascode input module 20, it is necessary that the sum of the current values of the fourth NMOS transistor 204 and the eighth NMOS transistor 208 is equal to the current value of the third NMOS transistor 203, and if the aspect ratio of the fourth NMOS transistor 204 is M, the aspect ratio of the eighth NMOS transistor 208 is N, and the aspect ratio of the third NMOS transistor 203 is m+n, the aspect ratios of the fourth NMOS transistor 204, the eighth NMOS transistor 208, and the third NMOS transistor 203 are M: n: M+N.

Optionally, referring to fig. 5, a schematic circuit structure of a bias circuit module 40 in an amplifier circuit according to an embodiment of the present invention is shown, where the bias circuit module 40 includes: a twelfth NMOS transistor 412, a thirteenth NMOS transistor 413, a fourteenth NMOS transistor 414, a ninth PMOS transistor 409, a tenth PMOS transistor 410, a second constant current source 411, and a fourth constant current source 408; it should be noted that, in fig. 5, the folded cascode input module 20, the floating current source closed loop module 30, and the output module 50 are the same as the components in the same module in fig. 3, and the components thereof are not specifically identified for brevity of the drawing.

Referring to fig. 5, in combination with fig. 3, the gate of the twelfth NMOS transistor 412 is connected to the source of the thirteenth NMOS transistor 413 and the second fixed current source 411, respectively; the source of the twelfth NMOS transistor 412 is grounded; the drain of the twelfth NMOS transistor 412 is connected to the gate of the ninth NMOS transistor 309, the gate of the thirteenth NMOS transistor 413, the drain of the thirteenth NMOS transistor 413, and the fourth constant current source 408, respectively; the gate of the thirteenth NMOS transistor 413 is connected to the drain thereof, the gate of the ninth NMOS transistor 309, the drain of the twelfth NMOS transistor 412, and the fourth constant current source 408, respectively; the source of the thirteenth NMOS transistor 413 is connected to the gate of the twelfth NMOS transistor 412 and the second constant current source 411, respectively; the drain of the thirteenth NMOS transistor 413 is connected to the gate of the thirteenth NMOS transistor 309, the drain of the twelfth NMOS transistor 412, and the fourth constant current source 408, respectively.

The gate of the fourteenth NMOS transistor 414 is connected to the drain of the fourteenth NMOS transistor itself and the drain of the tenth PMOS transistor 410, respectively; the source of the fourteenth NMOS tube 414 is grounded; the drain electrode of the fourteenth NMOS tube 414 is connected with the grid electrode of the fourteenth NMOS tube and the drain electrode of the tenth PMOS tube 410 respectively; the grid electrode of the ninth PMOS tube 409 is respectively connected with the source electrode of the tenth PMOS tube 410 and the second fixed current source 411; the source of the ninth PMOS transistor 409 is connected to the source of the second PMOS transistor 212, the second fixed current source 411, the fourth fixed current source 408, and the output module 50, respectively; the drain electrode of the ninth PMOS transistor 409 is connected to the gate electrode of the fifth PMOS transistor 305, the gate electrode of the tenth PMOS transistor 410, and the second fixed current source 411, respectively; the gate of the tenth PMOS transistor 410 is connected to the drain of the ninth PMOS transistor 409, the gate of the fifth PMOS transistor 305, and the second fixed current source 411, respectively; the source of the tenth PMOS transistor 410 is connected to the gate of the ninth PMOS transistor 409 and the second fixed current source 411, respectively; the drain of the tenth PMOS transistor 410 is connected to the drain and gate of the fourteenth NMOS transistor 414, respectively.

Wherein, the twelfth NMOS transistor 412, the thirteenth NMOS transistor 413, the second fixed current source 411, and the fourth fixed current source 408 cooperate to provide the bias voltage for the ninth NMOS transistor 309, and simultaneously make the drain-source voltage of the ninth NMOS transistor 309 equal to the drain-source voltage of the thirteenth NMOS transistor 413; the fourteenth NMOS transistor 414, the ninth PMOS transistor 409, the tenth PMOS transistor 410, and the second constant current source 411 cooperate to provide the bias voltage for the fifth PMOS transistor 305, and simultaneously make the drain-source voltage of the fifth PMOS transistor 305 equal to the drain-source voltage of the tenth PMOS transistor 410.

Optionally, referring to fig. 3, the output module 50 includes: a fifteenth NMOS transistor 505, an eleventh PMOS transistor 506, a first resistor 502, a second resistor 504, a first capacitor 501, and a second capacitor 503.

The gate of the fifteenth NMOS transistor 505 is connected to the drain of the sixth NMOS transistor 206, the source of the ninth NMOS transistor 309, the drain of the fifth PMOS transistor 305, and the first end of the first capacitor 501, respectively; the source of the fifteenth NMOS transistor 505 is grounded; the drain electrode of the fifteenth NMOS tube 505 is respectively connected with the first end of the first resistor 502, the first end of the second resistor 504 and the drain electrode of the eleventh PMOS tube 506; the gate of the eleventh PMOS transistor 506 is connected to the drain of the fourth PMOS transistor 214, the source of the fifth PMOS transistor 305, the source of the sixth PMOS transistor 306, and the first end of the second capacitor 503, respectively; the source of the eleventh PMOS transistor 506 is connected to the source of the second PMOS transistor 212, the source of the ninth NMOS transistor 309, the second constant current source 411, the fourth constant current source 408, and the power supply VDD, respectively; the drain of the eleventh PMOS 506 is connected to the first end of the second resistor 504, the first end of the first resistor 502, and the drain of the fifteenth NMOS 505, respectively.

The first end of the first resistor 502 is connected with the drain electrode of the fifteenth NMOS tube 505, the drain electrode of the eleventh PMOS tube 506 and the first end of the second resistor 504 respectively; a second terminal of the first resistor 502 is connected to a second terminal of the first capacitor 501; the first end of the second resistor 504 is connected with the drain electrode of the fifteenth NMOS tube 505, the drain electrode of the eleventh PMOS tube 506 and the first end of the first resistor 502 respectively; a second terminal of the second resistor 504 is connected to a second terminal of the second capacitor 503.

The first end of the first capacitor 501 is connected to the gate of the fifteenth NMOS transistor 505, the drain of the sixth NMOS transistor 206, the source of the ninth NMOS transistor 309, and the drain of the fifth PMOS transistor 305, respectively; a second terminal of the first capacitor 501 is connected to a second terminal of the first resistor 502; the first end of the second capacitor 503 is connected to the gate of the eleventh PMOS transistor 506, the drain of the fourth PMOS transistor 214, the source of the fifth PMOS transistor 305, and the source of the sixth PMOS transistor 306, respectively; a second terminal of the second capacitor 503 is connected to a second terminal of the second resistor 504.

The drain electrodes of the fifteenth NMOS tube 505 and the eleventh PMOS tube 506 are the output ends of the amplifier circuit; the first resistor 502 and the first capacitor 501 form a miller compensation structure, and frequency compensation is provided for the output current of the amplifier circuit; the second resistor 504 and the second capacitor 503 form a miller compensation structure that provides frequency compensation for the amplifier circuit.

The principle of equalizing the drain-source voltage of the ninth NMOS transistor 309 and the drain-source voltage of the thirteenth NMOS transistor 413, and equalizing the drain-source voltage of the fifth PMOS transistor 305 and the drain-source voltage of the tenth PMOS transistor 410 is as follows: the current value of the fourth fixed current source 408 is set to be twice the current value of the second fixed current source 411, and since the sum of the current values flowing through the twelfth NMOS transistor 412 and the thirteenth NMOS transistor 413 is equal to the current value of the fourth fixed current source 408, the current values flowing through the twelfth NMOS transistor 412 and the thirteenth NMOS transistor 413 are both equal to the current value of the second fixed current source 411, as is known from the circuit configuration, the sum of the gate-source voltages of the ninth NMOS transistor 309 and the fifteenth NMOS transistor 505 is equal to the sum of the gate-source voltages of the twelfth NMOS transistor 412 and the thirteenth NMOS transistor 413, that is, V _gs9 (the gate-source voltage of the ninth NMOS transistor 309) +v _gs15 (the gate-source voltage of the fifteenth NMOS transistor 505) =v _gs12 (the gate-source voltage of the twelfth NMOS transistor 412) +v _gs13 (the gate-source voltage of the thirteenth NMOS transistor 413), the twelfth NMOS transistor 412 is set to match the fifteenth NMOS transistor 505, the ninth NMOS transistor 309 is matched with the thirteenth NMOS transistor 413, and the matching here refers to: the MOS transistors all adopt a multi-finger structure, and each finger has the same size, and V _gs9＝V_gs13,V_gs15＝V_gs12 is made by such a matching design, so that the current value flowing through the fifteenth NMOS transistor 505 is N times the current value flowing through the twelfth NMOS transistor 412, that is, the static current value of the output stage circuit in the amplifier circuit is: the current value of the second fixed current source 411 is N times, where N refers to the ratio of the number of fingers of the fifteenth NMOS transistor 505 to the twelfth NMOS transistor 412. Since the drain-source voltage of the thirteenth NMOS transistor 413 is equal to its own gate-source voltage, i.e., V _ds13 (drain-source voltage of the thirteenth NMOS transistor 413) =v _gs13 (gate-source voltage of the thirteenth NMOS transistor 413), while the drain-source voltage of the ninth NMOS transistor 309 is equal to its gate-source voltage, i.e., V _ds9 (drain-source voltage of the ninth NMOS transistor 309) =v _gs9 (gate-source voltage of the ninth NMOS transistor 309) due to the feedback loop in the aforementioned floating current source closed loop module 30, therefore, the drain-source voltage of the ninth NMOS transistor 309 is also equal to the drain-source voltage of the thirteenth NMOS transistor 413.

By adopting the circuit structure, the drain-source voltage of the ninth NMOS tube 309 is equal to the drain-source voltage of the thirteenth NMOS tube 413, so that the influence of the channel length modulation effect of the ninth NMOS tube 309 in the current AB type amplifier circuit is avoided, the control of the output current of the fifteenth NMOS tube 505 is more accurate, the drain-source voltage of the ninth NMOS tube 309 is still stable even if the power supply voltage changes, the purpose that the change amplitude of the static current under different power supply voltages is greatly reduced is achieved, and finally the power supply voltage inhibition ratio of the AB type amplifier is improved.

Similarly to the above, the sum of the gate-source voltages of the fifth PMOS transistor 305 and the eleventh PMOS transistor 506 is equal to the sum of the gate-source voltages of the ninth PMOS transistor 409 and the tenth PMOS transistor 410, i.e., V _gs5p (the gate-source voltage of the fifth PMOS transistor 305) +v _gs11p (the gate-source voltage of the eleventh PMOS transistor 506) =v _gs9p (the gate-source voltage of the ninth PMOS transistor 409) +v _gs10p (the gate-source voltage of the tenth PMOS transistor 410), and similarly, the ninth PMOS transistor 409 is provided to be matched with the eleventh PMOS transistor 506, and the fifth PMOS transistor 305 is provided to be matched with the tenth PMOS transistor 410, then the output current value flowing through the eleventh PMOS transistor 506 is N times the current value flowing through the ninth PMOS transistor 409, i.e., the static current value of the output stage circuit in the amplifier circuit is also: the current value of the second fixed current source 411 is N times, where N is the ratio of the number of fingers of the eleventh PMOS transistor 506 to the tenth PMOS transistor 410.

As can be derived from the circuit structure, the drain-source voltage V _ds5p =vdd (power supply voltage) -V _gs11p-V_gs15 of the fifth PMOS transistor 305, the drain-source voltage V _ds10p =vdd (power supply voltage) -V _gs9p-V_gs14 of the tenth PMOS transistor 410 (gate-source voltage of the fourteenth NMOS transistor 414), and the fourteenth NMOS transistor 414 is set to match with the fifteenth NMOS transistor 505, so that V _ds5p＝V_ds10p is obtained, that is, the drain-source voltage of the fifth PMOS transistor 305 is also equal to the drain-source voltage of the tenth PMOS transistor 410.

By adopting the circuit structure, the drain-source voltage of the fifth PMOS transistor 305 is equal to the drain-source voltage of the tenth PMOS transistor 410, so that the influence of the channel length modulation effect of the fifth PMOS transistor 305 in the current class AB amplifier circuit is avoided, the control of the output current of the eleventh PMOS transistor 506 is more accurate, the drain-source voltage of the fifth PMOS transistor 305 remains equal to the drain-source voltage of the tenth PMOS transistor 410 even if the power supply voltage changes, the purpose that the variation amplitude of the static current under different power supply voltages is greatly reduced is achieved, and finally the power supply voltage suppression ratio of the class AB amplifier is improved.

In view of the above, the amplifier circuit according to the embodiment of the present invention makes the drain-source voltage of the ninth NMOS 309 equal to the gate-source voltage thereof through the feedback loop in the floating current source closed loop module 30, so as to avoid the drain-source voltage of the ninth NMOS 309 from being too high, reduce the leakage (I _bd) between the drain terminal of the ninth NMOS 309 and the substrate, and finally avoid the problems of reduced output impedance, reduced gain, and reduced power supply rejection ratio of the differential input stage circuit in the class AB amplifier circuit; meanwhile, based on the matching of the twelfth NMOS tube 412 and the fifteenth NMOS tube 505 in the bias circuit module 40, the ninth NMOS tube 309 and the thirteenth NMOS tube 413, as the drain-source voltage of the ninth NMOS tube 309 is equal to the gate-source voltage thereof, the drain-source voltage of the ninth NMOS tube 309 is equal to the drain-source voltage of the thirteenth NMOS tube 413, the influence of the channel length modulation effect of the ninth NMOS tube 309 is eliminated, the purpose that the variation amplitude of the static current under different power supply voltages is greatly reduced is achieved, and finally the power supply voltage inhibition ratio of the AB amplifier is improved.

Similarly, according to the amplifier circuit of the embodiment of the invention, based on the matching of the ninth PMOS transistor 409 and the eleventh PMOS transistor 506, the fifth PMOS transistor 305 and the tenth PMOS transistor 410, and the matching of the fourteenth NMOS transistor 414 and the fifteenth NMOS transistor 505, the drain-source voltage of the fifth PMOS transistor 305 is equal to the drain-source voltage of the tenth PMOS transistor 410, so that the influence of the channel length modulation effect of the fifth PMOS transistor 305 is eliminated, the purpose of greatly reducing the variation amplitude of the quiescent current under different power supply voltages is achieved, and finally the power supply voltage suppression ratio of the class AB amplifier is improved.

In summary, in the use process of the amplifier circuit, the quiescent current of the output stage circuit is accurately controlled, the output impedance of the differential input stage circuit in the amplifier circuit is improved, and the gain and the power supply rejection ratio of the amplifier circuit are finally improved. The whole amplifier circuit has fewer components, lower cost, strong compatibility and high operation reliability, and greatly enriches the choice of using AB class amplifiers by users.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. An amplifier circuit, the amplifier circuit comprising:

the bias circuit module provides bias voltage for the grid electrodes of a fifth PMOS tube and a ninth NMOS tube in the floating current source closed-loop module so that the output stage of the amplifier circuit is biased in class A and class B, and the bias circuit module and the floating current source closed-loop module jointly control the static current of the transistor in the output module so as to control the static current of the output stage circuit in the amplifier circuit;

the floating current source closed loop module comprises: the ninth NMOS tube, the fifth PMOS tube, the sixth PMOS tube and the auxiliary amplifier;

the auxiliary amplifier controls the drain voltage of the ninth NMOS tube so that the drain voltage of the ninth NMOS tube is equal to the gate voltage of the ninth NMOS tube.

2. The amplifier circuit of claim 1, wherein the folded cascode input module comprises: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube;

3. The amplifier circuit of claim 2, wherein the floating current source closed loop module comprises: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube;

4. The amplifier circuit of claim 3 wherein the bias circuit module comprises: a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube;

5. The amplifier circuit of claim 4, wherein the output module comprises: a fifteenth NMOS tube, an eleventh PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

6. The amplifier circuit of claim 3 wherein the drain voltage of the ninth NMOS transistor acts on the gate of the sixth PMOS transistor through the feedback stage differential input pair and the feedback stage current mirror load to control the drain voltage of the sixth PMOS transistor such that the drain voltage of the ninth NMOS transistor is equal to the gate voltage.

7. The amplifier circuit of claim 4 wherein the fourth NMOS transistor has a width to length ratio of M, the eighth NMOS transistor has a width to length ratio of N, the third NMOS transistor has a width to length ratio of m+n, and the current on the branch formed by the fourth NMOS transistor and the sixth NMOS transistor is equal to the sum of the currents flowing through the ninth NMOS transistor and the fifth PMOS transistor.

8. The amplifier circuit of claim 4, wherein the drain-source voltage of the ninth NMOS transistor is equal to the drain-source voltage of the thirteenth NMOS transistor;

9. The amplifier circuit of claim 4, wherein the drain-source voltage of the fifth PMOS transistor is equal to the drain-source voltage of the tenth PMOS transistor;

10. The amplifier circuit of claim 4, wherein the current on the branch consisting of the fourth NMOS transistor and the sixth NMOS transistor is equal to the sum of the currents flowing through the ninth NMOS transistor and the fifth PMOS transistor;