CN112821875B - An amplifier circuit - Google Patents

Abstract

The present invention provides an amplifier circuit, which relates to the field of electronics. The amplifier circuit includes: a folded common source and common gate input module, a floating current source closed loop module, a bias circuit module and an output module; the folded common source and common gate input module is used to provide an input signal for the amplifier circuit; the floating current source closed loop module is used to suppress the reduction of output impedance and control the quiescent current of the amplifier output stage circuit; the bias circuit module is used to provide a bias voltage and control the quiescent current of the amplifier output stage circuit; the output module is used to output the current generated by the amplifier circuit. The amplifier circuit of the present invention not only accurately controls the quiescent current of the output stage circuit, but also improves the output impedance of the differential input stage of the amplifier, and finally improves the gain and power supply rejection ratio of the amplifier. The entire amplifier circuit has fewer components added, low cost, strong compatibility, high operating reliability, and greatly enriches the user's choice of using Class AB amplifiers.

Description

An amplifier circuit

Technical Field

The invention relates to the field of electronics, and in particular to an amplifier circuit.

Background technique

Operational amplifiers are an important part of analog circuit systems. They are used to construct circuits with various functions such as signal amplification, signal filtering, and power amplification. When an operational amplifier needs to drive small resistors and large capacitors, the output stage is usually biased in Class AB or class-AB. Class AB amplifiers have a small quiescent current and can generate a very large output current to the load. They have the advantages of high efficiency and low distortion. Generally, high-performance class AB amplifiers need to have high gain and power supply rejection ratio.

At present, due to the characteristics of internal components and the coordination of various circuit components, the output current control of class AB amplifiers cannot be very precise, especially the control of the quiescent current of the output current is difficult to achieve precise control. When the working power supply voltage changes, the quiescent current of the output current will change significantly, thereby reducing the power supply rejection ratio of the class AB amplifier and increasing the distortion of the class AB amplifier.

Summary of the invention

In view of the above problems, the present invention provides an amplifier circuit to solve the above problems.

An embodiment of the present invention provides an amplifier circuit, the amplifier circuit comprising:

Folded common source and common gate input module, floating current source closed loop module, bias circuit module and output module;

The folded cascode input module, the floating current source closed-loop module, the bias circuit module and the output module are connected to each other;

The folded cascode input module is used to provide an input signal for the amplifier circuit;

The floating current source closed-loop module is used to suppress the reduction of the output impedance of the folded cascode input module, and to control the static current of the output stage circuit in the amplifier circuit together with the bias circuit module;

The bias circuit module is used to provide a bias voltage for the floating current source closed-loop module, and to control the static current of the output stage circuit in the amplifier circuit together with the floating current source closed-loop module;

The output module is used to output the current generated by the amplifier circuit and compensate for the frequency characteristics of the amplifier circuit;

Among them, the bias circuit module provides a bias voltage for the gate of the transistor in the floating current source closed-loop module so that the output stage of the amplifier circuit is biased in Class AB, and the bias circuit module and the floating current source closed-loop module jointly control the quiescent current of the transistor in the output module, thereby controlling the quiescent current of the output stage circuit in the amplifier circuit.

Optionally, the folded cascode input module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, and a fourth PMOS tube;

The first NMOS transistor and the second NMOS transistor constitute an input-stage differential input pair of transistors for receiving external signals;

The third NMOS transistor, the fourth NMOS transistor, the eighth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the seventh NMOS transistor constitute a common-source and common-gate current mirror load of the differential input stage circuit in the amplifier circuit to generate an output current of the differential input stage circuit in the amplifier circuit and control the drain voltage of the MOS transistor in the floating current source closed-loop module;

The first PMOS tube and the second PMOS tube constitute an input-stage current mirror;

The third PMOS tube and the fourth PMOS tube form an input stage common source and common gate structure; the input stage current mirror and the input stage common source and common gate structure work together to generate an output current of the differential input stage circuit in the amplifier circuit.

Optionally, the floating current source closed-loop module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube;

The tenth NMOS tube and the eleventh NMOS tube constitute a feedback stage differential input pair of tubes;

The seventh PMOS tube and the eighth PMOS tube constitute a feedback-stage current mirror load, and the feedback-stage differential input pair tube and the feedback-stage current mirror load work together to control the drain voltage of the ninth NMOS tube so that the drain voltage of the ninth NMOS tube is equal to its own gate voltage.

Optionally, the bias circuit module includes: a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube;

The twelfth NMOS tube, the thirteenth NMOS tube and the fixed current source work together to provide a bias voltage for the ninth NMOS tube, and at the same time make the drain-source voltage of the ninth NMOS tube equal to the drain-source voltage of the thirteenth NMOS tube;

The fourteenth NMOS tube, the ninth PMOS tube, the tenth PMOS tube and the fixed current source work together to provide a bias voltage for the fifth PMOS tube, and at the same time make the drain-source voltage of the fifth PMOS tube equal to the drain-source voltage of the tenth PMOS tube.

Optionally, the output module includes: a fifteenth NMOS tube, an eleventh PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

The drains of the fifteenth NMOS tube and the eleventh PMOS tube are output ends of the amplifier circuit;

The first resistor and the first capacitor form a Miller compensation structure to provide frequency compensation for the amplifier circuit;

The second resistor and the second capacitor form a Miller compensation structure to provide frequency compensation for the amplifier circuit.

Optionally, the drain voltage of the ninth NMOS tube acts on the gate of the sixth PMOS tube through the feedback stage differential input pair and the feedback stage current mirror load, thereby controlling the drain voltage of the sixth PMOS tube so that the drain voltage of the ninth NMOS tube is equal to the gate voltage.

Optionally, the width-to-length ratio of the fourth NMOS tube is M, the width-to-length ratio of the eighth NMOS tube is N, the width-to-length ratio of the third NMOS tube is M+N, and the current on the branch formed by the fourth NMOS tube and the sixth NMOS tube is equal to the sum of the current flowing through the ninth NMOS tube and the current flowing through the fifth PMOS tube.

Optionally, the drain-source voltage of the ninth NMOS tube is equal to the drain-source voltage of the thirteenth NMOS tube;

The ninth NMOS tube and the thirteenth NMOS tube both adopt a multi-finger structure, and each finger has the same size.

Optionally, the drain-source voltage of the fifth PMOS tube is equal to the drain-source voltage of the tenth PMOS tube;

The fifth PMOS tube and the tenth PMOS tube both adopt a multi-finger structure, and each finger has the same size.

Optionally, the current on the branch formed by the fourth NMOS tube and the sixth NMOS tube is equal to the sum of the current flowing through the ninth NMOS tube and the current flowing through the fifth PMOS tube;

The current on the branch formed by the seventh NMOS tube and the eighth NMOS tube directly flows through the sixth PMOS tube to keep the floating current source closed-loop module stable;

The magnitude of the current flowing through the ninth NMOS tube and the magnitude of the current flowing through the fifth PMOS tube change dynamically with the change of the load current of the amplifier circuit.

The present invention provides an amplifier circuit, which uses a floating current source closed-loop module to suppress the reduction of the output impedance of a folded common source and common gate input module, and jointly controls the quiescent current of an output stage circuit in the amplifier circuit with a bias circuit module; at the same time, the bias circuit module is used to provide a bias voltage for the floating current source closed-loop module, and jointly controls the quiescent current of the output stage circuit in the amplifier circuit with the floating current source closed-loop module. This circuit not only accurately controls the quiescent current, but also improves the output impedance of the amplifier differential input stage circuit, and ultimately improves the gain and power supply rejection ratio of the amplifier. The entire amplifier circuit has fewer components added, has a low cost, is highly compatible, and has high operating reliability, which greatly enriches the user's choice of using a class AB amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

FIG1 is a circuit diagram of a typical class AB amplifier;

FIG2 is a schematic diagram of a module of an amplifier circuit according to an embodiment of the present invention;

FIG3 is a schematic diagram of an amplifier circuit according to an embodiment of the present invention;

4 is a schematic diagram of the circuit structure of an amplifier circuit with an auxiliary amplifier Au according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the circuit structure of a bias circuit module in an amplifier circuit according to an embodiment of the present invention.

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

The inventors have found that it is currently difficult to accurately control the quiescent current of the output current of a class AB amplifier, and even a small increase in the quiescent current will cause the power supply rejection ratio of the class AB amplifier to decrease, thereby increasing the distortion of the class AB amplifier. The inventors have further found that the main reason for the above problem is that the characteristics of the transistors that control the output current in the class AB amplifier themselves lead to the above problem.

Referring to FIG1 , a circuit diagram of a typical class AB amplifier is shown. The class AB amplifier circuit is composed of a differential input stage circuit, a class-AB bias generating circuit and an output stage circuit, wherein the differential input stage circuit is a folded common source and common gate structure, which has a high output impedance and voltage gain, NMOS transistors M1 and M2 constitute a differential input pair, IB1 provides a bias current for the differential pair, and NMOS transistor M9 and PMOS transistor M10 constitute a floating current source for controlling the static current of the output stage. The class-AB bias circuit includes NMOS transistors M22 and M23 in a stacked diode connection and PMOS transistors M24 and M25 in a stacked diode connection, which provide bias voltages for floating current source transistors M9 and M10, respectively. The output stage circuit includes a PMOS transistor M21 and an NMOS transistor M20, and a resistor Rc and a capacitor Cc constitute a Miller compensation structure to provide frequency compensation for the amplifier circuit.

In the above-mentioned conventional class AB amplifier circuit, the current flowing through the NMOS transistors M22 and M23 is a fixed current source IB2. Ideally, the NMOS transistors M22 and M20 are matched, and M23 and M9 are matched. They have the same gate-source voltage Vgs, so the current flowing through the output stage NMOS transistor M20 is N*IB2, where N is the ratio of the width-to-length ratio of M20 to M22. The current flowing through the PMOS transistor M21 has the same control principle. The control accuracy of the static current of the output current depends on the matching between the transistors M9/M23, M22/M20, M10/M25 and M24/M21. However, the drain-source voltages Vds of transistors M9 and M23, and M10 and M25 are different. Due to the channel length modulation effect, the control of the output stage current is not precise enough. When the power supply voltage changes, the drain-source voltages VdsM9 and VdsM10 of M9 and M10 also change, causing a large change in the quiescent current of the output stage circuit, which reduces the power supply rejection ratio of the class AB amplifier and increases the distortion of the class AB amplifier.

On the other hand, in some high-voltage CMOS processes, since the drain voltage of the NMOS transistor M9 in the floating current source structure is relatively high, the leakage current (Ibd) between its drain terminal and its own substrate is relatively large, thereby reducing the output impedance of the differential input stage in the class AB amplifier circuit and the gain of the class AB amplifier. In addition, this leakage current varies with the power supply voltage, which also reduces the power supply rejection ratio of the class AB amplifier.

Based on the above problems, the inventors have conducted in-depth research, combined the characteristics of the differential input structure and the current mirror structure, and after a large number of field tests and simulation calculations, boldly and creatively proposed the amplifier circuit of the present invention, which solves the above problems. In addition, the entire amplifier circuit has fewer components, lower costs, and strong compatibility. The solution proposed by the inventors is explained and illustrated in detail below.

2 , a schematic diagram of a module of an amplifier circuit according to an embodiment of the present invention is shown, which may specifically include:

The folded cascode input module 20 , the floating current source closed-loop module 30 , the bias circuit module 40 and the output module 50 .

The folded cascode input module 20, the floating current source closed-loop module 30, the bias circuit module 40 and the output module 50 are connected to each other. The folded cascode input module 20 is used to provide an input signal for the class AB amplifier circuit; the floating current source closed-loop module 30 is used to suppress the reduction of the output impedance of the folded cascode input module 20, and to control the static current of the current output by the class AB amplifier circuit together with the bias circuit module 40; the bias circuit module 40 provides a bias voltage for the gate of the transistor in the floating current source closed-loop module 30, so that the output stage of the class AB amplifier circuit is biased in class AB, and the bias circuit module 40 and the floating current source closed-loop module 30 jointly control the static current of the transistor in the output module 50, thereby controlling the static current of the output stage circuit in the class AB amplifier circuit; the output module 50 is used to output the current generated by the class AB amplifier circuit and compensate for the frequency characteristics of the class AB amplifier circuit.

Optionally, referring to Figure 3, a schematic diagram of an amplifier circuit of an embodiment of the present invention is shown, wherein Au in the floating current source closed-loop module 30 refers to an auxiliary amplifier, which together with other transistors constitute the floating current source closed-loop module 30, and its specific structure is described in detail at the corresponding place below; similarly, the class-AB bias generating circuit in Figure 3 refers to the bias circuit module 40 in the amplifier circuit of the embodiment of the present invention, and its specific structure is described in detail at the corresponding place below.

3 , the folded common-source input module 20 in the amplifier circuit of the embodiment of the present invention includes: a first NMOS tube 201, a second NMOS tube 202, a third NMOS tube 203, a fourth NMOS tube 204, a fifth NMOS tube 205, a sixth NMOS tube 206, a seventh NMOS tube 207, an eighth NMOS tube 208, a first PMOS tube 211, a second PMOS tube 212, a third PMOS tube 213, a fourth PMOS tube 214, a first fixed bias voltage terminal 209, a first fixed current source 210, a second fixed bias voltage terminal 216 and a third fixed bias voltage terminal 215.

The gate of the first NMOS tube 201 is connected to the first external signal input terminal. The signal received by the first external signal input terminal is generated by an external device and needs to be processed by a class AB amplifier circuit; the source of the first NMOS tube 201 is connected to the source of the second NMOS tube 202 and the first fixed current source 210 respectively; the drain of the first NMOS tube 201 is connected to the drain of the first PMOS tube 211 and the source of the third PMOS tube 213 respectively; the gate of the second NMOS tube 202 is connected to the second external signal input terminal. Similarly, the signal received by the second external signal input terminal is also generated by an external device and needs to be processed by a class AB amplifier circuit. The two signals can be from the same signal source, or can be a reference signal, a signal to be processed, or other forms of signals. The embodiment of the present invention does not impose any limitation on this. The source of the second NMOS tube 202 is connected to the source of the first NMOS tube 201 and the first fixed current source 210 respectively; the drain of the second NMOS tube 202 is connected to the drain of the second PMOS tube 212 and the source of the fourth PMOS tube 214 respectively. The first NMOS tube 201 and the second NMOS tube 202 constitute a differential input pair of tubes of the input stage circuit of the class AB amplifier circuit, which are used to receive external signals and then generate differential current signals of the input stage according to the external signals.

The gate of the third NMOS tube 203 is connected to the gate of the fourth NMOS tube 204, the gate of the eighth NMOS tube 208, the drain of the fifth NMOS tube 205 and the drain of the third PMOS tube 213 respectively; the source of the third NMOS tube 203 is grounded; the drain of the third NMOS tube 203 is connected to the source of the fifth NMOS tube 205; the gate of the fourth NMOS tube 204 is connected to the gate of the third NMOS tube 203, the gate of the eighth NMOS tube 208, the drain of the fifth NMOS tube 205 and the drain of the third PMOS tube 213 respectively. The source of the fourth NMOS tube 204 is grounded; the drain of the fourth NMOS tube 204 is connected to the source of the sixth NMOS tube 206; the gate of the fifth NMOS tube 205 is connected to the gate of the sixth NMOS tube 206, the gate of the seventh NMOS tube 207 and the first fixed bias voltage terminal 209 respectively; the source of the fifth NMOS tube 205 is connected to the drain of the third NMOS tube 203; the drain of the fifth NMOS tube 205 is connected to the gate of the third NMOS tube 203, the gate of the fourth NMOS tube 204, the gate of the eighth NMOS tube 208 The gate of the sixth NMOS tube 206 is connected to the gate of the fifth NMOS tube 205, the gate of the seventh NMOS tube 207 and the first fixed bias voltage terminal 209 respectively; the source of the sixth NMOS tube 206 is connected to the drain of the fourth NMOS tube 204; the drain of the sixth NMOS tube 206 is connected to the floating current source closed-loop module 30 and the output module 50 respectively; the gate of the seventh NMOS tube 207 is connected to the gate of the fifth NMOS tube 205, the gate of the sixth NMOS tube 206 and the first fixed bias voltage terminal 209 respectively. The fixed bias voltage terminal 209 is connected respectively; the source of the seventh NMOS tube 207 is connected to the drain of the eighth NMOS tube 208; the drain of the seventh NMOS tube 207 is connected to the floating current source closed-loop module 30; the gate of the eighth NMOS tube 208 is connected to the gate of the third NMOS tube 203, the gate of the fourth NMOS tube 204, the drain of the fifth NMOS tube 205 and the drain of the third PMOS tube 213 respectively; the source of the eighth NMOS tube 208 is grounded; the drain of the eighth NMOS tube 208 is connected to the source of the seventh NMOS tube 207.

The third NMOS tube 203, the fourth NMOS tube 204, the eighth NMOS tube 208, the fifth NMOS tube 205, the sixth NMOS tube 206, and the seventh NMOS tube 207 constitute a common-source and common-gate current mirror load of the input stage circuit in the class AB amplifier circuit; the common-source and common-gate current mirror load of the input stage and the current provided by the first NMOS tube 201 and the second NMOS tube 202 are received, and the output current of the input stage circuit in the class AB amplifier circuit is generated according to the current. At the same time, the common-source and common-gate current mirror load of the input stage controls the drain voltage of the ninth NMOS tube in the floating current source closed-loop module 30.

The gate of the first PMOS tube 211 is connected to the gate of the second PMOS tube 212 and the third fixed bias voltage terminal 215 respectively; the source of the first PMOS tube 211 is connected to the working power supply VDD, the source of the second PMOS tube 212, the bias circuit module 40 and the output module 50 respectively; the drain of the first PMOS tube 211 is connected to the drain of the first NMOS tube 201 and the source of the third PMOS tube 213 respectively; the gate of the second PMOS tube 212 is connected to the gate of the first PMOS tube 211 and the third fixed bias voltage terminal 215 respectively; the source of the second PMOS tube 212 is connected to the source of the first PMOS tube 211, the working power supply VDD, the bias circuit module 40 and the output module 50 respectively; the drain of the second PMOS tube 212 is connected to the drain of the second NMOS tube 202 and the drain of the fourth PMOS tube 214 The gate of the third PMOS tube 213 is connected to the gate of the fourth PMOS tube 214 and the second fixed bias voltage terminal 216 respectively; the source of the third PMOS tube 213 is connected to the drain of the first PMOS tube 211 and the drain of the first NMOS tube 201 respectively; the drain of the third PMOS tube 213 is connected to the drain of the fifth NMOS tube 205, the gate of the third NMOS tube 203, the gate of the fourth NMOS tube 204 and the gate of the eighth NMOS tube 208 respectively; the gate of the fourth PMOS tube 214 is connected to the gate of the third PMOS tube 213 and the second fixed bias voltage terminal 216 respectively; the source of the fourth PMOS tube 214 is connected to the drain of the second PMOS tube 212 and the drain of the second NMOS tube 202 respectively; the drain of the fourth PMOS tube 214 is connected to the floating current source closed-loop module 40.

Among them, the first PMOS tube 211 and the second PMOS tube 212 constitute an input stage current mirror in the class AB amplifier circuit; the third PMOS tube 213 and the fourth PMOS tube 214 constitute an input stage cascode structure; the above-mentioned input stage current mirror and input stage cascode structure receive the current provided by the first NMOS tube 201 and the second NMOS tube 202, and generate the current of the two branches of the differential input stage circuit according to the current and through the joint action, and the current of the two branches is processed to obtain the output current of the input stage circuit in the class AB amplifier circuit. The principle of generating the current signal of this part of the circuit is the same as the principle of generating the current of the same part of the current class AB amplifier, and for the sake of brevity of the specification, it is not repeated here. It should be noted that a branch in the cascode current mirror of the input stage can control the drain voltage of the ninth NMOS tube in the floating current source closed-loop module 30, which will be specifically described in the corresponding part below.

Optionally, referring to FIG3 , the floating current source closed-loop module 30 includes: a ninth NMOS tube 309, a fifth PMOS tube 305, a sixth PMOS tube 306 and an auxiliary amplifier Au, wherein the circuit structure diagram of the amplifier circuit with the auxiliary amplifier Au in the embodiment of the present invention is shown in FIG4 , which includes: a tenth NMOS tube 310, an eleventh NMOS tube 311, a seventh PMOS tube 307, an eighth PMOS tube 308 and a third fixed current source 312. It should be noted that the components of the folded common source and common gate input module 20, the bias circuit module 40 and the output module 50 in FIG4 are the same as those in the same module in FIG3 , and for the sake of simplicity of the drawing, the components are not specifically identified.

4, in combination with FIG. 3, the gate of the ninth NMOS tube 309 is connected to the bias circuit module 40 and the gate of the eleventh NMOS tube 311 respectively; the source of the ninth NMOS tube 309 is connected to the drain of the sixth NMOS tube 206, the drain of the fifth PMOS tube 305 and the output module 50 respectively; the drain of the ninth NMOS tube 309 is connected to the drain of the seventh NMOS tube 207, the drain of the sixth PMOS tube 306 and the gate of the tenth NMOS tube 310 respectively; the gate of the tenth NMOS tube 310 is connected to the drain of the ninth NMOS tube 309; the source of the tenth NMOS tube 310 is connected to the drain of the seventh NMOS tube 207, the drain of the sixth PMOS tube 306 and the gate of the tenth NMOS tube 310 respectively; The source of the eleventh NMOS tube 311 is connected to the third fixed current source 312 respectively; the drain of the tenth NMOS tube 310 is connected to the drain of the seventh PMOS tube 307, the gate of the seventh PMOS tube 307 and the gate of the eighth PMOS tube 308 respectively; the gate of the eleventh NMOS tube 311 is connected to the gate of the ninth NMOS tube 309; the source of the eleventh NMOS tube 311 is connected to the source of the tenth NMOS tube 310 and the third fixed current source 312 respectively; the drain of the eleventh NMOS tube 311 is connected to the drain of the eighth PMOS tube 308 and the gate of the sixth PMOS tube 306 respectively.

The gate of the fifth PMOS tube 305 is connected to the bias circuit module 40; the source of the fifth PMOS tube 305 is connected to the drain of the fourth PMOS tube 214, the source of the sixth PMOS tube 306 and the output module 50 respectively; the drain of the fifth PMOS tube 305 is connected to the source of the ninth NMOS tube 309, the drain of the sixth NMOS tube 206 and the output module 50 respectively; the gate of the sixth PMOS tube 306 is connected to the drain of the eleventh NMOS tube 311 and the drain of the eighth PMOS tube 308 respectively; the source of the sixth PMOS tube 306 is connected to the drain of the fourth PMOS tube 214, the source of the fifth PMOS tube 305 and the output module 50 respectively; the drain of the sixth PMOS tube 306 is connected to the drain of the ninth NMOS tube 309, the drain of the seventh NMOS tube 207 and the gate of the tenth NMOS tube 310 respectively; the gate of the seventh PMOS tube 307 is connected to its own drain, The gate of the eighth PMOS tube 308 and the drain of the tenth NMOS tube 310 are connected respectively; the source of the seventh PMOS tube 307 is connected respectively to the source of the eighth PMOS tube 308, the source of the first PMOS tube 211 and the source of the second PMOS tube 212; the drain of the seventh PMOS tube 307 is connected respectively to its own gate, the gate of the eighth PMOS tube 308 and the drain of the tenth NMOS tube 310; the gate of the eighth PMOS tube 308 is connected respectively to the gate of the seventh PMOS tube 307, the drain of the seventh PMOS tube 307 and the drain of the tenth NMOS tube 310; the source of the eighth PMOS tube 308 is connected respectively to the source of the seventh PMOS tube 307, the source of the first PMOS tube 211 and the source of the second PMOS tube 212; the drain of the eighth PMOS tube 308 is connected respectively to the gate of the sixth PMOS tube 306 and the drain of the eleventh NMOS tube 311.

Among them, the tenth NMOS tube 310 and the eleventh NMOS tube 311 constitute a feedback-stage differential input pair tube, the seventh PMOS tube 307 and the eighth PMOS tube 308 constitute a feedback-stage current mirror load, and the above-mentioned feedback-stage differential input pair tube and the feedback-stage current mirror load work together to achieve the function of an amplifier, so as to control the drain voltage of the ninth NMOS tube 309 so that the drain voltage of the ninth NMOS tube 309 is equal to its own gate voltage.

The principle of the above-mentioned action is: the drain voltage and gate voltage of the ninth NMOS tube 309 are used as voltage signals of the positive and negative input terminals of the differential input pair, respectively. Meanwhile, the drain voltage of the sixth PMOS tube 306 is also used as the voltage signal of the positive input terminal of the differential input pair. If the drain voltage of the ninth NMOS tube 309 is higher, the higher drain voltage will increase the current value of the branch composed of the tenth NMOS tube 310 and the seventh PMOS tube 307. Since the sum of the current value of the branch composed of the tenth NMOS tube 310 and the seventh PMOS tube 307 and the current value of the branch composed of the eleventh NMOS tube 311 and the eighth PMOS tube 308 is equal to the current value of the third fixed current source 312, when the current value of the branch composed of the tenth NMOS tube 310 and the seventh PMOS tube 307 increases, naturally, the current value of the eleventh NMOS tube 311 and the eighth PMOS tube 308 increases. The current value on the branch composed of the tenth NMOS tube 310 and the seventh PMOS tube 307 is reduced, which is reflected in the increase of the gate voltage of the sixth PMOS tube 306. Naturally, the drain voltage of the sixth PMOS tube 306 will also decrease, and the drain voltage of the sixth PMOS tube 306 is the same as the drain voltage of the ninth NMOS tube 309. Therefore, the drain voltage of the ninth NMOS tube 309 is also reduced. The reduced drain voltage will reduce the current value on the branch composed of the tenth NMOS tube 310 and the seventh PMOS tube 307, and finally reach a current value equal to the current value on the branch composed of the eleventh NMOS tube 311 and the eighth PMOS tube 308. Since the gate voltage of the ninth NMOS tube 309 controls the current value on the branch composed of the eleventh NMOS tube 311 and the eighth PMOS tube 308, through such a feedback structure, the drain voltage of the ninth NMOS tube 309 is finally equal to its own gate voltage. Even if the operating voltage VDD changes, the above structure can still ensure that the drain voltage of the ninth NMOS tube 309 is equal to its own gate voltage, thereby avoiding the drain voltage of the ninth NMOS tube 309 being too high, reducing the leakage current (I _bd ) between the drain end of the ninth NMOS tube 309 and the substrate, and ultimately avoiding the problems of reduced output impedance, reduced gain, and reduced power supply rejection ratio of the differential input stage circuit in the class AB amplifier circuit.

In the above process, the current on the branch formed by the fourth NMOS tube 204 and the sixth NMOS tube 206 is equal to the sum of the current flowing through the ninth NMOS tube 309 and the current flowing through the fifth PMOS tube 305. Since the distribution ratio of the current on the branch formed by the fourth NMOS tube 204 and the sixth NMOS tube 206 between the ninth NMOS tube 309 and the fifth PMOS tube 305 changes with the change of the load of the amplifier circuit, under certain load conditions, the current flowing through the fifth PMOS tube 305 will increase, and the current flowing through the ninth NMOS tube 309 will decrease, while under other conditions, the current flowing through the fifth PMOS tube 305 will decrease, and the current flowing through the ninth NMOS tube 309 will increase. When the load resistance driven by the amplifier circuit is small or the load current is large, the current flowing through the ninth NMOS tube 309 and the current flowing through the fifth PMOS tube 305 will be unbalanced. In extreme cases, the current on the branch composed of the fourth NMOS tube 204 and the sixth NMOS tube 206 will all flow through the fifth PMOS tube 305 but not through the ninth NMOS tube 309, that is, the current flowing through the ninth NMOS tube 309 is 0. In this case, the current of the sixth PMOS tube 306 will become extremely small. The extremely small sixth PMOS tube 306 will cause the entire floating current source closed-loop module 30 to be unstable and oscillate. In order to solve this problem, the seventh NMOS tube 207 and the eighth NMOS tube 208 are added to the folded common source input module 20. The current on the branch composed of the seventh NMOS tube 207 and the eighth NMOS tube 208 directly flows through the sixth PMOS tube 306, thereby ensuring that the current of the sixth PMOS tube 306 will not become extremely small, that is, ensuring the stability of the floating current source closed-loop module 30. Of course, in order to maintain the current balance of the two branches of the differential input stage in the folded common source and common gate input module 20, the sum of the current values of the fourth NMOS tube 204 and the eighth NMOS tube 208 needs to be equal to the current value of the third NMOS tube 203. If the width-to-length ratio of the fourth NMOS tube 204 is M, the width-to-length ratio of the eighth NMOS tube 208 is N, and the width-to-length ratio of the third NMOS tube 203 is M+N, then the ratio of the width-to-length ratios of the fourth NMOS tube 204, the eighth NMOS tube 208 and the third NMOS tube 203 is M:N:M+N.

Optionally, referring to FIG5 , a schematic diagram of the circuit structure of a bias circuit module 40 in an amplifier circuit according to an embodiment of the present invention is shown, wherein the bias circuit module 40 includes: a twelfth NMOS tube 412, a thirteenth NMOS tube 413, a fourteenth NMOS tube 414, a ninth PMOS tube 409, a tenth PMOS tube 410, a second fixed current source 411, and a fourth fixed current source 408; it should be noted that the components of the folded common source input module 20, the floating current source closed-loop module 30, and the output module 50 in FIG5 are the same as those in the same modules in FIG3 , and for the sake of simplicity of the drawing, the components therein are not specifically identified.

5 , in combination with FIG. 3 , the gate of the twelfth NMOS tube 412 is connected to the source of the thirteenth NMOS tube 413 and the second fixed current source 411 respectively; the source of the twelfth NMOS tube 412 is grounded; the drain of the twelfth NMOS tube 412 is connected to the gate of the ninth NMOS tube 309, the gate of the thirteenth NMOS tube 413, the drain of the thirteenth NMOS tube 413 and the fourth fixed current source 408 respectively; the gate of the thirteenth NMOS tube 413 is connected to its own drain, the gate of the ninth NMOS tube 309, the drain of the twelfth NMOS tube 412 and the fourth fixed current source 408 respectively; the source of the thirteenth NMOS tube 413 is connected to the gate of the twelfth NMOS tube 412 and the second fixed current source 411 respectively; the drain of the thirteenth NMOS tube 413 is connected to its own gate, the gate of the ninth NMOS tube 309, the drain of the twelfth NMOS tube 412 and the fourth fixed current source 408 respectively.

The gate of the fourteenth NMOS tube 414 is connected to its own drain and the drain of the tenth PMOS tube 410 respectively; the source of the fourteenth NMOS tube 414 is grounded; the drain of the fourteenth NMOS tube 414 is connected to its own gate and the drain of the tenth PMOS tube 410 respectively; the gate of the ninth PMOS tube 409 is connected to the source of the tenth PMOS tube 410 and the second fixed current source 411 respectively; the source of the ninth PMOS tube 409 is connected to the source of the second PMOS tube 212, the second fixed current source 411, the fourth fixed current source 408 and the output module 50 respectively. The drain of the ninth PMOS tube 409 is connected to the gate of the fifth PMOS tube 305, the gate of the tenth PMOS tube 410 and the second fixed current source 411 respectively; the gate of the tenth PMOS tube 410 is connected to the drain of the ninth PMOS tube 409, the gate of the fifth PMOS tube 305 and the second fixed current source 411 respectively; the source of the tenth PMOS tube 410 is connected to the gate of the ninth PMOS tube 409 and the second fixed current source 411 respectively; the drain of the tenth PMOS tube 410 is connected to the drain and gate of the fourteenth NMOS tube 414 respectively.

Among them, the twelfth NMOS tube 412, the thirteenth NMOS tube 413, the second fixed current source 411 and the fourth fixed current source 408 work together to provide a bias voltage for the ninth NMOS tube 309, and at the same time make the drain-source voltage of the ninth NMOS tube 309 equal to the drain-source voltage of the thirteenth NMOS tube 413; the fourteenth NMOS tube 414, the ninth PMOS tube 409, the tenth PMOS tube 410 and the second fixed current source 411 work together to provide a bias voltage for the fifth PMOS tube 305, and at the same time make the drain-source voltage of the fifth PMOS tube 305 equal to the drain-source voltage of the tenth PMOS tube 410.

Optionally, referring to FIG. 3 , the output module 50 includes: a fifteenth NMOS transistor 505 , an eleventh PMOS transistor 506 , a first resistor 502 , a second resistor 504 , a first capacitor 501 and a second capacitor 503 .

The gate of the fifteenth NMOS tube 505 is connected to the drain of the sixth NMOS tube 206, the source of the ninth NMOS tube 309, the drain of the fifth PMOS tube 305, and the first end of the first capacitor 501, respectively; the source of the fifteenth NMOS tube 505 is grounded; the drain of the fifteenth NMOS tube 505 is connected to the first end of the first resistor 502, the first end of the second resistor 504, and the drain of the eleventh PMOS tube 506, respectively; the gate of the eleventh PMOS tube 506 is connected to the drain of the fourth PMOS tube 214, The source of the fifth PMOS tube 305, the source of the sixth PMOS tube 306 and the first end of the second capacitor 503 are respectively connected; the source of the eleventh PMOS tube 506 is respectively connected to the source of the second PMOS tube 212, the source of the ninth NMOS tube 309, the second fixed current source 411, the fourth fixed current source 408 and the working power supply VDD; the drain of the eleventh PMOS tube 506 is respectively connected to the first end of the second resistor 504, the first end of the first resistor 502 and the drain of the fifteenth NMOS tube 505.

The first end of the first resistor 502 is connected to the drain of the fifteenth NMOS tube 505, the drain of the eleventh PMOS tube 506 and the first end of the second resistor 504 respectively; the second end of the first resistor 502 is connected to the second end of the first capacitor 501; the first end of the second resistor 504 is connected to the drain of the fifteenth NMOS tube 505, the drain of the eleventh PMOS tube 506 and the first end of the first resistor 502 respectively; the second end of the second resistor 504 is connected to the second end of the second capacitor 503.

The first end of the first capacitor 501 is connected to the gate of the fifteenth NMOS tube 505, the drain of the sixth NMOS tube 206, the source of the ninth NMOS tube 309 and the drain of the fifth PMOS tube 305 respectively; the second end of the first capacitor 501 is connected to the second end of the first resistor 502; the first end of the second capacitor 503 is connected to the gate of the eleventh PMOS tube 506, the drain of the fourth PMOS tube 214, the source of the fifth PMOS tube 305 and the source of the sixth PMOS tube 306 respectively; the second end of the second capacitor 503 is connected to the second end of the second resistor 504.

Among them, the drains of the fifteenth NMOS tube 505 and the eleventh PMOS tube 506 are the output ends of the amplifier circuit; the first resistor 502 and the first capacitor 501 constitute a Miller compensation structure to provide frequency compensation for the output current of the amplifier circuit; the second resistor 504 and the second capacitor 503 constitute a Miller compensation structure to provide frequency compensation for the amplifier circuit.

The principle of making the drain-source voltage of the ninth NMOS tube 309 equal to the drain-source voltage of the thirteenth NMOS tube 413, and making the drain-source voltage of the fifth PMOS tube 305 equal to the drain-source voltage of the tenth PMOS tube 410 is as follows: the current value of the fourth fixed current source 408 is set to be twice the current value of the second fixed current source 411. Since the sum of the current values flowing through the twelfth NMOS tube 412 and the thirteenth NMOS tube 413 is equal to the current value of the fourth fixed current source 408, the current values flowing through the twelfth NMOS tube 412 and the thirteenth NMOS tube 413 are both equal to the current value of the second fixed current source 411. It can be seen from the circuit structure that the sum of the gate-source voltages of the ninth NMOS tube 309 and the fifteenth NMOS tube 505 is equal to the sum of the gate-source voltages of the twelfth NMOS tube 412 and the thirteenth NMOS tube 413, that is, V _gs9 (gate-source voltage of the ninth NMOS tube 309)+V _gs15 (gate-source voltage of the fifteenth NMOS tube 505)= _Vgs12 (gate-source voltage of the twelfth NMOS tube 412)+ _Vgs13 (gate-source voltage of the thirteenth NMOS tube 413), the twelfth NMOS tube 412 is matched with the fifteenth NMOS tube 505, and the ninth NMOS tube 309 is matched with the thirteenth NMOS tube 413. It should be noted that the matching here means that the above-mentioned MOS tubes all adopt a multi-finger structure, and each finger has the same size. Through such a matching design, _Vgs9 = _Vgs13 , _Vgs15 = _Vgs12 , so the current value flowing through the fifteenth NMOS tube 505 is N times the current value flowing through the twelfth NMOS tube 412, that is, the static current value of the output stage circuit in the amplifier circuit is: N times the current value of the second fixed current source 411, wherein N refers to the ratio of the number of fingers of the fifteenth NMOS tube 505 to the number of fingers of the twelfth NMOS tube 412. Since the drain-source voltage of the thirteenth NMOS tube 413 is equal to its own gate-source voltage, that is, V _ds13 (drain-source voltage of the thirteenth NMOS tube 413) = V _gs13 (gate-source voltage of the thirteenth NMOS tube 413), and due to the effect of the feedback loop in the aforementioned floating current source closed-loop module 30, the drain-source voltage of the ninth NMOS tube 309 is equal to its gate-source voltage, that is, V _ds9 (drain-source voltage of the ninth NMOS tube 309) = V _gs9 (gate-source voltage of the ninth NMOS tube 309), so the drain-source voltage of the ninth NMOS tube 309 is also equal to the drain-source voltage of the drain-source voltage of the thirteenth NMOS tube 413.

By adopting the above circuit structure, the drain-source voltage of the ninth NMOS tube 309 is equal to the drain-source voltage of the thirteenth NMOS tube 413, thereby avoiding the influence of the channel length modulation effect of the ninth NMOS tube 309 in the current class AB amplifier circuit, making the control of the output current of the fifteenth NMOS tube 505 more precise, even if the power supply voltage changes, the drain-source voltage of the ninth NMOS tube 309 remains stable, achieving the purpose of greatly reducing the variation amplitude of the static current under different power supply voltages, and finally improving the power supply voltage rejection ratio of the class AB amplifier.

Similar to the above situation, the sum of the gate-source voltages of the fifth PMOS tube 305 and the eleventh PMOS tube 506 is equal to the sum of the gate-source voltages of the ninth PMOS tube 409 and the tenth PMOS tube 410, that is, V _gs5p (gate-source voltage of the fifth PMOS tube 305)+V _gs11p (gate-source voltage of the eleventh PMOS tube 506)=V _gs9p (gate-source voltage of the ninth PMOS tube 409)+V _gs10p (gate-source voltage of the tenth PMOS tube 410). Similarly, the ninth PMOS tube 409 is matched with the eleventh PMOS tube 506, and the fifth PMOS tube 305 is matched with the tenth PMOS tube 410. Then, the output current value flowing through the eleventh PMOS tube 506 is N times the current value flowing through the ninth PMOS tube 409, that is, the static current value of the output stage circuit in the amplifier circuit is also N times the current value of the second fixed current source 411, wherein N is the ratio of the number of fingers of the eleventh PMOS tube 506 to the number of fingers of the tenth PMOS tube 410.

It can be concluded from the circuit structure that the drain-source voltage V _ds5p of the fifth PMOS tube 305 is VDD (power supply voltage)-V _gs11p -V _gs15 , the drain-source voltage V _ds10p of the tenth PMOS tube 410 is VDD (power supply voltage)-V _gs9p -V _gs14 (gate-source voltage of the fourteenth NMOS tube 414 ), and the fourteenth NMOS tube 414 is set to match the fifteenth NMOS tube 505 , so V _ds5p =V _ds10p is obtained, that is, the drain-source voltage of the fifth PMOS tube 305 is also equal to the drain-source voltage of the tenth PMOS tube 410 .

By adopting the above circuit structure, the drain-source voltage of the fifth PMOS tube 305 is equal to the drain-source voltage of the tenth PMOS tube 410, thereby avoiding the influence of the channel length modulation effect of the fifth PMOS tube 305 in the current class AB amplifier circuit, making the control of the output current of the eleventh PMOS tube 506 more precise. Even if the power supply voltage changes, the drain-source voltage of the fifth PMOS tube 305 still remains equal to the drain-source voltage of the tenth PMOS tube 410, achieving the purpose of greatly reducing the variation amplitude of the static current under different power supply voltages, and finally improving the power supply voltage rejection ratio of the class AB amplifier.

In summary, the amplifier circuit of the embodiment of the present invention, through the effect of the feedback loop in the floating current source closed-loop module 30, makes the drain-source voltage of the ninth NMOS tube 309 equal to its gate-source voltage, thereby avoiding the drain voltage of the ninth NMOS tube 309 being too high, and reducing the leakage current (I _{bd )} between the drain end of the ninth NMOS tube 309 and the substrate. ), and finally avoid the problems of reduced output impedance, reduced gain, and reduced power supply rejection ratio of the differential input stage circuit in the class AB amplifier circuit; at the same time, based on the matching of the twelfth NMOS tube 412 and the fifteenth NMOS tube 505 in the bias circuit module 40, and the matching of the ninth NMOS tube 309 and the thirteenth NMOS tube 413, since the drain-source voltage of the ninth NMOS tube 309 is equal to its gate-source voltage, the drain-source voltage of the ninth NMOS tube 309 and the drain-source voltage of the thirteenth NMOS tube 413 are also equal, eliminating the influence of the channel length modulation effect of the ninth NMOS tube 309, achieving the purpose of greatly reducing the variation amplitude of the static current under different power supply voltages, and finally improving the power supply voltage rejection ratio of the class AB amplifier.

Similarly, the amplifier circuit of the embodiment of the present invention is based on the matching of the ninth PMOS tube 409 with the eleventh PMOS tube 506, the matching of the fifth PMOS tube 305 with the tenth PMOS tube 410, and the matching of the fourteenth NMOS tube 414 with the fifteenth NMOS tube 505, so that the drain-source voltage of the fifth PMOS tube 305 is equal to the drain-source voltage of the tenth PMOS tube 410, thereby eliminating the influence of the channel length modulation effect of the fifth PMOS tube 305, achieving the purpose of greatly reducing the variation amplitude of the static current under different power supply voltages, and ultimately improving the power supply voltage rejection ratio of the class AB amplifier.

In summary, the amplifier circuit of the present invention not only accurately controls the quiescent current of the output stage circuit during use, but also improves the output impedance of the differential input stage circuit in the amplifier circuit, and finally improves the gain and power supply rejection ratio of the amplifier circuit. The entire amplifier circuit has fewer components added, low cost, strong compatibility, high operating reliability, and greatly enriches the user's choice of using class AB amplifiers.

Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims (10)

1. An amplifier circuit, the amplifier circuit comprising:

The device comprises a folding cascode input module, a floating current source closed loop module, a bias circuit module and an output module;

the folding cascode input module, the floating current source closed loop module, the bias circuit module and the output module are connected with each other;

The folded cascode input module is used for providing an input signal for the amplifier circuit;

the floating current source closed loop module is used for inhibiting the output impedance of the folding cascode input module from decreasing and controlling the quiescent current of an output stage circuit in the amplifier circuit together with the bias circuit module;

the bias circuit module is used for providing bias voltage for the floating current source closed-loop module and controlling the quiescent current of an output stage circuit in the amplifier circuit together with the floating current source closed-loop module;

the output module is used for outputting the current generated by the amplifier circuit and compensating the frequency characteristic of the amplifier circuit;

the bias circuit module provides bias voltage for the grid electrodes of a fifth PMOS tube and a ninth NMOS tube in the floating current source closed-loop module so that the output stage of the amplifier circuit is biased in class A and class B, and the bias circuit module and the floating current source closed-loop module jointly control the static current of the transistor in the output module so as to control the static current of the output stage circuit in the amplifier circuit;

the floating current source closed loop module comprises: the ninth NMOS tube, the fifth PMOS tube, the sixth PMOS tube and the auxiliary amplifier;

the auxiliary amplifier controls the drain voltage of the ninth NMOS tube so that the drain voltage of the ninth NMOS tube is equal to the gate voltage of the ninth NMOS tube.

2. The amplifier circuit of claim 1, wherein the folded cascode input module comprises: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube;

the first NMOS tube and the second NMOS tube form an input stage differential input pair tube for receiving external signals;

The third NMOS tube, the fourth NMOS tube, the eighth NMOS tube, the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube form a common-source common-gate current mirror load of a differential input stage circuit in the amplifier circuit so as to generate output current of the differential input stage circuit in the amplifier circuit and control drain voltage of an MOS tube in the floating current source closed loop module;

the first PMOS tube and the second PMOS tube form an input stage current mirror;

the third PMOS tube and the fourth PMOS tube form an input stage common-source common-gate structure; the input stage current mirror and the input stage cascode structure cooperate to generate an output current of a differential input stage circuit in the amplifier circuit.

3. The amplifier circuit of claim 2, wherein the floating current source closed loop module comprises: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube;

The tenth NMOS tube and the eleventh NMOS tube form a feedback level differential input pair tube;

The seventh PMOS tube and the eighth PMOS tube form a feedback stage current mirror load, the feedback stage differential input pair tube and the feedback stage current mirror load act together to control the drain voltage of the ninth NMOS tube, so that the drain voltage of the ninth NMOS tube is equal to the grid voltage of the ninth NMOS tube.

4. The amplifier circuit of claim 3 wherein the bias circuit module comprises: a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube;

The twelfth NMOS tube, the thirteenth NMOS tube and the fixed current source act together to provide bias voltage for the ninth NMOS tube, and meanwhile, the drain-source voltage of the ninth NMOS tube is equal to the drain-source voltage of the thirteenth NMOS tube;

the fourteenth NMOS tube, the ninth PMOS tube, the tenth PMOS tube and the fixed current source act together to provide bias voltage for the fifth PMOS tube, and meanwhile drain-source voltage of the fifth PMOS tube is equal to drain-source voltage of the tenth PMOS tube.

5. The amplifier circuit of claim 4, wherein the output module comprises: a fifteenth NMOS tube, an eleventh PMOS tube, a first resistor, a second resistor, a first capacitor and a second capacitor;

The drain electrodes of the fifteenth NMOS tube and the eleventh PMOS tube are the output end of the amplifier circuit;

the first resistor and the first capacitor form a miller compensation structure for providing frequency compensation for the amplifier circuit;

The second resistor and the second capacitor form a miller compensation structure for providing frequency compensation for the amplifier circuit.

6. The amplifier circuit of claim 3 wherein the drain voltage of the ninth NMOS transistor acts on the gate of the sixth PMOS transistor through the feedback stage differential input pair and the feedback stage current mirror load to control the drain voltage of the sixth PMOS transistor such that the drain voltage of the ninth NMOS transistor is equal to the gate voltage.

7. The amplifier circuit of claim 4 wherein the fourth NMOS transistor has a width to length ratio of M, the eighth NMOS transistor has a width to length ratio of N, the third NMOS transistor has a width to length ratio of m+n, and the current on the branch formed by the fourth NMOS transistor and the sixth NMOS transistor is equal to the sum of the currents flowing through the ninth NMOS transistor and the fifth PMOS transistor.

8. The amplifier circuit of claim 4, wherein the drain-source voltage of the ninth NMOS transistor is equal to the drain-source voltage of the thirteenth NMOS transistor;

The ninth NMOS tube and the thirteenth NMOS tube are of multi-interdigital structures, and each interdigital structure has the same size.

9. The amplifier circuit of claim 4, wherein the drain-source voltage of the fifth PMOS transistor is equal to the drain-source voltage of the tenth PMOS transistor;

the fifth PMOS tube and the tenth PMOS tube are all in multi-interdigital structures, and each interdigital has the same size.

10. The amplifier circuit of claim 4, wherein the current on the branch consisting of the fourth NMOS transistor and the sixth NMOS transistor is equal to the sum of the currents flowing through the ninth NMOS transistor and the fifth PMOS transistor;

the current on a branch formed by the seventh NMOS tube and the eighth NMOS tube directly flows through the sixth PMOS tube so that the floating current source closed-loop module is kept stable;

the magnitude of the current flowing through the ninth NMOS transistor and the magnitude of the current flowing through the fifth PMOS transistor dynamically change with the change of the load current of the amplifier circuit.