CN104242830A - Reconfigurable ultra-broadband low noise amplifier with active inductor - Google Patents
Reconfigurable ultra-broadband low noise amplifier with active inductor Download PDFInfo
- Publication number
- CN104242830A CN104242830A CN201410484497.9A CN201410484497A CN104242830A CN 104242830 A CN104242830 A CN 104242830A CN 201410484497 A CN201410484497 A CN 201410484497A CN 104242830 A CN104242830 A CN 104242830A
- Authority
- CN
- China
- Prior art keywords
- nmos pass
- pass transistor
- grid
- drain electrode
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a reconfigurable ultra-broadband low noise amplifier with an active inductor, which has the characteristics of high gains, adjustable gains, small area, low noises and the like. The low noise amplifier comprises a parallel feedback amplifier, a Cascode amplifier and a common source amplifier fed back based on a fully differential floating active inductor, and an output buffering stage, wherein the parallel feedback amplifier adopts a resistor to replace a traditional spiral inductor to realize broadband input impedance matching and the area of a chip is reduced; by adopting the structure, the transconductance is increased so that the transconductance is changed into gmN+gmP from original gmN or gmP, and the noises of the amplifier are reduced. A middle amplification stage is composed of the Cascode amplifier and the common source amplifier so that the gains of the whole amplifier are increased. The active inductor is the fully differential floating active inductor and the whole amplifier only adopts one active inductor so that the area of the chip is greatly reduced; the size of an inductance value can be changed through adjusting bias voltage, and furthermore, the grains of the low noise amplifier are changed and the grains can be adjusted.
Description
Technical field
The present invention relates to a kind of field of radio frequency circuit design, particularly relate to a kind of reconfigurable ultra-wideband low-noise amplifier based on active inductance.
Background technology
Inductance is widely used in low noise amplifier design.Most of the low noise amplifier chip area is occupied at the passive inductance of sheet (PI), and quality factor (Q) and self-resonant frequency low, inductance value and Q value can not regulate, and more and more can not meet low noise amplifier small size, high integrated, the adjustable growth requirement of low cost, broadband, performance.
In addition, as everyone knows, the performance of low noise amplifier is decided by device (element) size and circuit bias state.Along with the development of integrated circuit technology, the characteristic size of device constantly reduces, technique (process) deviation is on device property and then more and more serious on the impact of low noise amplifier, in addition, do not consider when low noise amplifier designs and the parasitism of exist actually (comprising encapsulation parasitic) also makes low noise amplifier performance off-design original intention value.Operating voltage (Supply Voltage) change and ambient temperature (Temperature) change also have an impact to low noise amplifier characteristic.Therefore for adapting to these changes, people wish to regulate (reconfigure) to low noise amplifier performance, the impact brought low noise amplifier with compensate for process deviation, encapsulation parasitism, variation of ambient temperature.
Therefore, instantly need the urgent technical problem solved to be exactly: how can the design one low noise amplifier of novelty, make it have adjustable gain, be convenient to integrated.
Summary of the invention:
The invention provides a kind of reconfigurable ultra-wideband low-noise amplifier based on active inductance, by the gain-adjusted regulating the bias voltage of active inductance to realize amplifier.Because active inductance adopts the transistor that size is little to synthesize, instead of the passive inductance that area is large, therefore substantially reduce chip area, and be convenient to integrated.
A kind of ultra-wideband low-noise amplifier reconfigurable based on active inductance provided by the invention, comprises shunt feedback amplifier 1, Cascode amplifier 2, and band difference floats the common-source amplifier 4 that ground active inductance 3 feeds back, and exports buffer stage 5.Wherein shunt feedback amplifier 1 completes broadband Input matching, and Cascode amplifier 2 and common-source amplifier 4 cascade, as interstage amplifier section, export buffer stage 5 and complete output matching.
Preferably, described shunt feedback amplifier 1 is by the first nmos pass transistor (M1), first PMOS transistor (M2) and the first feedback resistance (R1) be in parallel composition, the wherein source class ground connection of the first nmos pass transistor (M1), the source class of the first PMOS transistor (M2) meets power supply Vdd, the grid of two transistors connects input jointly, and the drain electrode of two transistors is connected to the input of Cascode amplifier 2 by the first coupling capacitance (C1).
Preferably, described Cascode amplifier 2 is connected and composed by the source class of the drain electrode of the second nmos pass transistor (M3) and the 3rd nmos pass transistor (M4), the wherein source class ground connection of the second nmos pass transistor (M3), drain electrode connects the source class of the 3rd nmos pass transistor (M4), the grid of the 3rd nmos pass transistor (M4) connects the first bias voltage (V1), the input of the common-source amplifier 4 being connected to band feedback by the second coupling capacitance (C2) that drains.
Preferably, the common-source amplifier 4 of described band feedback floats ground active inductance 3 by the 4th nmos pass transistor (M5) and difference and forms, wherein active inductance 3 two ends, difference floating ground connect grid and the drain electrode of the 4th nmos pass transistor (M5) respectively, the source class ground connection of the 4th nmos pass transistor (M5), drain electrode connects the input of buffer stage 5.
Preferably, described difference floating ground active inductance 3 comprises the first differential pair 6 be made up of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3) and the second differential pair 7 be made up of the second PMOS transistor (Mp4) and the direct cross-couplings of the 3rd PMOS transistor (Mp5), the first buffer resistance (R4) between two differential pairs and the second buffer resistance (R5), also comprise the first current source nmos transistor (Mn1) and the second current source PMOS transistor (Mp1), 3rd current source PMOS transistor (Mp2) and the 4th current source PMOS transistor (Mp3).Wherein the first current source nmos transistor (Mn1) source class ground connection, grid connects the 3rd bias voltage (Vb1), and drain electrode connects the source class of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3).The source class of the 7th nmos pass transistor (Mn2) connects the source class of the 8th nmos pass transistor (Mn3), grid connects the grid of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the second PMOS transistor (Mp4) and the drain electrode of the 3rd PMOS transistor (Mp5).The grid of the 8th nmos pass transistor (Mn3) connects the drain electrode of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the 3rd PMOS transistor (Mp5) and the drain electrode of the second PMOS transistor (Mp4).The source class of the second PMOS transistor (Mp4) connects the source class of the 3rd PMOS transistor (Mp5) and the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the second current source PMOS transistor (Mp1).The source class of the 3rd PMOS transistor (Mp5) connects the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the 4th current source PMOS transistor (Mp3).Second current source PMOS transistor (Mp1) source class meets power supply Vdd, and grid connects the 4th bias voltage (Vb2).3rd current source PMOS transistor (Mp2) source class meets power supply Vdd, and grid connects the 5th bias voltage (Vb3).4th current source PMOS transistor (Mp3) source class meets power supply Vdd, and grid connects the 6th bias voltage (Vb4).First buffer resistance (R4) one end receives the grid of the 7th nmos pass transistor (Mn2), and an end receives the grid of the second PMOS transistor (Mp4).Second buffer resistance (R5) one end receives the grid of the 8th nmos pass transistor (Mn3), and an end receives the grid of the 3rd PMOS transistor (Mp5).
Preferably, described difference float ground active inductance 3 inductance value can by change the 3rd bias voltage (Vb1), 4th bias voltage (Vb2), 5th bias voltage (Vb3) and the 6th bias voltage (Vb4) carry out tuning, realize the adjustable of inductance value, and then the gain of low noise amplifier can be changed.
Preferably, described buffer stage 5 is made up of the 5th nmos pass transistor (M6) and the 6th nmos pass transistor (M7), wherein the 5th nmos pass transistor (M6) drain electrode meets power supply Vdd, source class connects the drain electrode of the 6th nmos pass transistor (M7), the grid of the 6th nmos pass transistor (M7) connects the second bias voltage (V2), source class ground connection, exports the source electrode of termination the 5th nmos pass transistor (M6) and the drain electrode of the 6th nmos pass transistor (M7).
Compared with prior art, the present invention has the following advantages:
The present invention adopts shunt feedback amplifier as the first order, replaces passive inductive feedback with resistance feedback, saves the area of chip, achieves wide-band impedance coupling simultaneously, adopts PMOS transistor and nmos pass transistor parallel connection to increase mutual conductance, makes it become g
mN+ g
mP, reduce noise factor.And the present invention adopts difference floating ground active inductance to replace passive inductance, whole amplifier is made not use passive inductance, further reduce the area of chip, and realize the adjustable of inductance value by regulating its external bias voltage, and then achieve the adjustable of low noise amplifier gain, compensate for the technique because not considering in design, the parasitic gain degradation brought of encapsulation, obtaining good gain flatness simultaneously.
Accompanying drawing illustrates:
Fig. 1 is circuit diagram of the present invention.
Fig. 2 is the S11 of low noise amplifier after employing parallel feedback structure, the relation curve of S12, S22, NF and frequency.
Fig. 3 is the circuit diagram that difference of the present invention floats ground active inductance.
Fig. 4 is the equivalent circuit diagram that difference of the present invention floats ground active inductance.
Fig. 5 is ground active inductance bias voltage is floated in the gain of low noise amplifier of the present invention variation relation figure with difference.
Fig. 6 is schematic diagram of the present invention.
Main element symbol description:
1-shunt feedback amplifier 2-Cascode amplifier 3-difference floating ground active inductance
4-NMOS common-source amplifier 5-NMOS exports buffer stage 6-NMOS first differential pair circuit
7-PMOS second differential pair circuit
Embodiment:
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing, the present invention is described in further detail.But example is not as a limitation of the invention.
The present invention is based on TSMC RF CMOS 0.18 μm of technique to carry out designing and verifying.Whole circuit topology as shown in Figure 1, comprise by the first nmos pass transistor (M1), first PMOS transistor (M2) and the first feedback resistance (R1) be in parallel composition shunt feedback amplifier 1, the Cascode amplifier 2 connected and composed by the drain electrode of the second nmos pass transistor (M3) and the source class of the 3rd nmos pass transistor (M4), the grid of the 4th nmos pass transistor (M5) and the drain electrode of the 4th nmos pass transistor (M5) is connected respectively and the common source feedback amplifier 4 that forms by active inductance 3 two ends, difference floating ground, the output buffer stage 5 that the drain electrode connecting the 6th nmos pass transistor (M7) by the source electrode of the 5th nmos pass transistor (M6) is formed.The wherein source class ground connection of the first nmos pass transistor (M1), the source class of the first PMOS transistor (M2) meets power supply Vdd, the grid of two transistors connects input jointly, the drain electrode of two transistors connects the grid of the second nmos pass transistor (M3) by the first coupling capacitance (C1), the source class ground connection of the second nmos pass transistor (M3), drain electrode connects the source class of the 3rd nmos pass transistor (M4), the grid of the 3rd nmos pass transistor (M4) connects the first bias voltage (V1), drain electrode is connected to the grid of the 4th nmos pass transistor (M5) by the second coupling capacitance (C2), the source class ground connection of the 4th nmos pass transistor (M5), drain electrode connects the grid of the 5th nmos pass transistor (M6), 5th nmos pass transistor (M6) drain electrode meets power supply Vdd, source class connects the drain electrode of the 6th nmos pass transistor (M7), the grid of the 6th nmos pass transistor (M7) connects the second bias voltage (V2), source class ground connection, export the source electrode of termination the 5th nmos pass transistor (M6) and the drain electrode of the 6th nmos pass transistor (M7).First feedback resistance (R1) one end receives the first nmos pass transistor (M1) and the first PMOS transistor (M2) grid, and an end receives the drain electrode of the first nmos pass transistor (M1) and the first PMOS transistor (M2).Second load resistance (R2) one end receives the drain electrode of the 3rd nmos pass transistor (M4), one end receives power supply Vdd, 3rd load resistance (R3) end receives the drain electrode of the 4th nmos pass transistor (M5), and an end receives power supply Vdd.
Difference floating ground active inductance 3 comprises the first current source nmos transistor (Mn1), second current source PMOS transistor (Mp1), 3rd current source PMOS transistor (Mp2) and the 4th current source PMOS transistor (Mp3), and the first differential pair 6 to be made up of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3) and by the second PMOS transistor (Mp4) and the 3rd PMOS transistor (Mp5) directly the second differential pair 7 of forming of cross-couplings, also comprise the first buffer resistance (R4) between two differential pairs and the second buffer resistance (R5).Wherein the first current source nmos transistor (Mn1) source class ground connection, grid connects the 3rd bias voltage (Vb1), and drain electrode connects the source class of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3).The source class of the 7th nmos pass transistor (Mn2) connects the source class of the 8th nmos pass transistor (Mn3), grid connects the grid of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the second PMOS transistor (Mp4) and the drain electrode of the 3rd PMOS transistor (Mp5).The grid of the 8th nmos pass transistor (Mn3) connects the drain electrode of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the 3rd PMOS transistor (Mp5) and the drain electrode of the second PMOS transistor (Mp4).The source class of the second PMOS transistor (Mp4) connects the source class of the 3rd PMOS transistor (Mp5) and the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the second current source PMOS transistor (Mp1).The source class of the 3rd PMOS transistor (Mp5) connects the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the 4th current source PMOS transistor (Mp3).Second current source PMOS transistor (Mp1) source class meets power supply Vdd, and grid connects the 4th bias voltage (Vb2).3rd current source PMOS transistor (Mp2) source class meets power supply Vdd, and grid connects the 5th bias voltage (Vb3).4th current source PMOS transistor (Mp3) source class meets power supply Vdd, and grid connects the 6th bias voltage (Vb4).First buffer resistance (R4) one end receives the grid of the 7th nmos pass transistor (Mn2), and an end receives the grid of the second PMOS transistor (Mp4).Second buffer resistance (R5) one end receives the grid of the 8th nmos pass transistor (Mn3), and an end receives the grid of the 3rd PMOS transistor (Mp5).
As shown in Figure 1, the present invention adopts shunt feedback amplifier as the first order, increases the mutual conductance of the first order, makes it by original g
mPor g
mNbecome g
mN+ g
mP, input impedance R
in, gain A
vcan be expressed as with noise factor NF:
Wherein R
l, R
1and R
stotal load resistance of first order shunt feedback amplifier respectively, parallel feedback resistance and source impedance.G
mNand g
mPbe respectively the mutual conductance of the first nmos pass transistor (M1) and the first PMOS transistor (M2), λ is 2/3 in long channel MOSFET.Known by choosing suitable R by formula (1)
1value can realize wide-band impedance coupling, as can be seen from formula (2) and formula (3), this parallel feedback structure improves the gain of the first order and reduces the noise factor of the first order, according to low noise amplifier cascade noise theory, when in cascade low noise amplifier, first order gain is enough large, the noise factor of whole amplifier depends primarily on the first order.The S11 adopting low noise amplifier after this parallel feedback structure is given, the relation of S22, NF and frequency in Fig. 2.As can be seen from the figure, in 500MHz to 5GHz scope, S11 and S22 is all lower than-10dB, and NF, lower than 4dB, shows to have good input-output adapt ation and noiseproof feature.
As shown in Figure 1, the present invention as the second level (interstage amplifier section) with Cascode amplifier 2 and common-source amplifier 4 cascade, improves the gain of whole amplifier, and adds the isolation of input and output.Fig. 2 gives the relation of S12 and frequency equally, and as can be seen from the figure, S12 is lower than-70dB in 500MHz to 5GHz scope, and reverse isolation is good.
As shown in Figure 1, the present invention's difference floats ground active inductance 3 as the feedback inductance of common-source amplifier, considerably reduces the area of chip, and achieves the adjustable of inductance value by the adjustment of external bias.Fig. 3 for this reason difference floats the structure chart of ground active inductance, and the first differential pair 6 be made up of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3) is equivalent to positive mutual conductance g
mN1, be equivalent to negative transconductance-g by the second PMOS transistor (Mp4) and the 3rd PMOS transistor (Mp5) the second differential pair 7 that directly cross-couplings forms
mP1, positive negative transconductance is directly connected, and then negative transconductance is by the first buffer resistance (R4), and the second buffer resistance (R5) takes back input.First current source nmos transistor (Mn1) provides biased for the first differential pair 6, second current source PMOS transistor (Mp1), the 3rd current source PMOS transistor (Mp2) and the 4th current source PMOS transistor (Mp3) provide biased for the second differential pair 7.Fig. 4 is the equivalent circuit diagram that this difference floats ground active inductance.Wherein,
R
P＝r
oP (6)
C
P＝C
effN (7)
Wherein R
s, R
pand C
pbe respectively dead resistance and the parasitic capacitance of active inductance, C
effNand C
effPbe respectively the input equivalent capacity of active inductance first differential pair 6 and the second differential pair 7, r
oNand r
oPbe respectively the output equivalent resistance of active inductance first differential pair 6 and the second differential pair 7.As can be seen from formula (4), by changing g
mN1and g
mP1(namely changing Vb1, the value of Vb2, Vb3, Vb4) just can change inductance value, and then changes the gain of amplifier.
Fig. 5 is the gain S of low noise amplifier
21the variation relation figure of ground active inductance bias voltage is floated with difference.As can be seen from the figure, by the bias voltage regulating difference to float ground active inductance, S
21can regulate within the scope of 13.5dB-19.8dB, tuning range reaches 6dB.
Above embodiment only in order to technical scheme of the present invention to be described, to enable professional and technical personnel in the field realize or uses the present invention, being not intended to limit.Although with reference to previous embodiment to invention has been detailed description, those skilled in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (2)
1. the reconfigurable ultra-wideband low-noise amplifier based on active inductance, it is characterized in that: comprise by the first nmos pass transistor (M1), first PMOS transistor (M2) and the first feedback resistance (R1) be in parallel composition shunt feedback amplifier (1), the Cascode amplifier (2) connected and composed by the drain electrode of the second nmos pass transistor (M3) and the source class of the 3rd nmos pass transistor (M4), the grid of the 4th nmos pass transistor (M5) and the drain electrode of the 4th nmos pass transistor (M5) is connected respectively and the common source feedback amplifier (4) that forms by active inductance (3) two ends, difference floating ground, the output buffer stage (5) that the drain electrode connecting the 6th nmos pass transistor (M7) by the source electrode of the 5th nmos pass transistor (M6) is formed, the wherein source class ground connection of the first nmos pass transistor (M1), the source class of the first PMOS transistor (M2) meets power supply Vdd, the grid of two transistors connects input jointly, the drain electrode of two transistors connects the grid of the second nmos pass transistor (M3) by the first coupling capacitance (C1), the source class ground connection of the second nmos pass transistor (M3), drain electrode connects the source class of the 3rd nmos pass transistor (M4), the grid of the 3rd nmos pass transistor (M4) connects the first bias voltage (V1), drain electrode is connected to the grid of the 4th nmos pass transistor (M5) by the second coupling capacitance (C2), the source class ground connection of the 4th nmos pass transistor (M5), drain electrode connects the grid of the 5th nmos pass transistor (M6), 5th nmos pass transistor (M6) drain electrode meets power supply Vdd, source class connects the drain electrode of the 6th nmos pass transistor (M7), the grid of the 6th nmos pass transistor (M7) connects the second bias voltage (V2), source class ground connection, export the source electrode of termination the 5th nmos pass transistor (M6) and the drain electrode of the 6th nmos pass transistor (M7), first feedback resistance (R1) one end receives the first nmos pass transistor (M1) and the first PMOS transistor (M2)) grid, an end receives the drain electrode of the first nmos pass transistor (M1) and the first PMOS transistor (M2), second load resistance (R2) one end receives the drain electrode of the 3rd nmos pass transistor (M4), one end receives power supply Vdd, 3rd load resistance (R3) end receives the drain electrode of the 4th nmos pass transistor (M5), and an end receives power supply Vdd,
Wherein, difference floating ground active inductance (3) comprises the first current source nmos transistor (Mn1), second current source PMOS transistor (Mp1), 3rd current source PMOS transistor (Mp2) and the 4th current source PMOS transistor (Mp3), and the first differential pair (6) to be made up of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3) and by the second PMOS transistor (Mp4) and the 3rd PMOS transistor (Mp5) directly the second differential pair (7) of forming of cross-couplings, also comprise the first buffer resistance (R4) between two differential pairs and the second buffer resistance (R5), wherein the first current source nmos transistor (Mn1) source class ground connection, grid connects the 3rd bias voltage (Vb1), and drain electrode connects the source class of the 7th nmos pass transistor (Mn2) and the 8th nmos pass transistor (Mn3), the source class of the 7th nmos pass transistor (Mn2) connects the source class of the 8th nmos pass transistor (Mn3), grid connects the grid of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the second PMOS transistor (Mp4) and the drain electrode of the 3rd PMOS transistor (Mp5), the grid of the 8th nmos pass transistor (Mn3) connects the drain electrode of the 4th nmos pass transistor (M5), and drain electrode connects the grid of the 3rd PMOS transistor (Mp5) and the drain electrode of the second PMOS transistor (Mp4), the source class of the second PMOS transistor (Mp4) connects the source class of the 3rd PMOS transistor (Mp5) and the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the second current source PMOS transistor (Mp1), the source class of the 3rd PMOS transistor (Mp5) connects the drain electrode of the 3rd current source PMOS transistor (Mp2), and grid connects the drain electrode of the 4th current source PMOS transistor (Mp3), second current source PMOS transistor (Mp1) source class meets power supply Vdd, and grid connects the 4th bias voltage (Vb2), 3rd current source PMOS transistor (Mp2) source class meets power supply Vdd, and grid connects the 5th bias voltage (Vb3), 4th current source PMOS transistor (Mp3) source class meets power supply Vdd, and grid connects the 6th bias voltage (Vb4), first buffer resistance (R4) one end receives the grid of the 7th nmos pass transistor (Mn2), and an end receives the grid of the second PMOS transistor (Mp4), second buffer resistance (R5) one end receives the grid of the 8th nmos pass transistor (Mn3), and an end receives the grid of the 3rd PMOS transistor (Mp5).
2. the reconfigurable ultra-wideband low-noise amplifier based on active inductance according to claim 1, it is characterized in that: the voltage regulation limits of the 3rd described bias voltage (Vb1) is 0.5-1.5 volt, 4th bias voltage (Vb2), the voltage regulation limits of the 5th bias voltage (Vb3) and the 6th bias voltage (Vb4) is 0.5-2.7 volt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410484497.9A CN104242830B (en) | 2014-09-21 | 2014-09-21 | Reconfigurable ultra-wideband low-noise amplifier based on active inductance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410484497.9A CN104242830B (en) | 2014-09-21 | 2014-09-21 | Reconfigurable ultra-wideband low-noise amplifier based on active inductance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104242830A true CN104242830A (en) | 2014-12-24 |
| CN104242830B CN104242830B (en) | 2017-06-27 |
Family
ID=52230328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410484497.9A Active CN104242830B (en) | 2014-09-21 | 2014-09-21 | Reconfigurable ultra-wideband low-noise amplifier based on active inductance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104242830B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270110A (en) * | 2014-09-25 | 2015-01-07 | 西安电子科技大学 | Variable gain amplifier based on voltage-controlled inductive load |
| CN107040225A (en) * | 2016-11-01 | 2017-08-11 | 全球能源互联网研究院 | A kind of low-noise amplifier and its control method |
| CN107819445A (en) * | 2017-10-12 | 2018-03-20 | 湖北大学 | A kind of big output voltage swing drive circuit of high speed |
| CN108964620A (en) * | 2018-07-05 | 2018-12-07 | 湖南师范大学 | A kind of New Active inductance based on collapsible Cascode structure |
| CN109672418A (en) * | 2018-12-19 | 2019-04-23 | 佛山臻智微芯科技有限公司 | A kind of high gain operational amplifier using feedforward compensation |
| CN110708021A (en) * | 2019-09-30 | 2020-01-17 | 西安电子科技大学 | High-linearity differential double-feedback low-noise amplifier |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013125829A (en) * | 2011-12-14 | 2013-06-24 | Yamaha Corp | Semiconductor device |
| CN103973233A (en) * | 2014-05-20 | 2014-08-06 | 上海集成电路研发中心有限公司 | Low-noise amplifier based on differential structure active inductor |
| CN104009722A (en) * | 2014-05-07 | 2014-08-27 | 北京工业大学 | Full differential type ungrounded active inductor |
-
2014
- 2014-09-21 CN CN201410484497.9A patent/CN104242830B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013125829A (en) * | 2011-12-14 | 2013-06-24 | Yamaha Corp | Semiconductor device |
| CN104009722A (en) * | 2014-05-07 | 2014-08-27 | 北京工业大学 | Full differential type ungrounded active inductor |
| CN103973233A (en) * | 2014-05-20 | 2014-08-06 | 上海集成电路研发中心有限公司 | Low-noise amplifier based on differential structure active inductor |
Non-Patent Citations (1)
| Title |
|---|
| 郭振杰等: "基于有源电感的全集成超宽带低噪声放大器", 《微电子学》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270110A (en) * | 2014-09-25 | 2015-01-07 | 西安电子科技大学 | Variable gain amplifier based on voltage-controlled inductive load |
| CN107040225A (en) * | 2016-11-01 | 2017-08-11 | 全球能源互联网研究院 | A kind of low-noise amplifier and its control method |
| CN107819445A (en) * | 2017-10-12 | 2018-03-20 | 湖北大学 | A kind of big output voltage swing drive circuit of high speed |
| CN108964620A (en) * | 2018-07-05 | 2018-12-07 | 湖南师范大学 | A kind of New Active inductance based on collapsible Cascode structure |
| CN108964620B (en) * | 2018-07-05 | 2022-01-28 | 湖南师范大学 | Active inductor based on folding Cascode structure |
| CN109672418A (en) * | 2018-12-19 | 2019-04-23 | 佛山臻智微芯科技有限公司 | A kind of high gain operational amplifier using feedforward compensation |
| CN110708021A (en) * | 2019-09-30 | 2020-01-17 | 西安电子科技大学 | High-linearity differential double-feedback low-noise amplifier |
| CN110708021B (en) * | 2019-09-30 | 2023-04-07 | 西安电子科技大学 | High-linearity differential double-feedback low-noise amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104242830B (en) | 2017-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102497167B (en) | Radio-frequency ultra-wideband low-noise amplifier based on inductance compensation | |
| CN101741316B (en) | Gain variable broadband radio frequency low-noise amplifier | |
| CN104242830B (en) | Reconfigurable ultra-wideband low-noise amplifier based on active inductance | |
| CN102394571B (en) | In-chip integrated low noise amplifier | |
| CN107070425B (en) | Broadband low-power-consumption low-noise amplifier applied to wireless sensor network | |
| CN106059505B (en) | A kind of trsanscondutance amplifier of low noise sound pitch output resistance | |
| CN105141265A (en) | Gain increased operational transconductance amplifier | |
| CN107248850B (en) | Non-inductance low-power-consumption high-gain high-linearity broadband low-noise amplifier | |
| CN108964620B (en) | Active inductor based on folding Cascode structure | |
| CN107769736B (en) | Self-biased broadband low noise amplifier | |
| CN103219952B (en) | A kind of wideband low noise amplifier adopting noise cancellation technique | |
| CN102868377A (en) | Total 3G (Third Generation Telecommunication) CMOS (Complementary Metal-Oxide-Semiconductor Transistor) differential low-noise amplifier based on controllable active inductor | |
| CN110729974A (en) | Ultra-wideband high-gain low-noise amplifier | |
| CN111478671B (en) | Novel low-noise amplifier applied to Sub-GHz frequency band | |
| CN104821793B (en) | Signal amplifier, electronic device and forming method thereof | |
| CN104124924A (en) | Linearization common-gate CMOS low-noise amplifier circuit | |
| CN107733375A (en) | Ultra-wideband low-noise amplifier | |
| CN103956986A (en) | Differential active inductor with tunable high Q value | |
| CN112583361A (en) | High-gain broadband low-noise amplifier based on noise elimination | |
| CN104065346A (en) | Broadband low noise amplifier circuit based on cross-coupled feedback | |
| CN103633947A (en) | Noninductive and high-gain CMOS (Complementary Metal Oxide Semiconductor) broadband low-noise amplifier | |
| KR101590605B1 (en) | Linear power amplifier for wireless transmitter | |
| CN202772848U (en) | Fully third generation telecommunication (3G) complementary metal oxide semiconductor (CMOS) difference low noise amplifier based on controllable active inductor | |
| CN106559042A (en) | The low-noise amplifier being applied under low-voltage | |
| CN107104647B (en) | Power amplifier based on neural network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |