CN110224700A - A kind of high speed complementation type dual power supply operational amplifier - Google Patents
A kind of high speed complementation type dual power supply operational amplifier Download PDFInfo
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- CN110224700A CN110224700A CN201910365934.8A CN201910365934A CN110224700A CN 110224700 A CN110224700 A CN 110224700A CN 201910365934 A CN201910365934 A CN 201910365934A CN 110224700 A CN110224700 A CN 110224700A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses a kind of high speed complementation type dual power supply operational amplifiers, comprising: differential input end recommends see-saw circuit, cascade amplifying circuit；Differential input end is connect with the differential input end for recommending see-saw circuit；The output end for recommending see-saw circuit is connect with the signal input part of cascade amplifying circuit.The present invention uses the two stage amplifer of differential-input differential output, recommend see-saw circuit and cascade amplifying circuit, differential signal, which passes sequentially through, recommends see-saw circuit and cascade amplifying circuit, so that operational amplifier can be improved the amplitude of oscillation of output signal, and there is high speed, large bandwidth, the beneficial effect of shorter foundation and retention time.
Description
Technical field
The invention belongs to integrated circuit fields, and in particular to a kind of high speed complementation type dual power supply operational amplifier.
Background technique
Operational amplifier is the key modules of high-speed high-precision flow line ADC, and the foundation of amplifier and retention time are also
One of important parameter of amplifier, for sampling hold circuit, settling time is particularly important, as pipeline ADC samples speed
After the raising of degree, especially video (Radio Frequency, abbreviation RF) sampling, operational amplifier settling time is wanted
It asks and has shortened to ps rank, serious challenge is brought to operational amplifier design person.Existing scheme generallys use time domain pilotaxitic texture
Improve whole ADC speed, but the ADC of this structure would generally introduce the mistake such as offset, gain, timing, bandwidth
Match, these mismatches limit the overall performance of ADC.
In conclusion existing operational amplifier also limits the whole of ADC while reducing foundation and retention time
Body performance is unable to satisfy current application demand.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of high speed complementation type dual power supply fortune
Calculate amplifier.The technical problem to be solved in the present invention is achieved through the following technical solutions:
A kind of high speed complementation type dual power supply operational amplifier, comprising:
Differential input end recommends see-saw circuit, cascade amplifying circuit；
The differential input end is connect with the differential input end for recommending see-saw circuit；
The output end for recommending see-saw circuit is connect with the signal input part of the cascade amplifying circuit.
In one embodiment of the invention, the see-saw circuit of recommending includes: described to recommend see-saw circuit
It include: PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube N2, power end VDD；
First differential signal Vin_N inputs the grid of the PMOS tube P1 and the NMOS tube N1 by the differential input end
Pole, the second differential signal Vin_P input the grid of the PMOS tube P2 and the NMOS tube N2 by the differential input end；
The drain electrode of the PMOS tube P1 and the PMOS tube P2, substrate are connect with the power end VDD；
The source electrode of the PMOS tube P1 and the PMOS tube P2 pass through output end vo ut1_N and output end vo ut1_P respectively
It exports to cascade amplifying circuit；
The drain electrode of the NMOS tube N1 and the NMOS tube N2 pass through output end vo ut1_N and output end vo ut1_P respectively
To cascade amplifying circuit.
In one embodiment of the invention, the cascade amplifying circuit is gain-boost Telescopic cascode
Amplifying circuit, comprising: common mode feedback circuit, bias voltage input Vbias, auxiliary OP AMP AMP_N, auxiliary OP AMP AMP_P,
PMOS tube P4, PMOS tube P5, PMOS tube P6, PMOS tube P7, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6；
The grid of the PMOS tube P3 and the output end of common mode feedback circuit connect, the drain electrode of the PMOS tube P3 and substrate
It is connect with the power end VDD, the source electrode of the PMOS tube P3 is connect with the drain electrode of the PMOS tube P4；
The PMOS tube P4, PMOS tube P5 substrate connect with the power end VDD, the PMOS tube P4, PMOS tube
The source electrode of P5 is connect with the input terminal AMP_P_IN+ of the auxiliary OP AMP AMP_P, input terminal AMP_P_IN- respectively, the PMOS
Pipe P4, PMOS tube P5 source electrode also connect respectively with the drain electrode of the PMOS tube P6, PMOS tube P7, PMOS tube P4, PMOS
The grid of pipe P5 is connect with the bias voltage input Vbias；
The PMOS tube P6, PMOS tube P7 grid respectively with the output terminals A MP_P_OUT+ of auxiliary OP AMP AMP_P, output
Hold AMP_P_OUT- connection, the PMOS tube P6, PMOS tube P7 source electrode pass through output end vo ut_N, output end vo ut_P respectively
Output, the substrate and the power end VDD of the PMOS tube P6, PMOS tube P7；
The NMOS tube N3, NMOS tube N4 grid respectively with the output end vo ut1_N for recommending negater circuit, output
Hold Vout1_P connection, the source electrode ground connection GND of the NMOS tube N3, NMOS tube N4, the substrate of the NMOS tube N3, NMOS tube N4
It is grounded GND, the input terminal AMP_N_IN with the auxiliary OP AMP AMP_N respectively that drains of the NMOS tube N3, NMOS tube N4
+, input terminal AMP_N_IN- connection；
The NMOS tube N5, NMOS tube N6 drain electrode respectively with the input terminal AMP_N_IN+ of the auxiliary OP AMP AMP_N,
Input terminal AMP_N_IN- connection, the NMOS tube N5, NMOS tube N6 substrate be grounded GND, the NMOS tube N5, NMOS tube
The grid of N6 is connect with the output terminals A MP_N_OUT+ of the auxiliary OP AMP AMP_N, output AMP_N_OUT- respectively；
The differential input end of the common mode feedback circuit is connect with output end vo ut_N, output end vo ut_P respectively.
In one embodiment of the invention, the auxiliary OP AMP AMP_N includes: bias voltage input Vbias, PMOS
Pipe P8, PMOS tube P9, PMOS tube P10, PMOS tube P11, NMOS tube N7, NMOS tube N8, NMOS tube N9, NMOS tube N10；
The drain electrode of the PMOS tube P8 is connect with the power end VDD, the source electrode of the PMOS tube P8 and the PMOS tube
The drain electrode of P10 connects, and the substrate of the PMOS tube P8 is connect with the power end VDD, the grid of the PMOS tube P8 with it is described
Voltage input end Vbias connection；
The drain electrode of the PMOS tube P9 is connect with power end VDD, and the source electrode of the PMOS tube P9 is with the PMOS tube P11's
Drain electrode connection, the substrate of the PMOS tube P9 are connect with the power end VDD, the grid of the PMOS tube P9 and the biased electrical
Press input terminal Vbias connection；
The source electrode of the PMOS tube P10 is exported by the output terminals A MP_N_OUT+ of auxiliary OP AMP AMP_N, the PMOS tube
The substrate of P10 is connect with the power end VDD, and the grid of the PMOS tube P10 and the bias voltage input Vbias connect
It connects；
The source electrode of the PMOS tube P11 is exported by output terminals A MP_N_OUT-, the substrate of the PMOS tube P11 with it is described
Power end VDD connection, the grid of the PMOS tube P11 are connect with the voltage input end Vbias；
The source electrode and substrate of the NMOS tube N7 is grounded GND, the source of NMOS tube the N7 drain electrode and the NMOS tube N9
Pole connection, the grid of the NMOS tube N7 are connect with the input terminal AMP_N_IN+ of the auxiliary OP AMP AMP_N；
The source electrode and substrate of the NMOS tube N8 is grounded GND, the source of NMOS tube the N8 drain electrode and the NMOS tube N10
Pole connection, the grid of the NMOS tube N8 are connect with the input terminal AMP_N_IN- of the auxiliary OP AMP AMP_N；
The drain electrode of the NMOS tube N9 is exported by the output terminals A MP_N_OUT+ of the auxiliary OP AMP AMP_N, described
The Substrate ground GND of NMOS tube N9, the grid of the NMOS tube N9 are connect with the bias voltage input Vbias；
The drain electrode of the NMOS tube N10 is exported by the output terminals A MP_N_OUT- of the auxiliary OP AMP AMP_N, described
The Substrate ground GND of NMOS tube N10, the grid of the NMOS tube N10 are connect with the bias voltage input Vbias.
In one embodiment of the invention, the auxiliary OP AMP AMP_P is cascode structure, comprising: bias voltage
Input terminal Vbias, PMOS tube P12, PMOS tube P13, PMOS tube P14, PMOS tube P15, NMOS tube N11, NMOS tube N12, NMOS
Pipe N13, NMOS tube N14；
The drain electrode of the PMOS tube P12 is connect with the power end VDD, the source electrode and the PMOS of the PMOS tube P12
The drain electrode of pipe P14 connects, and the substrate of the PMOS tube P12 is connect with the power end VDD, the grid of the PMOS tube P12 and
The bias voltage input Vbias connection；
The drain electrode of the PMOS tube P13 is connect with power end VDD, the source electrode of the PMOS tube P13 and the PMOS tube P15
Drain electrode connection, the substrate of the PMOS tube P13 connect with the power end VDD, the grid of the PMOS tube P13 with it is described inclined
Set voltage input end Vbias connection；
The source electrode of the PMOS tube P14 is exported by the output terminals A MP_P_OUT+ of auxiliary OP AMP AMP_P, the PMOS tube
The substrate of P14 is connect with the power end VDD, and the grid of the PMOS tube P14 and the bias voltage input Vbias connect
It connects；
The source electrode of the PMOS tube P15 is exported by output terminals A MP_P_OUT-, the substrate and power supply of the PMOS tube P15
VDD connection is held, the grid of the PMOS tube P15 is connect with the bias voltage input Vbias；
The source electrode and substrate of the NMOS tube N11 is grounded GND, and the NMOS tube N11 drain electrode is with the NMOS tube N13's
Source electrode connection, the grid of the NMOS tube N11 are connect with the input terminal AMP_P_IN+ of the auxiliary OP AMP AMP_P；
The source electrode and substrate of the NMOS tube N12 is grounded GND, and the NMOS tube N12 drain electrode is with the NMOS tube N14's
Source electrode connection, the grid of the NMOS tube N12 are connect with the input terminal AMP_P_IN- of the auxiliary OP AMP AMP_P；
The drain electrode of the NMOS tube N13 is exported by the output terminals A MP_P_OUT+ of auxiliary OP AMP AMP_P, the NMOS tube
The Substrate ground GND of N13, the grid of the NMOS tube N13 are connect with the bias voltage input Vbias；
The drain electrode of the NMOS tube N14 is exported by output terminals A MP_P_OUT-, the Substrate ground of the NMOS tube N14
GND, the grid of the NMOS tube N14 are connect with the bias voltage input Vbias.
In one embodiment of the invention, the gain-boost Telescopic cascode amplifying circuit further includes capacitor
C1, capacitor C2, resistance R1, resistance R2；
The capacitor C1 is connected between the grid of NMOS tube N3 and the PMOS tube P4；
The capacitor C2 is connected between the grid of NMOS tube N4 and the PMOS tube P5；
The resistance R1 is connected between PMOS tube P4 and the bias voltage input Vbias；
The resistance R2 is connected between PMOS tube P5 and the bias voltage input Vbias.
In one embodiment of the invention, the gain-boost Telescopic cascode amplifying circuit further includes capacitor
C3, capacitor C4, resistance R3, resistance R4, PMOS tube P41, PMOS tube P51；
The capacitor C3 is connected between the grid of NMOS tube N3 and the PMOS tube P4；
The capacitor C4 is connected between the grid of NMOS tube N4 and the PMOS tube P5；
The resistance R3 is connected between PMOS tube P4 and the bias voltage input Vbias；
The resistance R4 is connected between PMOS tube P4 and the bias voltage input Vbias；
The grid of the PMOS tube P41 is connect with the bias voltage input Vbias, the source electrode of the PMOS tube P41
It is connect with the input terminal AMP_P_IN+ of the auxiliary OP AMP AMP_P, the drain electrode of the PMOS tube P41 is with the PMOS tube P3's
Source electrode connection；
The grid of the PMOS tube P51 is connect with bias voltage input Vbias, the source electrode of the PMOS tube P51 with it is auxiliary
The input terminal AMP_P_IN- connection of amplifier AMP_P is helped, the drain electrode of the PMOS tube P51 is connect with the source electrode of the PMOS tube P3,
The substrate of the PMOS tube P51 is connect with the substrate of PMOS tube P41.
Beneficial effects of the present invention:
The present invention uses the two stage amplifer of differential-input differential output, that is, recommends see-saw circuit and cascade amplification
Circuit, differential signal, which passes sequentially through, recommends see-saw circuit and cascade amplifying circuit, and operational amplifier is mentioned
The amplitude of oscillation of high output signal, and have high speed, large bandwidth, the beneficial effect of shorter foundation and retention time.
The present invention is described in further details below with reference to accompanying drawings and embodiments.
Detailed description of the invention
Fig. 1 is a kind of schematic block diagram of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention；
Fig. 2 is that a kind of reverse phase of recommending of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention is amplified
Circuit structure diagram；
Fig. 3 is a kind of gain-boost set of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention
Cartridge type cascade amplification circuit structure schematic diagram；
Fig. 4 is a kind of auxiliary OP AMP AMP_ of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention
N circuit structure chart；
Fig. 5 is a kind of auxiliary OP AMP AMP_ of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention
P circuit structure diagram；
Fig. 6 is the circuit diagram of another high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention；
Fig. 7 is the circuit diagram of another high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Embodiment one:
Referring to Figure 1, Fig. 1 is a kind of frame of high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention
Diagram is intended to, including differential input end, recommends see-saw circuit, cascade amplifying circuit；It differential input end and recommends anti-
The differential input end of phase amplifying circuit connects；Recommend the output end and gain raising property Telescopic cascode of see-saw circuit
Amplifying circuit.
In a kind of implementation, recommending see-saw circuit includes: PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube
N2, power end VDD；First differential signal Vin_N by differential input end input PMOS tube P1 and NMOS tube N1 grid, second
Differential signal Vin_P inputs the grid of PMOS tube P2 and NMOS tube N2 by differential input end；PMOS tube P1's and PMOS tube P2
Drain electrode, substrate are connect with power end VDD；The source electrode of PMOS tube P1 and PMOS tube P2 pass through output end vo ut1_N and defeated respectively
Outlet Vout1_P is exported to cascade amplifying circuit；The drain electrode of NMOS tube N1 and NMOS tube N2 pass through output end respectively
Vout1_N and output end vo ut1_P is to cascade amplifying circuit.
Wherein, as shown in Fig. 2, in recommending see-saw circuit, the first differential signal Vin_N and the second differential signal
Vin_P is recommended in see-saw circuit by differential signal input input.When the voltage value of power end VDD and the first difference are believed
When the voltage value difference of number Vin_N is less than the threshold voltage vt h of PMOS tube P1, PMOS tube P2, PMOS tube P1 is closed, at this time PMOS
Pipe P1 is equal to the biggish load resistance of resistance value, NMOS transistor conduction, and the first differential signal Vin_N is from NMOS tube N1 grid stream
Enter, the first differential signal Vin_N amplifies after NMOS tube N1 obtains NMOS tube N1 output electric current In1, NMOS tube N1 output electricity
Stream In1 is sent to the source electrode of PMOS tube P1, generates voltage difference, recommends the output end vo ut1_N output of inverter circuit；Work as power supply
The voltage value difference of the voltage value and the first differential signal Vin_N of holding VDD is greater than the threshold voltage of PMOS tube P1, PMOS tube P2
When Vth, PMOS tube P1 conducting, NMOS tube N1 is closed, and identical with above-mentioned steps, NMOS tube is equivalent to load resistance, PMOS at this time
The source electrode of pipe P1 obtains output electric current Ip1, will output electric current Ip1 be sent to the drain electrode of NMOS tube N1 after generate pressure difference, from recommending
The output end vo ut1_N of inverter circuit is exported；When the voltage value of power end VDD and the voltage value of the first differential signal Vin_N
When difference is equal to the threshold voltage vt h of PMOS tube P1, PMOS tube P2, PMOS tube P1 and NMOS tube N1 are connected, at this time PMOS tube
Load resistance each other between P1 and NMOS tube N1, remaining process is identical as above-mentioned steps, repeats no more.Similarly the second differential signal
PMOS tube P2 and NMOS tube the N2 theory structure having the same of the side Vin_P, the second differential signal Vin_P pass through PMOS tube
P2, NMOS tube N2 amplification after, from recommend inverter circuit output end vo ut1_P export.Inverter cricuit is recommended at this time to obtain
Difference output is to gain-boost Telescopic cascode amplifying circuit.
In addition, as shown in figure 3, in embodiments of the present invention, cascade amplifying circuit is telescopic using gain-boost
Cascade amplifying circuit, comprising: common mode feedback circuit, bias voltage input Vbias, auxiliary OP AMP AMP_N, auxiliary OP AMP
AMP_P, PMOS tube P4, PMOS tube P5, PMOS tube P6, PMOS tube P7, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube
N6；The grid of PMOS tube P3 and the output end of common mode feedback circuit connect, and the drain electrode of PMOS tube P3 and substrate and power end VDD connect
It connects, the source electrode of PMOS tube P3 is connect with the drain electrode of PMOS tube P4；PMOS tube P4, PMOS tube P5 substrate with power end VDD connect
Connect, PMOS tube P4, PMOS tube P5 source electrode respectively with the input terminal AMP_P_IN+ of auxiliary OP AMP AMP_P, input terminal AMP_P_
IN- connection, PMOS tube P4, PMOS tube P5 source electrode also connect respectively with the drain electrode of PMOS tube P6, PMOS tube P7, PMOS tube P4,
The grid of PMOS tube P5 is connect with bias voltage input Vbias；PMOS tube P6, PMOS tube P7 grid respectively with auxiliary OP AMP
The output terminals A MP_P_OUT+ of AMP_P, output terminals A MP_P_OUT- connection, PMOS tube P6, PMOS tube P7 source electrode pass through respectively
Output end vo ut_N, output end vo ut_P output, PMOS tube P6, the substrate of PMOS tube P7 and power end VDD；NMOS tube N3,
The grid of NMOS tube N4 respectively with recommend the output end vo ut1_N of negater circuit, output end vo ut1_P is connect, NMOS tube N3,
Source electrode the ground connection GND, NMOS tube N3 of NMOS tube N4, the substrate of NMOS tube N4 are grounded GND, the leakage of NMOS tube N3, NMOS tube N4
Pole is connect with the input terminal AMP_N_IN+ of auxiliary OP AMP AMP_N, input terminal AMP_N_IN- respectively；NMOS tube N5, NMOS tube N6
Drain electrode connect respectively with the input terminal AMP_N_IN+ of auxiliary OP AMP AMP_N, input terminal AMP_N_IN-, NMOS tube N5, NMOS
The substrate of pipe N6 is grounded GND, NMOS tube N5, NMOS tube N6 grid respectively with the output terminals A MP_N_ of auxiliary OP AMP AMP_N
OUT+, output AMP_N_OUT- connection；The differential input end of common mode feedback circuit respectively with output end vo ut_N, output end
Vout_P connection.
It needs to be described in detail, the signal for recommending see-saw circuit output end vo ut1_N passes through the grid of NMOS tube N3
Pole input gain raising type Telescopic cascode amplifying circuit, since NMOS tube N3 is common-source amplifier, so through NMOS tube
The amplified current signal of N3 flows into the source electrode of NMOS tube N5 through the drain electrode of NMOS tube N3；NMOS tube N5 is cathode-input amplifier, is put
After current signal after big amplifies again via NMOS tube N5, current source load PMOS tube P6, PMOS tube P4 arrival are passed sequentially through
The source electrode of PMOS tube P3 amplifies via the current gain raising type Telescopic cascode that NMOS tube N5 amplifies again at the same time
The output end vo ut_N of circuit generates the first output voltage signal and from gain-boost Telescopic cascode amplifying circuit
Output end vo ut_N output；Similarly, the signal for recommending see-saw circuit output end vo ut1_P is increased by NMOS tube N4 input
Beneficial raising type Telescopic cascode amplifying circuit, respectively using current source load after NMOS tube N4, NMOS tube N6 amplification
PMOS tube P7, PMOS tube P5 are sent to PMOS tube P3, meanwhile, jacket cylinder is improved via the current gain that NMOS tube N6 amplifies again
The output end vo ut_P of formula cascade amplifying circuit generates the first output voltage signal and from the telescopic common source of gain-boost
The output end vo ut_P output of grid amplifying circuit altogether.The output end of auxiliary OP AMP AMP_N and auxiliary OP AMP AMP_P is NMOS tube
N5, NMOS tube N6, PMOS tube P6, PMOS tube P7 provide high gate source voltage Vgs, so that NMOS tube N5, NMOS tube N6, PMOS tube
Impedance increase that P6, PMOS tube P7 can be exported, gain improve, allow in this way two stage amplifer can obtain simultaneously high-gain,
The characteristic of high bandwidth.Specifically, through the amplified voltage signal of NMOS tube N3 via the input terminal AMP_N_ of auxiliary OP AMP AMP_N
IN+ inputs auxiliary OP AMP AMP_N, then the grid of NMOS tube N5 is flowed out to through output terminals A MP_N_OUT+；Similarly, through NMOS tube N4
Amplified voltage signal inputs auxiliary OP AMP AMP_N via the input terminal AMP_N_IN- of auxiliary OP AMP AMP_N, then through exporting
End AMP_N_OUT- flows out to the grid of NMOS tube N6；For auxiliary OP AMP AMP_P, the voltage amplified again by NMOS tube N5 is believed
Number auxiliary OP AMP AMP_N is inputted by the input terminal AMP_P_IN+ of auxiliary OP AMP AMP_N by PMOS tube P6, then passes through auxiliary
The output terminals A MP_N_OUT+ of amplifier AMP_N is exported to the grid of the P6 of PMOS tube；Similarly, amplified again by NMOS tube N6
Voltage signal inputs auxiliary OP AMP AMP_N by the input terminal AMP_P_IN- of auxiliary OP AMP AMP_N by PMOS tube P7, then leads to
The output terminals A MP_N_OUT- for crossing auxiliary OP AMP AMP_N is exported to the grid of the P7 of PMOS tube；Common mode feedback circuit makes gain
Each metal-oxide-semiconductor the operation is stable in raising type Telescopic cascode amplifying circuit.
Further instruction is needed, the NMOS tube N1 and PMOS tube P1 of see-saw circuit are recommended while inputting common mode
Signal guarantees that two metal-oxide-semiconductors all work at saturation region, so that gain maximizes, which has the characteristics that big bandwidth, more hold
Easily make time pole far from the dominant pole in gain-boost Telescopic cascode amplifying circuit, the entire amplifying circuit made obtains
Maximum bandwidth, and can be used in the amplifying circuit of high speed.
Embodiment two:
As shown in Figure 4, Figure 5, the application of auxiliary OP AMP AMP_N and auxiliary OP AMP AMP_P is so that NMOS tube N5, NMOS tube
The gate source voltage Vgs increase of N6, PMOS tube P6, PMOS tube P7, so that output impedance increases, gain improves, and due to increasing
Auxiliary OP AMP circuit is used in beneficial raising type Telescopic cascode amplifying circuit, so that entire operational amplifier circuit acquisition is maximum
Bandwidth can be used for the operational amplifier circuit in the amplifying circuit of high speed.
Embodiment three:
Fig. 6 is referred to, Fig. 6 is another high speed complementation type dual power supply operational amplifier provided in an embodiment of the present invention
Circuit diagram is recommended the amplified differential signal of see-saw circuit and is passed to gain-boost Telescopic cascode amplification electricity
Road is connected between the bias voltage input Vbias and PMOS tube P4 in gain-boost Telescopic cascode amplifying circuit
One resistance, and the series capacitance C1 between the grid of PMOS tube P4 and the grid of NMOS tube N3.By recommending reverse phase amplification electricity
The differential signal of road amplification is inputted by the differential input end of gain-boost Telescopic cascode amplifying circuit, when through amplifying
Voltage signal afterwards is respectively sent to NMOS tube from the output end vo ut1_N and output end vo ut1_P for recommending see-saw circuit
While N3 and NMOS tube N4, capacitor C1, capacitor C2 can be also respectively flowed through, so that capacitor C1, capacitor C2 generate the effect of blocking,
Small signal is added on bias voltage input Vbias, at this point, PMOS tube P4, PMOS tube P5 are equal to common-source amplifier, is increased at this time
Beneficial raising type Telescopic cascode amplifying circuit is formed working condition same as see-saw circuit is recommended, by biasing
Voltage input end Vbias, auxiliary OP AMP AMP_P, common mode feedback circuit, PMOS tube P3, PMOS tube P4, PMOS tube P5, PMOS tube
Part and remaining circuit part common source and common grid amplifier and the load current source each other of P6, PMOS tube P7.
Example IV:
In the present embodiment, Fig. 7 is referred to, Fig. 7 is the double electricity of another high speed complementation type provided in an embodiment of the present invention
The circuit diagram of source operational amplifier increases PMOS tube P41 and PMOS tube P51 on the basis of embodiment three in circuit, due to
Capacitor C1, capacitor C2 generate blocking effect, can change the distribution of circuit zero pole point, may make the reduction of current phase nargin, because
This, increases the PMOS tube P41 in parallel with the PMOS tube P4 and PMOS tube P51 in parallel with PMOS tube P5, and such structure can be with
Reduce the influence to poles and zeros assignment.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (7)
1. a kind of high speed complementation type dual power supply operational amplifier characterized by comprising
Differential input end recommends see-saw circuit, cascade amplifying circuit；
The differential input end is connect with the differential input end for recommending see-saw circuit；
The output end for recommending see-saw circuit is connect with the signal input part of the cascade amplifying circuit.
2. a kind of high speed complementation type dual power supply operational amplifier according to claim 1, which is characterized in that described to recommend
See-saw circuit includes: PMOS tube P1, PMOS tube P2, NMOS tube N1, NMOS tube N2, power end VDD；
First differential signal Vin_N inputs the grid of the PMOS tube P1 and the NMOS tube N1 by the differential input end,
Second differential signal Vin_P inputs the grid of the PMOS tube P2 and the NMOS tube N2 by the differential input end；
The drain electrode of the PMOS tube P1 and the PMOS tube P2, substrate are connect with the power end VDD；
The source electrode of the PMOS tube P1 and the PMOS tube P2 pass through output end vo ut1_N and output end vo ut1_P output respectively
To cascade amplifying circuit；
The drain electrode of the NMOS tube N1 and the NMOS tube N2 pass through output end vo ut1_N and output end vo ut1_P to altogether respectively
Source is total to grid amplifying circuit.
3. a kind of high speed complementation type dual power supply operational amplifier according to claim 1, which is characterized in that the common source
Grid amplifying circuit includes: common mode feedback circuit, bias voltage input Vbias, auxiliary OP AMP AMP_N, auxiliary OP AMP AMP_ altogether
P, PMOS tube P4, PMOS tube P5, PMOS tube P6, PMOS tube P7, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6；
The output end connection of the grid and common mode feedback circuit of the PMOS tube P3, the drain electrode of the PMOS tube P3 and substrate and institute
Power end VDD connection is stated, the source electrode of the PMOS tube P3 is connect with the drain electrode of the PMOS tube P4, PMOS tube P5；
The PMOS tube P4, PMOS tube P5 substrate connect with the power end VDD, the PMOS tube P4, PMOS tube P5
Source electrode is connect with the input terminal AMP_P_IN+ of the auxiliary OP AMP AMP_P, input terminal AMP_P_IN- respectively, the PMOS tube
P4, PMOS tube P5 source electrode also connect respectively with the drain electrode of the PMOS tube P6, PMOS tube P7, the PMOS tube P4, PMOS tube
The grid of P5 is connect with the bias voltage input Vbias；
The PMOS tube P6, PMOS tube P7 grid respectively with output terminals A MP_P_OUT+, the output end of auxiliary OP AMP AMP_P
AMP_P_OUT- connection, the PMOS tube P6, PMOS tube P7 source electrode to pass through output end vo ut_N, output end vo ut_P respectively defeated
Out, the substrate and the power end VDD of the PMOS tube P6, PMOS tube P7, the source electrode difference of the PMOS tube P6, PMOS tube P7
It is connect with the drain electrode of the NMOS tube N5, NMOS tube N6；
The NMOS tube N3, NMOS tube N4 grid respectively with output end vo ut1_N, the output end for recommending negater circuit
Vout1_P connection, the source electrode ground connection GND of the NMOS tube N3, NMOS tube N4, the NMOS tube N3, the substrate of NMOS tube N4 are equal
Be grounded GND, the NMOS tube N3, NMOS tube N4 drain electrode respectively with the input terminal AMP_N_IN+ of the auxiliary OP AMP AMP_N,
Input terminal AMP_N_IN- connection, the NMOS tube N3, NMOS tube N4 drain electrode also respectively with the NMOS tube N5, NMOS tube N6
Source electrode connection；
The NMOS tube N5, NMOS tube N6 source electrode respectively with the input terminal AMP_N_IN+ of the auxiliary OP AMP AMP_N, input
Hold AMP_N_IN- connection, the NMOS tube N5, NMOS tube N6 substrate be grounded GND, the NMOS tube N5, NMOS tube N6
Grid is connect with the output terminals A MP_N_OUT+ of the auxiliary OP AMP AMP_N, output AMP_N_OUT- respectively；
The differential input end of the common mode feedback circuit is connect with output end vo ut_N, output end vo ut_P respectively.
4. a kind of high speed complementation type dual power supply operational amplifier according to claim 3, which is characterized in that the auxiliary
Amplifier AMP_N includes: bias voltage input Vbias, PMOS tube P8, PMOS tube P9, PMOS tube P10, PMOS tube P11, NMOS
Pipe N7, NMOS tube N8, NMOS tube N9, NMOS tube N10；
The drain electrode of the PMOS tube P8, PMOS tube P9 are connect with the power end VDD, the source of the PMOS tube P8, PMOS tube P9
Pole is connect with the drain electrode of the PMOS tube P10, PMOS tube P11 respectively, the substrate and the electricity of the PMOS tube P8, PMOS tube P9
Source VDD connection, the PMOS tube P8, PMOS tube P9 grid connect with the voltage input end Vbias；
The PMOS tube P10, PMOS tube P11 source electrode pass through respectively the output terminals A MP_N_OUT+ of auxiliary OP AMP AMP_N, output
Hold AMP_N_OUT- output, the PMOS tube P10, PMOS tube P11 substrate connect with the power end VDD, the PMOS tube
P10, PMOS tube P11 grid connect with the bias voltage input Vbias, the source of the PMOS tube P10, PMOS tube P11
Pole is also connect with the drain electrode of NMOS tube N9, NMOS tube N10 respectively；
The NMOS tube N7, the source electrode of NMOS tube N8 and substrate are grounded GND, the drain electrode point of the NMOS tube N7, NMOS tube N8
It is not connect with the source electrode of the NMOS tube N9, NMOS tube N10, the NMOS tube N7, the grid of NMOS tube N8 and the auxiliary are transported
Put input terminal AMP_N_IN+, the input terminal AMP_N_IN- connection of AMP_N；
The NMOS tube N9, NMOS tube N10 drain electrode respectively by the output terminals A MP_N_OUT+ of the auxiliary OP AMP AMP_N,
Output terminals A MP_N_OUT- output, the Substrate ground GND, the NMOS tube N9, NMOS tube of the NMOS tube N9, NMOS tube N10
The grid of N10 is connect with the bias voltage input Vbias.
5. a kind of high speed complementation type dual power supply operational amplifier according to claim 3, which is characterized in that the auxiliary
Amplifier AMP_P is cascode structure, comprising: bias voltage input Vbias, PMOS tube P12, PMOS tube P13, PMOS tube
P14, PMOS tube P15, NMOS tube N11, NMOS tube N12, NMOS tube N13, NMOS tube N14；
The drain electrode of the PMOS tube P12, PMOS tube P13 are connect with the power end VDD, the PMOS tube P12, PMOS tube P13
Source electrode connect respectively with the drain electrode of the PMOS tube P14, PMOS tube P15, the PMOS tube P12, PMOS tube P13 substrate with
The power end VDD connection, the grid input with the auxiliary OP AMP AMP_P respectively of the PMOS tube P12, PMOS tube P13
Hold AMP_P_IN+, input terminal AMP_P_IN- connection；
The PMOS tube P14, PMOS tube P15 source electrode pass through output terminals A MP_P_OUT+, the output end of auxiliary OP AMP AMP_P
AMP_P_OUT- output, the source electrode also drain electrode with NMOS tube N13, NMOS tube N14 respectively of the PMOS tube P14, PMOS tube P15
Connection, the PMOS tube P14, PMOS tube P15 substrate connect with the power end VDD, the PMOS tube P14, PMOS tube P15
Grid connect with the bias voltage input Vbias；
The NMOS tube N11, the source electrode of NMOS tube N12 and substrate are grounded GND, the leakage of the NMOS tube N11, NMOS tube N12
Pole is connect with the source electrode of the NMOS tube N13, NMOS tube N14, the NMOS tube N11, the grid of NMOS tube N12 and the biasing
Voltage input end Vbias connection；
The drain electrode of the NMOS tube N13, NMOS tube N14 pass through output terminals A MP_P_OUT+, the output end of auxiliary OP AMP AMP_P
AMP_P_OUT+ output, the NMOS tube N13, the Substrate ground GND, the NMOS tube N13 of NMOS tube N14, NMOS tube N14
Grid is connect with the bias voltage input Vbias.
6. a kind of high speed complementation type dual power supply operational amplifier according to claim 5, which is characterized in that the gain
Raising type Telescopic cascode amplifying circuit further includes capacitor C1, capacitor C2, resistance R1, resistance R2；
The capacitor C1 is connected between the grid of NMOS tube N3 and the PMOS tube P4 grid；
The capacitor C2 is connected between the grid of NMOS tube N4 and the PMOS tube P5 grid；
The resistance R1 is connected between PMOS tube P4 grid and the bias voltage input Vbias；
The resistance R2 is connected between PMOS tube P5 grid and the bias voltage input Vbias.
7. a kind of high speed complementation type dual power supply operational amplifier according to claim 5, which is characterized in that the gain
Raising type Telescopic cascode amplifying circuit further includes capacitor C3, capacitor C4, resistance R3, resistance R4, PMOS tube P41, PMOS
Pipe P51；
The capacitor C3 is connected between the grid of NMOS tube N3 and the PMOS tube P4 grid；
The capacitor C4 is connected between the grid of NMOS tube N4 and the PMOS tube P5 grid；
The resistance R3 is connected between PMOS tube P4 grid and the bias voltage input Vbias；
The resistance R4 is connected between PMOS tube P4 grid and the bias voltage input Vbias；
The PMOS tube P41, PMOS tube P51 grid connect with the bias voltage input Vbias, the PMOS tube P41,
The source electrode of PMOS tube P51 is connect with the input terminal AMP_P_IN+ of the auxiliary OP AMP AMP_P, input terminal AMP_P_IN- respectively,
The drain electrode of the PMOS tube P41, PMOS tube P51 are connect with the source electrode of the PMOS tube P3, the substrate of the PMOS tube P41 with
The substrate of PMOS tube P51 connects.
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