CN103199807A - Split compensation two-stage operational amplifier based on inverter input structure - Google Patents

Abstract

The invention belongs to the technical field of electronics and relates to the frequency compensation technology of operational amplifiers in analog integrated circuits. The split compensation two-stage operational amplifier comprises a two-stage operational amplifier. A first-stage operational amplifier is composed of N-channel metal oxide semiconductor (NMOS) tubes (M1N, M2N, M3 and M4) and P-channel metal oxide semiconductor (PMOS) tubes (M1P, M2P and M0). A second-stage operational amplifier is composed of a PMOS tube M5P and an NMOS tube M5N. A traditional Miller capacitor is divided into a Cm1 portion and a Cm2 portion to finish frequency compensation of the operational amplifier. A first frequency compensation capacitor Cm1 is connected with the position between the output end of the first operational amplifier and the output end of the whole two-stage operational amplifier. A second frequency compensation capacitor Cm2 is connected with the position between a connection point of a source of the NMOS tube M2N and a drain of the NMOS tube M4 in the first-stage operational amplifier and the output end of the whole two-stage operational amplifier. The split compensation two-stage operational amplifier has strong robustness and higher unit grain bandwidth and output slew rate due to the fact that non-dominant poles and stray parameter are not related.

Description

Division compensation two-stage calculation amplifier based on the inverter input structure

Technical field

The invention belongs to electronic technology field, relate to the frequency compensation technology of the operational amplifier in the analog integrated circuit.

Background technology

Semiconductor and communication industry demand increase day by day, have accelerated the development of analog integrated circuit.Operational amplifier is widely used in band-gap reference, DC-DC converter and the data converter as important module in the analog integrated circuit.Operational amplifier commonly used comprises one-stage amplifier, two-stage calculation amplifier, three-stage operational amplifier.Two-stage calculation amplifier has obtained because of its higher gain and wideer output voltage swing using widely.Yet because two-stage calculation amplifier has two close low-frequency pole, therefore need carry out frequency compensation to it, two close low-frequency pole are pushed open.

The frequency compensation technology that two-stage calculation amplifier is commonly used is miller-compensated, its circuit structure as shown in Figure 1, it divides to make the stable output of operational amplifier by limit.Yet traditional is miller-compensated because miller capacitance C _mBi-directional path can produce RHP zero point, thereby reduce the unity gain bandwidth (GBW) of operational amplifier.

In order to eliminate the RHP zero point of traditional miller-compensated two-stage calculation amplifier, provided different solutions in the prior art: 1) as shown in Figure 2, at miller capacitance C _mResistance R of last series connection is eliminating RHP zero point, but the resistance that needs is bigger, and this need consume more chip area; 2) as shown in Figure 3, at a miller capacitance series connection voltage (or electric current) thus buffer is eliminated RHP zero point to destroy its bi-directional path, but this needs extra bias current, makes circuit structure more complicated; 3) cascade compensation (as shown in Figure 4), utilize the principle of current buffer the non-dominant pole of operational amplifier can be pushed to the position of higher frequency, and do not need extra bias current, but its performance parameter is relevant with the parasitic capacitance of first order output, reliability is lower.

Existing data searching utilizes tradition miller-compensated, also has data searching to utilize cascade to compensate to improve the performance of operational amplifier.But can improve the performance of operational amplifier at present, and the frequency compensation report with strong robustness is not checked and verify as yet.

Summary of the invention

In order to eliminate based on miller-compensated two-stage calculation amplifier intrinsic RHP zero point, the invention provides a kind of two-stage calculation amplifier that divides compensation.This operational amplifier adopts inverter input structure, has improved operational amplifier small-signal and large-signal performance on the basis of eliminating two-stage calculation amplifier intrinsic RHP zero point, has strong robustness.

Detailed technology scheme of the present invention is as follows:

Division compensation two-stage calculation amplifier based on the inverter input structure shown in Fig. 5,6, comprises two stage amplifer, and first order amplifier is managed M by NMOS _1N, M _2N, M ₃, M ₄With PMOS pipe M _1P, M _2P, M ₀Form, second level amplifier is managed M by PMOS _5PWith NMOS pipe M _5NForm.

In the first order amplifier, PMOS manages M ₀Source electrode meet power vd D, PMOS manages M ₀Grid meet NMOS pipe M ₃And M ₄Grid and NMOS pipe M _1NWith PMOS pipe M _1PDrain electrode, PMOS manages M ₀Drain electrode PMOS pipe M _1PAnd M _2PSource electrode; PMOS manages M _1PWith NMOS pipe M _1NGate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS manages M _2PWith NMOS pipe M _2NGate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS manages M _1PWith NMOS pipe M _1NDrain electrode interconnection, PMOS manages M _2PWith NMOS pipe M _2NDrain electrode interconnection and as the output of first order amplifier; NMOS manages M _1NSource electrode meet NMOS pipe M ₃Drain electrode, NMOS manages M _2NSource electrode meet NMOS pipe M ₄Drain electrode, NMOS manages M ₃And M ₄Source ground.

In the amplifier of the second level, PMOS manages M _5PSource electrode meet power vd D, PMOS manages M _5PWith NMOS pipe M _5NGate interconnection and connect the output of first order amplifier, PMOS manages M _5PWith NMOS pipe M _5NDrain electrode interconnection and as the output of whole two-stage calculation amplifier, NMOS manages M _5NSource ground.

Between the output of the output of first order amplifier and whole two-stage calculation amplifier, be connected with first frequency building-out capacitor C _M1NMOS pipe M in first order amplifier _2NSource electrode and NMOS pipe M ₄The drain electrode tie point and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _M2

The present invention is with traditional miller capacitance C _mBe split into C _M1And C _M2Two parts are finished the frequency compensation of fortune amplifier with this.The differential pair of first order amplifier is by inverter M _1NAnd M _1PForm.Current source is by the M that is operated in linear zone and critical saturation region ₀Form.M0, M3, the grid of M4 and M _1NAnd M _1PDrain electrode link to each other, form auto bias circuit.Second level amplifier is managed M by PMOS _5PWith NMOS pipe M _5NForm the inverter input structure.

The present invention has following characteristics:

1, C _M2The resistance of ordering with A can form a left half-plane and compensate the negative that non-dominant pole produces zero point and move.

2, operational amplifier of the present invention adopts the automatic biasing technology, does not need extra biasing circuit.Auto bias circuit can suppress PVT (process, voltage, influence temperature) of circuit.For example, if VDD increase, then V _GS0Increase bias current I ₁Increase, then the B point voltage increases, simultaneously V _GS0Reduce, offsetting VDD with this increases the influence that brings to circuit.

3, operational amplifier of the present invention time limit and parasitic capacitance are irrelevant, have stronger robustness.

4, current source M ₀Be operated in linear zone, in the large-signal transfer process, can provide big electric current, improve the Slew Rate of circuit.

5, the inverter input structure is all adopted in the input of the two-stage of operational amplifier of the present invention, can increase the mutual conductance of operational amplifier, can improve gain and the unity gain bandwidth of operational amplifier.

Description of drawings

Fig. 1 is miller-compensated two-stage calculation amplifier circuit structure signal in the prior art.

Fig. 2 is the miller-compensated two-stage calculation amplifier circuit structure signal that adds series resistance in the prior art.

Fig. 3 is the miller-compensated two-stage calculation amplifier circuit structure signal that adds the series voltage buffer in the prior art.

Fig. 4 is the two-stage calculation amplifier circuit structure signal of folded common source and common grid compensation in the prior art.

Fig. 5 is the two-stage calculation amplifier circuit structure signal of division compensation provided by the invention.

Fig. 6 is the division compensation two-stage calculation amplifier physical circuit figure based on the inverter input structure provided by the invention.

Fig. 7 is the division compensation two-stage calculation amplifier small-signal equivalent circuit based on the inverter input structure provided by the invention.

Embodiment

Division compensation two-stage calculation amplifier based on the inverter input structure shown in Fig. 5,6, comprises two stage amplifer, and first order amplifier is managed M by NMOS _1N, M _2N, M ₃, M ₄With PMOS pipe M _1P, M _2P, M ₀Form, second level amplifier is managed M by PMOS _5PWith NMOS pipe M _5NForm.

In the first order amplifier, PMOS manages M ₀Source electrode meet power vd D, PMOS manages M ₀Grid meet NMOS pipe M ₃And M ₄Grid and NMOS pipe M _1NWith PMOS pipe M _1PDrain electrode, PMOS manages M ₀Drain electrode PMOS pipe M _1PAnd M _2PSource electrode; PMOS manages M _1PWith NMOS pipe M _1NGate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS manages M _2PWith NMOS pipe M _2NGate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS manages M _1PWith NMOS pipe M _1NDrain electrode interconnection, PMOS manages M _2PWith NMOS pipe M _2NDrain electrode interconnection and as the output of first order amplifier; NMOS manages M _1NSource electrode meet NMOS pipe M ₃Drain electrode, NMOS manages M _2NSource electrode meet NMOS pipe M ₄Drain electrode, NMOS manages M ₃And M ₄Source ground.

In the amplifier of the second level, PMOS manages M _5PSource electrode meet power vd D, PMOS manages M _5PWith NMOS pipe M _5NGate interconnection and connect the output of first order amplifier, PMOS manages M _5PWith NMOS pipe M _5NDrain electrode interconnection and as the output of whole two-stage calculation amplifier, NMOS manages M _5NSource ground.

Between the output of the output of first order amplifier and whole two-stage calculation amplifier, be connected with first frequency building-out capacitor C _M1NMOS pipe M in first order amplifier _2NSource electrode and NMOS pipe M ₄The drain electrode tie point and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _M2

The present invention is with traditional miller capacitance C _mBe split into C _M1And C _M2Two parts are finished the frequency compensation of fortune amplifier with this.The differential pair of first order amplifier is by inverter M _1NAnd M _1PForm.Current source is by the M that is operated in linear zone and critical saturation region ₀Form.M0, M3, the grid of M4 and M _1NAnd M _1PDrain electrode link to each other, form auto bias circuit.Second level amplifier is managed M by PMOS _5PWith NMOS pipe M _5NForm the inverter input structure.

The small-signal equivalent circuit of operational amplifier of the present invention as shown in Figure 7.Analyze its equivalent electric circuit, the small-signal transfer function is:

$A_{v-\mathrm{open}}=\frac{A_{\mathrm{dc}}(1+s\frac{(g_{m1N}+{\mathrm{<figure-callout\; id="1P"\; label="g\; m"\; filenames="HDA00002967439800023.png"\; state="\{\{state\}\}">g</figure-callout>}}_m)C_{m2}}{g_{m1}{g}_{\mathrm{me}}}-s^2\frac{g_{m1N}{C}_{m1}{C}_{m2}}{g_{m1}{g}_{\mathrm{me}}{g}_{m2}})}{(1+\frac{s}{p_{-3\mathrm{dB}}})(1+s\frac{C_{m1}(g_{\mathrm{me}}{C}_L+g_{m2}{C}_{m2})}{g_{m2}{g}_{\mathrm{me}}{C}_{\mathrm{me}}}+s^2\frac{C_{m1}{C}_{m2}{C}_L}{g_{\mathrm{me}}{g}_{m2}{C}_{\mathrm{me}}})}---\left(1\right)$

Wherein:

g _me=g _m1N+g _o4+g _o1N (2)

$g_{m1}=\frac{{\mathrm{<figure-callout\; id="1P"\; label="g\; m"\; filenames="HDA00002967439800023.png"\; state="\{\{state\}\}">g</figure-callout>}}_m{g}_{m1N}+{\mathrm{<figure-callout\; id="1P"\; label="g\; m"\; filenames="HDA00002967439800023.png"\; state="\{\{state\}\}">g</figure-callout>}}_m{g}_{o4}+g_{m1N}{g}_{o4}}{g_{m1N}+g_{o4}+g_{o1N}}---\left(3\right)$

$C_{\mathrm{me}}=C_{m1}+C_{m2}\frac{g_{m1N}}{g_{\mathrm{me}}}---\left(4\right)$

A _dc=g _m1R ₁g _m2R ₂ (5)

$p_{-3\mathrm{dB}}=-\frac{1}{C_{\mathrm{me}}{R}_1{g}_{m2}{R}_2}---\left(6\right)$

g _M2=g _M5N+ g _M5P, R ₁≈ R _1N, R ₂=R _5N//R _5P.g _M1, g _M2It is the equivalent transconductance of first and second grade amplifier.g _MeThe equivalent admittance that expression A is ordered, C _MeRepresent the miller capacitance of equivalence, C _LThe expression equivalent load capacitance.A _DcAnd p _-3dBRepresent DC current gain and the dominant pole of operational amplifier respectively.

The non-dominant pole that can draw operational amplifier of the present invention from (1) is:

$p_{\mathrm{nd}\mathrm{1,2}}=-\frac{g_{\mathrm{me}}{C_L}^{\&prime;}}{2C_L{C}_{m2}}(1\&PlusMinus;j\sqrt{\frac{4g_{m2}{C}_{\mathrm{me}}{C}_{m2}{C}_L}{g_{\mathrm{me}}{C_L}^{\&prime;2}{C}_{m1}}}-1)---\left(10\right)$

Wherein

${C_L}^{\&prime;}=C_L+\frac{C_{m2}{g}_{m2}}{g_{\mathrm{me}}}---\left(11\right)$

From (10) formula as can be seen, the non-dominant pole of operational amplifier of the present invention and parasitic parameter are irrelevant, therefore have stronger robustness.

From (4) as can be seen, the equivalent miller capacitance of operational amplifier of the present invention is not two miller capacitance sums, and less than two miller capacitance sums.

The unity gain bandwidth of operational amplifier of the present invention (GBW) and Slew Rate (SR) are:

$\mathrm{GBW}=\frac{g_{m1}}{C_{\mathrm{me}}}---\left(12\right)$

$\mathrm{SR}=\frac{I_1}{C_{\mathrm{me}}}---\left(13\right)$

From (12), (13) formula as can be seen because equivalent miller capacitance diminishes, GBW and the SR of operational amplifier of the present invention all are improved.

Claims (1)

1. based on the division compensation two-stage calculation amplifier of inverter input structure, comprise two stage amplifer, first order amplifier is managed M by NMOS _1N, M _2N, M ₃, M ₄With PMOS pipe M _1P, M _2P, M ₀Form, second level amplifier is managed M by PMOS _5PWith NMOS pipe M _5NForm;

In the first order amplifier, PMOS manages M ₀Source electrode meet power vd D, PMOS manages M ₀Grid meet NMOS pipe M ₃And M ₄Grid and NMOS pipe M _1NWith PMOS pipe M _1PDrain electrode, PMOS manages M ₀Drain electrode PMOS pipe M _1PAnd M _2PSource electrode; PMOS manages M _1PWith NMOS pipe M _1NGate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS manages M _2PWith NMOS pipe M _2NGate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS manages M _1PWith NMOS pipe M _1NDrain electrode interconnection, PMOS manages M _2PWith NMOS pipe M _2NDrain electrode interconnection and as the output of first order amplifier; NMOS manages M _1NSource electrode meet NMOS pipe M ₃Drain electrode, NMOS manages M _2NSource electrode meet NMOS pipe M ₄Drain electrode, NMOS manages M ₃And M ₄Source ground;

In the amplifier of the second level, PMOS manages M _5PSource electrode meet power vd D, PMOS manages M _5PWith NMOS pipe M _5NGate interconnection and connect the output of first order amplifier, PMOS manages M _5PWith NMOS pipe M _5NDrain electrode interconnection and as the output of whole two-stage calculation amplifier, NMOS manages M _5NSource ground;

Between the output of the output of first order amplifier and whole two-stage calculation amplifier, be connected with first frequency building-out capacitor C _M1NMOS pipe M in first order amplifier _2NSource electrode and NMOS pipe M ₄The drain electrode tie point and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _M2

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