CN103199807B - Division based on inverter input structure compensates two-stage calculation amplifier - Google Patents

Abstract

The invention belongs to electronic technology field, relate to the frequency acquisition and tracking of operational amplifier in analog integrated circuit.Comprise two stage amplifer, first order amplifier is by NMOS tube M _1N, M _2N, M ₃, M ₄with PMOS M _1P, M _2P, M ₀composition, second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition.The present invention is by traditional miller capacitance C _mbe split into C _m1and C _m2two parts, complete the frequency compensation of operational amplifier with this; Wherein first frequency building-out capacitor C _m1be connected between the output of first order amplifier and the output of whole two-stage calculation amplifier, second frequency building-out capacitor C _m2be connected to NMOS tube M in first order amplifier _2Nsource electrode and NMOS tube M ₄drain junction and the output of whole two-stage calculation amplifier between.The non-dominant pole of the present invention and parasitic parameter have nothing to do, and have stronger robustness, have higher unity gain bandwidth simultaneously and export Slew Rate.

Description

Division based on inverter input structure compensates two-stage calculation amplifier

Technical field

The invention belongs to electronic technology field, relate to the frequency acquisition and tracking of the operational amplifier in analog integrated circuit.

Background technology

Semiconductor and communication industry demand increase day by day, accelerate the development of analog integrated circuit.Operational amplifier is widely used in band-gap reference, DC-DC converter and data converter as an important module in analog integrated circuit.Conventional operational amplifier comprises one-stage amplifier, two-stage calculation amplifier, three-stage operational amplifier.Two-stage calculation amplifier is widely used because of its higher gain and wider output voltage swing.But there are two close low-frequency pole due to two-stage calculation amplifier, therefore need to carry out frequency compensation to it, two close low-frequency pole are pushed open.

The frequency acquisition and tracking that two-stage calculation amplifier is conventional is miller-compensated, and as shown in Figure 1, it is divided by limit and makes that operational amplifier is stable to be exported its circuit structure.But it is traditional miller-compensated because miller capacitance C _mbi-directional path can produce a Right-half-plant zero, thus reduce the unity gain bandwidth (GBW) of operational amplifier.

In order to eliminate the Right-half-plant zero of traditional miller-compensated two-stage calculation amplifier, give different solutions in prior art: 1) as shown in Figure 2, at miller capacitance C _mupper series connection resistance R is to eliminate Right-half-plant zero, but the resistance needed is comparatively large, and this needs to consume more chip area; 2) as shown in Figure 3, voltage (or electric current) buffer that miller capacitance is connected is to destroy its bi-directional path thus to eliminate Right-half-plant zero, but this needs extra bias current, makes circuit structure more complicated; 3) cascade compensation (as shown in Figure 4), utilize the principle of current buffer the non-dominant pole of operational amplifier can be pushed to the position of higher frequency, and do not need extra bias current, but its performance parameter is relevant to the parasitic capacitance that the first order exports, and reliability is lower.

Existing data searching utilizes tradition miller-compensated, also has data searching to utilize cascade compensation to improve the performance of operational amplifier.But the performance of operational amplifier can be improved at present, and the frequency compensation report with strong robustness is not yet checked and verify.

Summary of the invention

In order to eliminate based on the intrinsic Right-half-plant zero of miller-compensated two-stage calculation amplifier, the invention provides a kind of two-stage calculation amplifier dividing compensation.This operational amplifier adopts inverter input structure, the basis of eliminating the intrinsic Right-half-plant zero of two-stage calculation amplifier improves operational amplifier small-signal and large-signal performance, has strong robustness.

Detailed technology scheme of the present invention is as follows:

Division based on inverter input structure compensates two-stage calculation amplifier, and as shown in Figure 5,6, comprise two stage amplifer, first order amplifier is by NMOS tube M _1N, M _2N, M ₃, M ₄with PMOS M _1P, M _2P, M ₀composition, second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition.

In first order amplifier, PMOS M ₀source electrode meet power vd D, PMOS M ₀grid meet NMOS tube M ₃and M ₄grid and NMOS tube M _1Nwith PMOS M _1Pdrain electrode, PMOS M ₀drain electrode PMOS M _1Pand M _2Psource electrode; PMOS M _1Pwith NMOS tube M _1Ngate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS M _2Pwith NMOS tube M _2Ngate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS M _1Pwith NMOS tube M _1Ndrain interconnection, PMOS M _2Pwith NMOS tube M _2Ndrain interconnection and as the output of first order amplifier; NMOS tube M _1Nsource electrode meet NMOS tube M ₃drain electrode, NMOS tube M _2Nsource electrode meet NMOS tube M ₄drain electrode, NMOS tube M ₃and M ₄source ground.

In the amplifier of the second level, PMOS M _5Psource electrode meet power vd D, PMOS M _5Pwith NMOS tube M _5Ngate interconnection and connect the output of first order amplifier, PMOS M _5Pwith NMOS tube M _5Ndrain interconnection and as the output of whole two-stage calculation amplifier, NMOS tube M _5Nsource ground.

First frequency building-out capacitor C is connected with between the output and the output of whole two-stage calculation amplifier of first order amplifier _m1; NMOS tube M in first order amplifier _2Nsource electrode and NMOS tube M ₄drain junction and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _m2.

The present invention is by traditional miller capacitance C _mbe split into C _m1and C _m2two parts, have carried out the frequency compensation of fortune amplifier with this.The differential pair of first order amplifier is by inverter M _1Nand M _1Pcomposition.Current source is by the M being operated in linear zone and critical statisfaction district ₀composition.The grid of M0, M3, M4 and M _1Nand M _1Pdrain electrode be connected, composition auto bias circuit.Second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition inverter input structure.

The present invention has following characteristics:

1, C _m2a Left half-plane can be formed with the resistance of A point to compensate the negative that non-dominant pole produces zero point and move.

2, operational amplifier of the present invention adopts automatic biasing technology, does not need extra biasing circuit.Auto bias circuit can suppress the impact of the PVT (process, voltage, temperature) of circuit.Such as, if VDD increases, then V _gS0increase, bias current I ₁increase, then B point voltage increases, simultaneously V _gS0reduce, offsetting VDD with this increases the impact brought to circuit.

3, operational amplifier of the present invention time limit and parasitic capacitance have nothing to do, and have stronger robustness.

4, current source M ₀be operated in linear zone, in large-signal transfer process, can larger current be provided, improve the Slew Rate of circuit.

5, the two-stage input of operational amplifier of the present invention all adopts inverter input structure, can increase the mutual conductance of operational amplifier, can improve gain and the unity gain bandwidth of operational amplifier.

Accompanying drawing explanation

Fig. 1 is miller-compensated two-stage calculation amplifier circuit structure signal in prior art.

Fig. 2 is the miller-compensated two-stage calculation amplifier circuit structure signal adding series resistance in prior art.

Fig. 3 is the miller-compensated two-stage calculation amplifier circuit structure signal adding series voltage buffer in prior art.

Fig. 4 is the two-stage calculation amplifier circuit structure signal that in prior art, folded common source and common grid compensates.

Fig. 5 is the two-stage calculation amplifier circuit structure signal that division provided by the invention compensates.

Fig. 6 is that the division based on inverter input structure provided by the invention compensates two-stage calculation amplifier physical circuit figure.

Fig. 7 is that the division based on inverter input structure provided by the invention compensates two-stage calculation amplifier small-signal equivalent circuit.

Embodiment

Division based on inverter input structure compensates two-stage calculation amplifier, and as shown in Figure 5,6, comprise two stage amplifer, first order amplifier is by NMOS tube M _1N, M _2N, M ₃, M ₄with PMOS M _1P, M _2P, M ₀composition, second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition.

In first order amplifier, PMOS M ₀source electrode meet power vd D, PMOS M ₀grid meet NMOS tube M ₃and M ₄grid and NMOS tube M _1Nwith PMOS M _1Pdrain electrode, PMOS M ₀drain electrode PMOS M _1Pand M _2Psource electrode; PMOS M _1Pwith NMOS tube M _1Ngate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS M _2Pwith NMOS tube M _2Ngate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS M _1Pwith NMOS tube M _1Ndrain interconnection, PMOS M _2Pwith NMOS tube M _2Ndrain interconnection and as the output of first order amplifier; NMOS tube M _1Nsource electrode meet NMOS tube M ₃drain electrode, NMOS tube M _2Nsource electrode meet NMOS tube M ₄drain electrode, NMOS tube M ₃and M ₄source ground.

In the amplifier of the second level, PMOS M _5Psource electrode meet power vd D, PMOS M _5Pwith NMOS tube M _5Ngate interconnection and connect the output of first order amplifier, PMOS M _5Pwith NMOS tube M _5Ndrain interconnection and as the output of whole two-stage calculation amplifier, NMOS tube M _5Nsource ground.

First frequency building-out capacitor C is connected with between the output and the output of whole two-stage calculation amplifier of first order amplifier _m1; NMOS tube M in first order amplifier _2Nsource electrode and NMOS tube M ₄drain junction and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _m2.

The present invention is by traditional miller capacitance C _mbe split into C _m1and C _m2two parts, have carried out the frequency compensation of fortune amplifier with this.The differential pair of first order amplifier is by inverter M _1Nand M _1Pcomposition.Current source is by the M being operated in linear zone and critical statisfaction district ₀composition.The grid of M0, M3, M4 and M _1Nand M _1Pdrain electrode be connected, composition auto bias circuit.Second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition inverter input structure.

The small-signal equivalent circuit of operational amplifier of the present invention as shown in Figure 7.Analyze its equivalent electric circuit, small-signal transfer function is:

$A_{\mathrm{\ν}-open}=\frac{A_{dc}(1+s\frac{(g_{m1N}+g_{m1P})C_{m2}}{g_{m1}{g}_{me}}-s^2\frac{g_{m1N}{C}_{m1}{C}_{m2}}{g_{m1}{g}_{me}{g}_{m2}})}{(1+\frac{s}{p_{-3dB}})(1+s\frac{C_{m1}(g_{me}{C}_L+g_{m2}{C}_{m2})}{g_{m2}{g}_{me}{C}_{me}}+s^2\frac{C_{m1}{C}_{m2}{C}_L}{g_{me}{g}_{m2}{C}_{me}})}---\left(1\right)$

Wherein:

g _me＝g _m1N+g _o4+g _o1N(2)

$g_{m1}=\frac{g_{m1P}{g}_{m1N}+g_{m1P}{g}_{o4}+g_{m1N}{g}_{o4}}{g_{m1N}+g_{o4}+g_{o1N}}---\left(3\right)$

$C_{me}=C_{m1}+C_{m2}\frac{g_{m1N}}{g_{me}}---\left(4\right)$

A _dc＝g _m1R ₁g _m2R ₂(5)

$p_{-3dB}=-\frac{1}{C_{me}{R}_1{g}_{m2}{R}_2}---\left(6\right)$

g _m2＝g _m5N+g _m5P,R ₁≈R _1N,R ₂＝R _5N//R _5P。G _m1, g _m2it is the equivalent transconductance of first and second grade of amplifier.G _merepresent the equivalent admittance of A point, C _merepresent the miller capacitance of equivalence, C _lrepresent equivalent load capacitance.A _dcand p _-3dBrepresent DC current gain and the dominant pole of operational amplifier respectively.

Can show that the non-dominant pole of operational amplifier of the present invention is from (1):

$p_{nd1,2}=-\frac{g_{me}{C_L}^{\′}}{2C_L{C}_{m2}}(1\±j\sqrt{\frac{4g_{m2}{C}_{me}{C}_{m2}{C}_L}{g_{me}{C_L}^{\′2}{C}_{m1}}-1})---\left(10\right)$

Wherein

${C_L}^{\′}=C_L+\frac{C_{m2}{g}_{m2}}{g_{me}}---\left(11\right)$

As can be seen from (10) formula, the non-dominant pole of operational amplifier of the present invention and parasitic parameter have nothing to do, and therefore have stronger robustness.

As can be seen from (4), the equivalent miller capacitance of operational amplifier of the present invention is not two miller capacitance sums, and is less than two miller capacitance sums.

Unity gain bandwidth (GBW) and the Slew Rate (SR) of operational amplifier of the present invention are:

$GBW=\frac{g_{m1}}{C_{me}}---\left(12\right)$

$SR=\frac{I_1}{C_{me}}---\left(13\right)$

From (12), (13) formula can be found out, because equivalent miller capacitance diminishes, GBW and SR of operational amplifier of the present invention is all improved.

Claims (1)

1. the division based on inverter input structure compensates two-stage calculation amplifier, and comprise two stage amplifer, first order amplifier is by NMOS tube M _1N, M _2N, M ₃, M ₄with PMOS M _1P, M _2P, M ₀composition, second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition;

In first order amplifier, PMOS M ₀source electrode meet power vd D, PMOS M ₀grid meet NMOS tube M ₃and M ₄grid and NMOS tube M _1Nwith PMOS M _1Pdrain electrode, PMOS M ₀drain electrode PMOS M _1Pand M _2Psource electrode; PMOS M _1Pwith NMOS tube M _1Ngate interconnection and as the reverse input end of whole two-stage calculation amplifier, PMOS M _2Pwith NMOS tube M _2Ngate interconnection and as the positive input of whole two-stage calculation amplifier; PMOS M _1Pwith NMOS tube M _1Ndrain interconnection, PMOS M _2Pwith NMOS tube M _2Ndrain interconnection and as the output of first order amplifier; NMOS tube M _1Nsource electrode meet NMOS tube M ₃drain electrode, NMOS tube M _2Nsource electrode meet NMOS tube M ₄drain electrode, NMOS tube M ₃and M ₄source ground;

In the amplifier of the second level, PMOS M _5Psource electrode meet power vd D, PMOS M _5Pwith NMOS tube M _5Ngate interconnection and connect the output of first order amplifier, PMOS M _5Pwith NMOS tube M _5Ndrain interconnection and as the output of whole two-stage calculation amplifier, NMOS tube M _5Nsource ground;

First frequency building-out capacitor C is connected with between the output and the output of whole two-stage calculation amplifier of first order amplifier _m1; NMOS tube M in first order amplifier _2Nsource electrode and NMOS tube M ₄drain junction and the output of whole two-stage calculation amplifier between be connected with second frequency building-out capacitor C _m2.