CN102130659A - Circuit structure for reducing input offset voltage of two-stage operational amplifier - Google Patents
Circuit structure for reducing input offset voltage of two-stage operational amplifier Download PDFInfo
- Publication number
- CN102130659A CN102130659A CN 201110009728 CN201110009728A CN102130659A CN 102130659 A CN102130659 A CN 102130659A CN 201110009728 CN201110009728 CN 201110009728 CN 201110009728 A CN201110009728 A CN 201110009728A CN 102130659 A CN102130659 A CN 102130659A
- Authority
- CN
- China
- Prior art keywords
- pmos pipe
- pipe
- circuit
- pmos
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention provides a circuit structure for reducing input offset voltage of a two-stage operational amplifier, which comprises a switching control circuit, a first-stage differential amplification circuit, a second-stage common-source amplification circuit and a compensation network, wherein the output end of the switching control circuit is connected with the input end of the first-stage differential amplification circuit, the output end of the first-stage differential amplification circuit is connected with the input end of the second-stage common-source amplification circuit, and the compensation network is further connected between the input end and the output end of the second-stage common-source amplification circuit. The circuit structure has the benefits that the offset of the operational amplifier is reduced by adopting an MOS (metal oxide semiconductor) switching tube to control and exchange signals at the positive and the negative input ends and the signals at the output end of the operational amplifier; as only the MOS switching tube is increased in the circuit, the circuit structure only needs very small area and very low power consumption; and the circuit does not affect the gain of the operational amplifier, the phase margin, the power supply voltage rejection ratio, the common-mode input range and other performance indexes while reducing the input offset voltage of the operational amplifier, and can be applied in mainstream CMOS (complementary metal oxide semiconductor) circuit systems.
Description
Technical field
The invention belongs to the Microelectronics and Solid State Electronics technical field, relate to a kind of operation amplifier circuit of integrated circuit, be specifically related to a kind of circuit structure that reduces the two-stage calculation amplifier input offset voltage.
Background technology
Operational amplifier is widely used in analog circuit and the Digital Analog Hybrid Circuits.Because the CMOS technology has become the mainstream technology of integrated circuit, compares with traditional double polar form circuit, the cmos operational amplifier circuit has significant advantage at cost with on the construction cycle.The existing operational amplification offset voltage circuit mentality of designing that reduces realizes for adopting wave chopping technology and automatic zero set technology, but wave chopping technology need be with input signal and the coupling of switching mode square-wave signal, after synchronous demodulation and low-pass filtering, obtain non-linear little signal again, circuit complexity increases, and can obviously increase circuit area; The automatic zero set technology will be stored in imbalance in the electric capacity, mainly contains input imbalance storage and output imbalance storage, mainly is applicable to discrete signal circuit such as switching capacity.Therefore compatibility and the circuit structure that reduces to lack of proper care that do not reduce other performances of amplifier have great importance mutually to design technology and CMOS technology.
Summary of the invention
The purpose of this invention is to provide a kind of circuit structure that reduces the operational amplifier input offset voltage, to reduce existing CMOS integrated transporting discharging input offset voltage.
The technical solution adopted in the present invention is that a kind of circuit structure that reduces the two-stage calculation amplifier input offset voltage comprises exchange control circuit, first order differential amplifier circuit, second level common source amplifying circuit and compensating network; The output of exchange control circuit is connected with the input of first order differential amplifier circuit, the output of first order differential amplifier circuit is connected with the input of second level common source amplifying circuit, also is connected with compensating network between the input of second level common source amplifying circuit and the output.
Wherein, the exchange control circuit is made of 4 PMOS pipes, is respectively: the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe and the tenth PMOS pipe; The source termination input signal in1 of the 7th PMOS pipe and the 8th PMOS pipe, the source termination input signal in2 of the 9th PMOS pipe and the tenth PMOS pipe; The grid of the 8th PMOS pipe and the 9th PMOS pipe meets control signal ck1 respectively, and the grid of the 7th PMOS pipe and the tenth PMOS pipe meets control signal ck2 respectively; The 8th PMOS pipe is connected with the drain terminal of the tenth PMOS pipe, and its output signal is ea1; The 7th PMOS pipe is connected with the drain terminal of the 9th PMOS pipe, and its output signal is ea2.
Wherein, first order differential amplifier circuit comprises NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe and the 6th PMOS pipe; Second level common source amplifying circuit comprises the 7th PMOS pipe; Compensating network comprises the zero suppression resistance and the building-out capacitor of series connection; The one PMOS pipe, the 2nd PMOS pipe and the 7th PMOS pipe three's source end is connected and connects operating voltage; The one PMOS pipe is connected with the grid of the 2nd PMOS pipe; The drain terminal of the one PMOS pipe is connected with the source end of a NMOS pipe through output out1, and the drain terminal of the 2nd PMOS pipe is connected with the source end of the 2nd NMOS pipe through output out2; The grid of the one NMOS pipe and the 2nd NMOS pipe meets the output signal e a1 of exchange control circuit and the output signal e a2 of exchange control circuit respectively, and NMOS pipe is connected with the drain terminal of the 2nd NMOS pipe and is connected with the source end of the 3rd NMOS pipe simultaneously; The 3rd NMOS pipe, the 5th NMOS pipe are connected with the grid of the 4th NMOS pipe, and the 3rd NMOS pipe, the 5th NMOS pipe are connected with the drain terminal of the 4th NMOS pipe and ground connection; The source end of the 5th NMOS pipe is connected with grid, and connects operating voltage simultaneously; The source end of the 3rd PMOS pipe and the 4th PMOS pipe connects the grid of PMOS pipe and the 2nd PMOS pipe respectively, and the grid of the 3rd PMOS pipe and the 4th PMOS pipe meets control signal ck2 and control signal ck1 respectively, and its drain terminal meets output out1 and output out2 respectively; The source end of the 5th PMOS pipe and the 6th PMOS pipe meets output out1 and output out2 respectively, and its grid meets control signal ck1 and control signal ck2 respectively, and the 5th PMOS pipe is connected with the drain terminal of the 6th PMOS pipe and meets output out
*Output out
*Be connected with an end of zero suppression resistance and the grid of the 7th PMOS pipe respectively; The drain terminal of the 7th PMOS pipe is connected with the source end of the 4th NMOS pipe; The other end of zero suppression resistance is by the building-out capacitor output voltage, and compensating network is also passed through capacity earth.
The invention has the beneficial effects as follows, adopt MOS switch controlled exchange amplifier positive-negative input end signal and output end signal to reduce the imbalance of amplifier, owing to only increased the MOS switching tube in the circuit, they only need very little area, extremely low power consumption, this circuit is when reducing the operational amplifier input offset voltage, do not influence the gain of amplifier, phase margin, supply-voltage rejection ratio (PSRR), performance index such as common-mode input range can be applicable in the main stream of CMOS Circuits System.
Description of drawings
Fig. 1 is the circuit structure diagram of traditional two-stage calculation amplifier;
Fig. 2 is the structured flowchart of two-stage calculation amplifier of the present invention;
Fig. 3 is the circuit diagram of exchange control circuit in the circuit of the present invention;
Fig. 4 is the circuit diagram of two stage amplifer in the circuit of the present invention;
Fig. 5 is the simulation curve comparison diagram (a is the simulation curve figure of the open-loop frequency response of traditional two-stage calculation amplifier circuit, and b is the simulation curve figure that adopts the open-loop frequency response of discharge circuit of the present invention) of the open-loop frequency response of traditional two-stage calculation amplifier circuit and discharge circuit of the present invention;
Fig. 6 is traditional two-stage calculation amplifier circuit and the simulation curve comparison diagram (a is the simulation curve figure of the supply-voltage rejection ratio PSRR frequency response of traditional two-stage calculation amplifier circuit, and b is the simulation curve figure of the supply-voltage rejection ratio PSRR frequency response of discharge circuit of the present invention) that adopts the supply-voltage rejection ratio PSRR frequency response of discharge circuit of the present invention;
Fig. 7 is the simulation curve comparison diagram (a is the simulation curve figure of the common-mode input range ICMR of traditional two-stage calculation amplifier circuit, and b is the simulation curve figure of the common-mode input range ICMR of discharge circuit of the present invention) of the common-mode input range ICMR of traditional two-stage calculation amplifier circuit and discharge circuit of the present invention;
Fig. 8 is the simulation curve comparison diagram of traditional two-stage calculation amplifier circuit and discharge circuit offset voltage of the present invention; (a is the simulation curve figure of the offset voltage of traditional two-stage calculation amplifier circuit, and b is the simulation curve figure of discharge circuit offset voltage of the present invention).
Among the figure, 1. exchange control circuit, 2. first order differential amplifier circuit, 3. second level common source amplifying circuit, 4. compensating network, m1. the one NMOS pipe, m2. the 2nd NMOS manages, m3. a PMOS manages, m4. the 2nd PMOS pipe, m5. the 3rd NMOS pipe, m6. the 7th PMOS manages, m7. the 4th NMOS manages, m8. the 5th NMOS pipe, m9. the 3rd PMOS pipe, m10. the 4th PMOS manages, m11. the 5th PMOS manages, m12. the 6th PMOS pipe, m13. the 7th PMOS pipe, m14. the 8th PMOS manages, m15. the 9th PMOS manages, m16. the tenth PMOS pipe, R
z. zero suppression resistance, C
c. building-out capacitor, C1. electric capacity;
Embodiment
The present invention is described in detail below in conjunction with the drawings and specific embodiments.
As shown in Figure 1, traditional two-stage calculation amplifier circuit comprises the common differential amplifier circuit of the first order, second level common source amplifying circuit and compensating network; The common differential amplifier circuit of the first order is made up of a NMOS pipe m1, the 2nd NMOS pipe m2, the 3rd NMOS pipe m5 and a PMOS pipe m3, the 2nd PMOS pipe m4, second level common source amplifying circuit is made up of the 4th NMOS pipe m7 and the 7th PMOS pipe m6, and compensating network comprises the zero suppression resistance R of series connection
zWith building-out capacitor C
cIn addition, reference current source I
RefProvide image current with the 5th NMOS pipe m8 for the 3rd NMOS pipe m5 and the 4th NMOS pipe m7.Wherein, a PMOS pipe m3, the 2nd PMOS pipe m4 and the 7th PMOS pipe m6 three's source end is connected and meets operating voltage VDD; The one PMOS pipe m3 is connected with the grid of the 2nd PMOS pipe m4; The drain terminal of the one PMOS pipe m3 is connected with its grid, and also the source end with NMOS pipe m1 is connected; The drain terminal of the 2nd PMOS pipe m4 is managed the source end of m2, grid and the zero suppression resistance R of the 7th PMOS pipe m6 with the 2nd NMOS respectively
zAn end connect the zero suppression resistance R
zThe other end by building-out capacitor C
cOutput voltage OUT, compensating network is also by capacitor C 1 ground connection; The drain terminal of the 7th PMOS pipe m6 is connected with the source end of the 4th NMOS pipe m7; The grid of the one NMOS pipe m1 and the 2nd NMOS pipe m2 meets the input signal in1 and the in2 of integrated transporting discharging respectively, and NMOS pipe m1 is connected the source end that also meets the 3rd NMOS pipe m5 simultaneously with the drain terminal of the 2nd NMOS pipe m2; The grid of the 3rd NMOS pipe m5, the 5th NMOS pipe m8 and the 4th NMOS pipe m7 is connected, and the drain terminal of the 3rd NMOS pipe m5, the 5th NMOS pipe m8 and the 4th NMOS pipe m7 is connected and ground connection; The source end of the 5th NMOS pipe m8 is connected with grid, and meets operating voltage VDD.The common differential amplifier circuit of the first order is converted to differential-mode current with differential-mode input voltage, this differential-mode current acts on the single ended voltage output that reverts to amplification on the current mirror load of being made up of PMOS pipe m3 and the 2nd PMOS pipe m4, the 7th PMOS pipe m6 is the common source connection in the common source amplifying circuit of the second level, the 4th NMOS pipe m7 is as the load pipe, constitute output stage amplifier circuit, output voltage OUT, compensating network plays frequency compensated effect.Often have asymmetry owing to reasons such as process deviation cause two difference input pipe characteristics in traditional two-stage calculation amplifying circuit, this can make that at input signal be at 0 o'clock, and still there is output in output, brings the input offset voltage of operational amplifier.
As shown in Figure 2, the invention discloses a kind of circuit structure that reduces the two-stage calculation amplifier input offset voltage, comprise first order differential amplifier circuit 2, second level common source amplifying circuit 3 and the compensating network 4 of exchange control circuit 1, band output function of exchange; The output of exchange control circuit 1 is connected with the input of first order differential amplifier circuit 2, the output of first order differential amplifier circuit 2 is connected with the input of second level common source amplifying circuit 3, also is connected with compensating network 4 between the input of second level common source amplifying circuit 3 and the output.The input signal of exchange control circuit 1 connects the input signal in1 and the in2 of integrated transporting discharging, and the input signal in1 of whole integrated transporting discharging is not the input that directly is connected first order differential amplifier circuit 2 with in2, but the input signal of control circuit 1 in return; The output signal e a1 of exchange control circuit 1 and ea2 are as the input of first order differential amplifier circuit 2, the output signal out of first order differential amplifier circuit 2
*Connect the input of second level common source amplifying circuit 3, the output output voltage OUT of second level common source amplifying circuit 3 inserts compensating network 4 between the input of output OUT and second level common-source amplifier 3.
The offset voltage of integrated transporting discharging is mainly because process deviation makes the differential input stage circuit be difficult to accomplish that complete symmetry causes, the present invention adopts two inputs of control signal exchange differential amplifier to bring in and eliminates the asymmetric imbalance that causes of differential input end, for the output voltage that do not change amplifier and the phase relation of input voltage, the output at differential amplifier also exchanges accordingly by control signal simultaneously.
As shown in Figure 3, the present invention exchanges control circuit 1 and mainly is made up of 4 PMOS pipes, is respectively: the 7th PMOS pipe m13, the 8th PMOS pipe m14, the 9th PMOS pipe m15 and the tenth PMOS pipe m16; The source termination input signal in1 of the 7th PMOS pipe m13 and the 8th PMOS pipe m14, the source termination input signal in2 of the 9th PMOS pipe m15 and the tenth PMOS pipe m16; The grid of the 8th PMOS pipe m14 and the 9th PMOS pipe m15 meets control signal ck1 respectively, and the grid of the 7th PMOS pipe m13 and the tenth PMOS pipe m16 meets control signal ck2 respectively; The 8th PMOS pipe m14 is connected with the drain terminal of the tenth PMOS pipe m16, and its output signal is ea1; The 7th PMOS pipe m13 is connected with the drain terminal of the 9th PMOS pipe m15, and its output signal is ea2.Control signal ck1 and control signal ck2 are that two opposite duty ratios of phase place are the control signal of 50% a certain frequency.When ck1 is a high level, when ck2 was low level, input signal in1 was connected to ea2 by the 7th PMOS pipe m13, and in2 is connected to ea1 by the tenth PMOS pipe m16; When ck1 is a low level, when ck2 was high level, input signal in1 was connected to ea1 by the 8th PMOS pipe m14, and in2 is connected to ea2 by the 9th PMOS pipe m15.As seen, by the control of ck1 and ck2, can realize the exchange of input end signal in1 and in2.
First order differential amplifier circuit 2 among the present invention, second level source electrode amplifying circuit 3 and compensating network 4 are as shown in Figure 4, first order differential amplifier circuit 2 has increased by 4 PMOS pipe m9～m12 by ck1 and ck2 control on the basis of traditional single-ended output differential amplifier, its effect is according to the output out1 of the input different choice differential amplifier of input signal in the exchange control circuit 1 or the input signal out that out2 amplifies as second level common source
*, fix with the output voltage of assurance difference amplifier and the phase relation between the input voltage.
Its concrete structure is: first order differential amplifier circuit 2 comprises a NMOS pipe m1, the 2nd NMOS pipe m2, the 3rd NMOS pipe m5, the 4th NMOS pipe m7, the 5th NMOS pipe m8, PMOS pipe m3, the 2nd PMOS pipe m4, the 3rd PMOS pipe m9, the 4th PMOS pipe m10, the 5th PMOS pipe m11 and the 6th PMOS pipe m12; Second level common source amplifying circuit 3 comprises the 7th PMOS pipe m6; Compensating network 4 comprises the zero suppression resistance R of series connection
zWith building-out capacitor C
cThe one PMOS pipe m3, the 2nd PMOS pipe m4 and the 7th PMOS pipe m6 three's source end is connected and meets operating voltage VDD; The one PMOS pipe m3 is connected with the grid of the 2nd PMOS pipe m4; The drain terminal of the one PMOS pipe m3 is connected with the source end of NMOS pipe m1 through output out1, and the drain terminal of the 2nd PMOS pipe m4 is connected with the source end of the 2nd NMOS pipe m2 through output out2; The grid of the one NMOS pipe m1 and the 2nd NMOS pipe m2 meets signal ea1 and signal ea2 respectively, and NMOS pipe m1 is connected the source end that also meets the 3rd NMOS pipe m5 simultaneously with the drain terminal of the 2nd NMOS pipe m2; The grid of the 3rd NMOS pipe m5, the 5th NMOS pipe m8 and the 4th NMOS pipe m7 is connected, and the drain terminal of the 3rd NMOS pipe m5, the 5th NMOS pipe m8 and the 4th NMOS pipe m7 is connected and ground connection; The source end of the 5th NMOS pipe m8 is connected with grid, and meets operating voltage VDD; The source end of the 3rd PMOS pipe m9 and the 4th PMOS pipe m10 connects the grid of PMOS pipe m3 and the 2nd PMOS pipe m4 respectively, the grid of the 3rd PMOS pipe m9 and the 4th PMOS pipe m10 meets control signal ck2 and control signal ck1 respectively, and its drain terminal meets output out1 and output out2 respectively; The source end of the 5th PMOS pipe m11 and the 6th PMOS pipe m12 meets output out1 and output out2 respectively, and its grid meets control signal ck1 and control signal ck2 respectively, and the drain terminal of the 5th PMOS pipe m11 and the 6th PMOS pipe m12 is connected and meets output out
*Output out
*Respectively with the zero suppression resistance R
zAn end and the grid of the 7th PMOS pipe m6 be connected; The drain terminal of the 7th PMOS pipe m6 is connected with the source end of the 4th NMOS pipe m7; The zero suppression resistance R
zThe other end by building-out capacitor C
cOutput voltage OUT, compensating network 4 is also by capacitor C 1 ground connection.
When ck1 is a high level, when ck2 is low level, the 3rd PMOS pipe m9 and the 6th PMOS pipe m12 conducting, the 4th PMOS pipe m10 and the 5th PMOS pipe m11 end, the conducting of the 3rd PMOS pipe m9 makes the 2nd PMOS pipe m4 and PMOS pipe m3 constitute the load of mirror current source as differential amplifier, the 2nd PMOS pipe m4 duplicates the electric current of PMOS pipe m3, and the conducting of the 6th PMOS pipe m12 makes the out2 termination lead to output out
*When ck1 is a low level, when ck2 is high level, the 4th PMOS pipe m10 and the 5th PMOS pipe m11 conducting, the 3rd PMOS pipe m9 and the 6th PMOS pipe m12 end, the conducting of the 4th PMOS pipe m10 makes the PMOS that wins manage m3 and the 2nd PMOS pipe m4 constitutes the load of mirror current source as differential amplifier, the one PMOS pipe m3 duplicates the electric current of the 2nd PMOS pipe m4, and the conducting of the 5th PMOS pipe m11 makes the out1 termination lead to output out
*Out
*What end connected later is second level common source amplifying circuit 3 (the 7th PMOS manages m6) and compensating network 4.
The whole operation principle that reduces two-stage calculation amplifier input offset voltage circuit structure is: when ck1 is a high level, when ck2 is low level, the 3rd PMOS pipe m9, the 6th PMOS pipe m12, the 7th PMOS pipe m13 and the tenth PMOS pipe m16 conducting, the 4th PMOS pipe m10, the 5th PMOS manage m11, the 8th PMOS pipe m14 and the 9th PMOS pipe m15 end, the value of the anode ea2 of difference input is input signal in1, and the value of ea1 is in2, and the output node of difference is out2.Otherwise, when ck1 is a low level, when ck2 is high level, the 3rd PMOS pipe m9, the 6th PMOS pipe m12, the 7th PMOS pipe m13 and the tenth PMOS pipe m16 end, the 4th PMOS pipe m10, the 5th PMOS manage m11, the 8th PMOS pipe m14 and the 9th PMOS pipe m15 conducting, and the value of the anode ea2 of difference input is input signal in2, the value of ea1 is in1, and the output node of difference is out1.
Adopt HSPICE circuit to be carried out emulation based on 0.5um mixed signal model, as shown in Figure 5, be the open-loop frequency response of traditional two stage amplifer circuit and two stage amplifer circuit of the present invention, as can be seen by a figure, the gain of tradition two stage amplifer circuit is 84dB, and phase margin is 76 °; By b figure as can be seen, the gain of discharge circuit of the present invention is 84dB, and phase margin is 60 °; The stability that discharge circuit of the present invention is described is better.
As shown in Figure 6, it is the simulation curve of the supply-voltage rejection ratio of traditional two stage amplifer circuit and two stage amplifer circuit of the present invention, by a figure as can be seen, the PSRR of tradition two stage amplifer circuit is 89.2dB, by b figure as can be seen, the PSRR of discharge circuit of the present invention is 90.88dB, illustrates that the Power Supply Rejection Ratio of discharge circuit of the present invention slightly improves, and is very little to output voltage influence during mains fluctuations.
As shown in Figure 7, be the simulation curve of the common-mode input range (ICMR) of traditional two stage amplifer circuit and two stage amplifer circuit of the present invention, by a figure as can be seen, the ICMR of traditional two stage amplifer circuit is 1.3～2.9V; By b figure as can be seen, the ICMR of discharge circuit of the present invention is 1.2～2.9V.Explanation is compared with traditional two stage amplifer circuit, and the minimum input common mode voltage of discharge circuit of the present invention has reduced, and has promptly increased common-mode input range.
Fig. 8 is the input offset voltage V of traditional two stage amplifer circuit and two stage amplifer circuit of the present invention
OsSimulation curve, its value differentially is input as zero and measures by being provided with.By a figure as can be seen, the V of traditional two stage amplifer circuit
OsBe 621.11mV; By b figure as can be seen, the V of discharge circuit of the present invention
OsBe about 417mV, the spike among the figure is because the switching of switch produces.Illustrate and adopt the input offset voltage of amplifier of the present invention to reduce 204mV.
Claims (3)
1. a circuit structure that reduces the two-stage calculation amplifier input offset voltage is characterized in that, comprises exchange control circuit (1), first order differential amplifier circuit (2), second level common source amplifying circuit (3) and compensating network (4); The output of exchange control circuit (1) is connected with the input of first order differential amplifier circuit (2), the output of first order differential amplifier circuit (2) is connected with the input of second level common source amplifying circuit (3), also is connected with compensating network (4) between the input of second level common source amplifying circuit (3) and the output.
2. the circuit that reduces the two-stage calculation amplifier input offset voltage according to claim 1, it is characterized in that: described exchange control circuit (1) is made of 4 PMOS pipes, is respectively: the 7th PMOS pipe (m13), the 8th PMOS pipe (m14), the 9th PMOS pipe (m15) and the tenth PMOS pipe (m16); The source termination input signal in1 of the 7th PMOS pipe (m13) and the 8th PMOS pipe (m14), the source termination input signal in2 of the 9th PMOS pipe (m15) and the tenth PMOS pipe (m16); The grid of the 8th PMOS pipe (m14) and the 9th PMOS pipe (m15) meets control signal ck1 respectively, and the grid of the 7th PMOS pipe (m13) and the tenth PMOS pipe (m16) meets control signal ck2 respectively; The 8th PMOS pipe (m14) is connected with the drain terminal of the tenth PMOS pipe (m16), and its output signal is ea1; The 7th PMOS pipe (m13) is connected with the drain terminal of the 9th PMOS pipe (m15), and its output signal is ea2.
3. the circuit that reduces the two-stage calculation amplifier input offset voltage according to claim 1 is characterized in that:
Described first order differential amplifier circuit (2) comprises NMOS pipe (m1), the 2nd NMOS pipe (m2), the 3rd NMOS pipe (m5), the 4th NMOS pipe (m7), the 5th NMOS pipe (m8), PMOS pipe (m3), the 2nd PMOS pipe (m4), the 3rd PMOS pipe (m9), the 4th PMOS pipe (m10), the 5th PMOS pipe (m11) and the 6th PMOS pipe (m12);
Described second level common source amplifying circuit (3) comprises the 7th PMOS pipe (m6);
Described compensating network (4) comprises the zero suppression resistance (R of series connection
z) and building-out capacitor (C
c);
The one PMOS pipe (m3), the 2nd PMOS pipe (m4) and the 7th PMOS pipe (m6) three's source end is connected and connects operating voltage; The one PMOS pipe (m3) is connected with the grid of the 2nd PMOS pipe (m4); The drain terminal of the one PMOS pipe (m3) is connected with the source end that a NMOS manages (m1) through output out1, and the drain terminal of the 2nd PMOS pipe (m4) is connected with the source end that the 2nd NMOS manages (m2) through output out2; The grid of the one NMOS pipe (m1) and the 2nd NMOS pipe (m2) meets the output signal e a1 of exchange control circuit (1) and the output signal e a2 of exchange control circuit (1) respectively, and the drain terminal of NMOS pipe (m1) and the 2nd NMOS pipe (m2) is connected and is connected with the source end of the 3rd NMOS pipe (m5) simultaneously; The 3rd NMOS pipe (m5), the 5th NMOS pipe (m8) and the grid of the 4th NMOS pipe (m7) are connected, and the drain terminal of the 3rd NMOS pipe (m5), the 5th NMOS pipe (m8) and the 4th NMOS pipe (m7) is connected and ground connection; The source end of the 5th NMOS pipe (m8) is connected with grid, and connects operating voltage simultaneously;
The source end of the 3rd PMOS pipe (m9) and the 4th PMOS pipe (m10) connects the grid of PMOS pipe (m3) and the 2nd PMOS pipe (m4) respectively, the grid of the 3rd PMOS pipe (m9) and the 4th PMOS pipe (m10) meets control signal ck2 and control signal ck1 respectively, and its drain terminal meets output out1 and output out2 respectively; The source end of the 5th PMOS pipe (m11) and the 6th PMOS pipe (m12) meets output out1 and output out2 respectively, its grid meets control signal ck1 and control signal ck2 respectively, and the drain terminal of the 5th PMOS pipe (m11) and the 6th PMOS pipe (m12) is connected and meets output out
*Output out
*Respectively with zero suppression resistance (R
z) an end be connected with the grid that the 7th PMOS manages (m6); The drain terminal of the 7th PMOS pipe (m6) is connected with the source end that the 4th NMOS manages (m7); Zero suppression resistance (R
z) the other end by building-out capacitor (C
c) output voltage, compensating network (4) is also by electric capacity (C1) ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110009728 CN102130659B (en) | 2011-01-20 | 2011-01-20 | Circuit structure for reducing input offset voltage of two-stage operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110009728 CN102130659B (en) | 2011-01-20 | 2011-01-20 | Circuit structure for reducing input offset voltage of two-stage operational amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102130659A true CN102130659A (en) | 2011-07-20 |
| CN102130659B CN102130659B (en) | 2013-03-13 |
Family
ID=44268570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110009728 Active CN102130659B (en) | 2011-01-20 | 2011-01-20 | Circuit structure for reducing input offset voltage of two-stage operational amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102130659B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178813A (en) * | 2013-02-26 | 2013-06-26 | 东南大学 | Low-offset full-motion comparator |
| CN103199807A (en) * | 2013-03-26 | 2013-07-10 | 电子科技大学 | Split compensation two-stage operational amplifier based on inverter input structure |
| CN104579208A (en) * | 2015-01-09 | 2015-04-29 | 湘潭大学 | Differential amplification circuit based on ferro-electric field effect transistors |
| CN104852608A (en) * | 2015-06-01 | 2015-08-19 | 株洲南车时代电气股份有限公司 | Apparatus and method for converting low-voltage frequency signal into high-voltage direct current signal |
| CN106466177A (en) * | 2015-08-17 | 2017-03-01 | 浙江诺尔康神经电子科技股份有限公司 | A kind of artificial cochlea's nerve telemetry system comprising pulse-width adjustment |
| CN107623498A (en) * | 2017-10-18 | 2018-01-23 | 上海芯北电子科技有限公司 | A kind of operational amplifier calibration method and circuit |
| CN109743031A (en) * | 2018-12-29 | 2019-05-10 | 长江存储科技有限责任公司 | A kind of power amplification circuit |
| CN110417358A (en) * | 2019-07-30 | 2019-11-05 | 上海艾为电子技术股份有限公司 | A kind of front stage circuits and operational amplifier |
| CN110690860A (en) * | 2019-11-26 | 2020-01-14 | 湖南中部芯谷科技有限公司 | Zero-temperature-drift operational amplifier suitable for small signal and high noise |
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| CN113674681A (en) * | 2021-08-20 | 2021-11-19 | 南京大学 | NMOS transistor-based PWM pixel circuit, driving method and display device |
| CN113674680A (en) * | 2021-08-20 | 2021-11-19 | 南京大学 | PWM (pulse-Width modulation) driving circuit and driving method based on pixel sharing |
| CN113741608A (en) * | 2021-08-30 | 2021-12-03 | 普冉半导体(上海)股份有限公司 | Linear voltage regulator circuit |
| WO2022252025A1 (en) * | 2021-05-31 | 2022-12-08 | 深圳技术大学 | Configurable active electrode having offset voltage suppression |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057734A (en) * | 1999-01-14 | 2000-05-02 | Seiko Epson Corporation | Symmetrical analog power amplifier |
| US6300834B1 (en) * | 2000-12-12 | 2001-10-09 | Elantec Semiconductor, Inc. | High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier |
| CN101587699A (en) * | 2008-05-21 | 2009-11-25 | 松下电器产业株式会社 | Offset cancellation circuit and display device |
| CN101841308A (en) * | 2010-05-24 | 2010-09-22 | 无锡汉咏微电子有限公司 | Structure of high performance operational amplifier |
-
2011
- 2011-01-20 CN CN 201110009728 patent/CN102130659B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057734A (en) * | 1999-01-14 | 2000-05-02 | Seiko Epson Corporation | Symmetrical analog power amplifier |
| US6300834B1 (en) * | 2000-12-12 | 2001-10-09 | Elantec Semiconductor, Inc. | High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier |
| CN101587699A (en) * | 2008-05-21 | 2009-11-25 | 松下电器产业株式会社 | Offset cancellation circuit and display device |
| CN101841308A (en) * | 2010-05-24 | 2010-09-22 | 无锡汉咏微电子有限公司 | Structure of high performance operational amplifier |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178813A (en) * | 2013-02-26 | 2013-06-26 | 东南大学 | Low-offset full-motion comparator |
| CN103178813B (en) * | 2013-02-26 | 2015-07-15 | 东南大学 | Low-offset full-motion comparator |
| CN103199807A (en) * | 2013-03-26 | 2013-07-10 | 电子科技大学 | Split compensation two-stage operational amplifier based on inverter input structure |
| CN103199807B (en) * | 2013-03-26 | 2015-09-09 | 电子科技大学 | Division based on inverter input structure compensates two-stage calculation amplifier |
| CN104579208A (en) * | 2015-01-09 | 2015-04-29 | 湘潭大学 | Differential amplification circuit based on ferro-electric field effect transistors |
| CN104852608A (en) * | 2015-06-01 | 2015-08-19 | 株洲南车时代电气股份有限公司 | Apparatus and method for converting low-voltage frequency signal into high-voltage direct current signal |
| CN106466177A (en) * | 2015-08-17 | 2017-03-01 | 浙江诺尔康神经电子科技股份有限公司 | A kind of artificial cochlea's nerve telemetry system comprising pulse-width adjustment |
| CN106466177B (en) * | 2015-08-17 | 2023-11-17 | 浙江诺尔康神经电子科技股份有限公司 | Artificial cochlea nerve telemetry system comprising pulse width adjustment |
| CN107623498A (en) * | 2017-10-18 | 2018-01-23 | 上海芯北电子科技有限公司 | A kind of operational amplifier calibration method and circuit |
| CN107623498B (en) * | 2017-10-18 | 2020-10-09 | 上海芯北电子科技有限公司 | Operational amplifier calibration method and circuit |
| CN109743031A (en) * | 2018-12-29 | 2019-05-10 | 长江存储科技有限责任公司 | A kind of power amplification circuit |
| CN110417358A (en) * | 2019-07-30 | 2019-11-05 | 上海艾为电子技术股份有限公司 | A kind of front stage circuits and operational amplifier |
| CN110417358B (en) * | 2019-07-30 | 2023-05-16 | 上海艾为电子技术股份有限公司 | Front-end circuit and operational amplifier |
| CN110690860A (en) * | 2019-11-26 | 2020-01-14 | 湖南中部芯谷科技有限公司 | Zero-temperature-drift operational amplifier suitable for small signal and high noise |
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| WO2022252025A1 (en) * | 2021-05-31 | 2022-12-08 | 深圳技术大学 | Configurable active electrode having offset voltage suppression |
| CN113674680A (en) * | 2021-08-20 | 2021-11-19 | 南京大学 | PWM (pulse-Width modulation) driving circuit and driving method based on pixel sharing |
| CN113674680B (en) * | 2021-08-20 | 2023-03-14 | 南京大学 | PWM (pulse-Width modulation) driving circuit and driving method based on pixel sharing |
| CN113674681A (en) * | 2021-08-20 | 2021-11-19 | 南京大学 | NMOS transistor-based PWM pixel circuit, driving method and display device |
| CN113741608A (en) * | 2021-08-30 | 2021-12-03 | 普冉半导体(上海)股份有限公司 | Linear voltage regulator circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102130659B (en) | 2013-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102130659B (en) | Circuit structure for reducing input offset voltage of two-stage operational amplifier | |
| US9634685B2 (en) | Telescopic amplifier with improved common mode settling | |
| CN103219961B (en) | The operation amplifier circuit that a kind of bandwidth is adjustable | |
| CN103973274B (en) | Latched comparator | |
| CN100549898C (en) | Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance | |
| TW200832896A (en) | Dynamic bandwidth compensating method and associated apparatus | |
| CN102394583B (en) | Broadband high-gain transconductance amplifier | |
| CN101471632A (en) | Self-bias low-voltage operation transconductance amplifier circuit with controllable loop gain | |
| CN108336978B (en) | Cascaded distributed low-noise amplifier | |
| CN109921756B (en) | Fully-differential transconductance operational amplifier | |
| CN116232331A (en) | Dynamic error elimination integrator applied to high-precision Sigma-Delta ADC | |
| CN102723918B (en) | A kind of trsanscondutance amplifier, resistance, inductance and filter | |
| CN104124932A (en) | Radio-frequency power amplification module | |
| WO2022027750A1 (en) | Comparator and analog-to-digital converter | |
| TW201431280A (en) | Triple cascode power amplifier | |
| CN103107791B (en) | Gain linear variable gain amplifier with constant bandwidth | |
| CN110649900A (en) | High signal-to-noise ratio two-stage operational amplifier | |
| CN101098123B (en) | Low-voltage and low-power dissipation pseudo-two stage Class-AB OTA structure | |
| CN108092628A (en) | A kind of operational amplifier and amplifier circuit that there is imbalance to eliminate structure | |
| US7986185B2 (en) | Rail-to-rail Miller compensation method without feed forward path | |
| CN204794913U (en) | Operational amplifier | |
| CN106712731B (en) | Operational amplifier | |
| CN109120234B (en) | Novel power amplification circuit | |
| CN203289404U (en) | CMOS buffer circuit capable of driving high capacitive load | |
| CN108199700A (en) | A kind of high-precision comparator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: XI AN JIEHANG ELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: XI AN UNIV. OF SCIENCE AND ENGINEERING Effective date: 20150721 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150721 Address after: 710065 Shaanxi city of Xi'an province high tech Zone gazelle Road No. 26 Xi'an Polytechnic University Science and Technology Park D block Patentee after: Xi'an Jie Hang Electronic Science and Technology Co., Ltd. Address before: 710048 Shaanxi city of Xi'an Province Jinhua Road No. 5 Patentee before: Xi'an University of Technology |