CN116232331A - Dynamic error elimination integrator applied to high-precision Sigma-Delta ADC - Google Patents
Dynamic error elimination integrator applied to high-precision Sigma-Delta ADC Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention provides a dynamic error elimination integrator applied to a high-precision Sigma-Delta ADC (analog to digital converter), which relates to the technical field of integrated circuits and comprises a non-overlapping clock generation module, a sampling integration control circuit, a first chopper modulation circuit, a second chopper modulation circuit, an integration capacitor and a fully differential operational amplifier; the input end of the sampling integral control circuit is connected with the signal input end, the two output ends of the sampling integral control circuit are respectively connected with the input end of the first chopper modulation circuit and one end of the integral capacitor, and the other end of the integral capacitor is respectively connected with the output end of the second chopper modulation circuit and the signal output end; and two ends of the fully differential operational amplifier are respectively connected with the output end of the first chopper modulation circuit and the input end of the second chopper modulation circuit. The invention can dynamically eliminate errors caused by non-ideal factors such as channel charge injection effect, clock feed-through effect, operational amplifier direct loss, operational amplifier low-frequency noise and the like, thereby effectively improving the precision of the whole Sigma-Delta ADC.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a dynamic error elimination integrator applied to a high-precision Sigma-Delta ADC.
Background
Analog-to-digital converters (Analog to Digital Converter, ADC) are devices that convert continuously varying analog signals to discrete digital signals and have wide application in the field of integrated circuits. Such as analog signals of temperature, pressure, sound, fingerprints or images, need to be converted into digital signals in a digital form that are easier to store, process and transmit. The Sigma-Delta ADC is the most commonly used high-precision ADC structure at present, and obtains higher conversion precision by utilizing the oversampling and noise shaping technology, and is widely applied to the fields of wearable equipment, industrial measurement, implantable medical electronics and the like.
The integrator is an important module of the Sigma-Delta ADC, and the main function is to sample the signal and shape the noise out of band, which has an important influence on the whole ADC performance. However, the channel charge injection effect and clock feed-through effect of the sampling switch in the current integrator can affect the sampling precision of the input signal, and the operational amplifier low-frequency noise can affect the noise of the whole circuit, the operational amplifier direct current offset can also affect the non-ideal factors such as the whole circuit offset and the nonlinearity of the on-resistance of the switch, which can bring errors to the circuit, thereby affecting the conversion precision of the whole ADC. It is therefore important to design an integrator that eliminates the above error factors in order for the Sigma-Delta ADC overall circuit to operate stably and achieve high accuracy.
Disclosure of Invention
The invention aims to solve the technical problem of providing a dynamic error elimination integrator applied to a high-precision Sigma-Delta ADC, which can dynamically eliminate channel charge injection effect and clock feed-through effect to avoid influencing the sampling precision of signals, and can dynamically eliminate errors caused by non-ideal factors such as operational amplifier straight loss and operational amplifier low-frequency noise, so that the precision of the whole Sigma-Delta ADC is effectively improved.
In order to solve the technical problems, the invention provides a dynamic error elimination integrator applied to a high-precision Sigma-Delta ADC, which comprises a non-overlapping clock generation module, a sampling integration control circuit, a first chopper modulation circuit, a second chopper modulation circuit, an integration capacitor and a fully differential operational amplifier; the input end of the sampling integral control circuit is connected with the signal input end, the two output ends of the sampling integral control circuit are respectively connected with the input end of the first chopper modulation circuit and one end of the integral capacitor, and the other end of the integral capacitor is respectively connected with the output end of the second chopper modulation circuit and the signal output end; the input end of the full-differential operational amplifier is connected with the output end of the first chopper modulation circuit, and the output end of the full-differential operational amplifier is connected with the input end of the second chopper modulation circuit; the non-overlapping clock generation module is connected with the sampling integration control circuit and is used for outputting two-phase non-overlapping clock control signals to control the sampling integration control circuit to sample the input differential voltage signals and outputting the sampled differential voltage signals to the integration capacitor and the first chopper modulation circuit.
The chopper control circuit is characterized by further comprising a chopper clock generation module, wherein the chopper clock generation module is respectively connected with the first chopper modulation circuit and the second chopper modulation circuit and is used for outputting chopper control signals to respectively control signal modulation work of the first chopper modulation circuit and the second chopper modulation circuit.
As an improvement of the above-described scheme, the first chopper modulation circuit includes a first chopper switch, a second chopper switch, a third chopper switch, and a fourth chopper switch; the input ends of the first chopping switch and the second chopping switch are respectively connected with the first output end of the sampling integration control circuit and one end of the first integration capacitor, and the input ends of the third chopping switch and the fourth chopping switch are respectively connected with the second output end of the sampling integration control circuit and one end of the second integration capacitor; the output ends of the first chopping switch and the third chopping switch are respectively connected with the positive input end of the fully differential operational amplifier, and the output ends of the second chopping switch and the fourth chopping switch are connected with the negative input end of the fully differential operational amplifier; the chopping clock generation module is respectively connected with the first chopping switch, the second chopping switch, the third chopping switch and the fourth chopping switch and is used for outputting a first chopping control signal to respectively control the on-off states of the first chopping switch and the fourth chopping switch and outputting a second chopping control signal to respectively control the on-off states of the second chopping switch and the third chopping switch.
As an improvement of the above-described aspect, the second chopper modulation circuit includes a fifth chopper switch, a sixth chopper switch, a seventh chopper switch, and an eighth chopper switch; the input ends of the fifth chopper switch and the sixth chopper switch are connected with the negative output end of the fully differential operational amplifier, and the input ends of the seventh chopper switch and the eighth chopper switch are connected with the positive output end of the fully differential operational amplifier; the output ends of the fifth chopper switch and the seventh chopper switch are respectively connected with the first signal output end and the other end of the first integrating capacitor, and the output ends of the sixth chopper switch and the eighth chopper switch are respectively connected with the second signal output end and the other end of the second integrating capacitor; the chopping clock generation module is respectively connected with the fifth chopping switch, the sixth chopping switch, the seventh chopping switch and the eighth chopping switch and is used for outputting a first chopping control signal to respectively control the on-off states of the fifth chopping switch and the eighth chopping switch and outputting a second chopping control signal to respectively control the on-off states of the sixth chopping switch and the seventh chopping switch.
As an improvement of the above scheme, the first chopping control signal and the second chopping control signal are opposite in phase.
As an improvement of the above scheme, the non-overlapping clock generation module includes a sampling phase clock generation module and an integration phase clock generation module; the sampling integral control circuit comprises a sampling switch control circuit, an integral switch control circuit and a sampling capacitor; the sampling phase clock generation module is connected with the sampling switch control circuit and is used for outputting a sampling clock control signal to control the sampling switch control circuit to conduct a sampling loop of the sampling capacitor so as to sample an input differential voltage signal; the integral phase clock generation module is connected with the integral switch control circuit and is used for outputting an integral clock control signal to control the integral switch control circuit to conduct a loop among the sampling capacitor, the first chopper modulation circuit and the integral capacitor so as to output a differential voltage signal sampled by the sampling capacitor to the integral capacitor and the first chopper modulation circuit; the sampling clock control signal and the integrating clock control signal are two-phase non-overlapping clocks and are opposite in phase.
As an improvement of the above scheme, the sampling switch control circuit comprises a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch, the integrating switch control circuit comprises a first integrating switch, a second integrating switch, a third integrating switch and a fourth integrating switch, and the sampling capacitor comprises a first sampling capacitor and a second sampling capacitor; the input ends of the first sampling switch and the second sampling switch are respectively connected with the corresponding differential voltage signal input ends, the output end of the first sampling switch is connected with the output end of the second sampling switch through the first sampling capacitor, the third sampling switch, the fourth sampling switch and the second sampling capacitor in sequence, and the output end of the first sampling switch is also connected with the output end of the second sampling switch through the first integrating switch and the second integrating switch in sequence; the connection end between the first integrating switch and the second integrating switch and the connection end between the third sampling switch and the fourth sampling switch are connected with the common-mode voltage signal input end, the connection end between the top pole plate of the first sampling capacitor and the third sampling switch is respectively connected with one end of the first integrating capacitor and the first input end of the first chopper modulation circuit through the third integrating switch, and the connection end between the top pole plate of the second sampling capacitor and the fourth sampling switch is respectively connected with one end of the second integrating capacitor and the second input end of the first chopper modulation circuit through the fourth integrating switch.
As an improvement of the above scheme, the sampling phase clock generation module includes a first sampling signal output end and a second sampling signal output end; the first sampling signal output end is respectively connected with the first sampling switch and the second sampling switch and is used for outputting a first sampling clock control signal to control the on-off states of the first sampling switch and the second sampling switch; the second sampling signal output end is respectively connected with the third sampling switch and the fourth sampling switch and is used for outputting a second sampling clock control signal to control the on-off states of the third sampling switch and the fourth sampling switch; the first sampling clock control signal is a delay signal of the second sampling clock control signal, and enters the falling edge after being delayed for a preset time so as to delay the on state of the first sampling switch and the second sampling switch to be disconnected.
As an improvement of the above scheme, the integral phase clock generation module includes a first integral signal output end and a second integral signal output end; the first integration signal output end is respectively connected with the first integration switch and the second integration switch and is used for outputting a first integration clock control signal to control the on-off states of the first integration switch and the second integration switch; the second integral signal output end is respectively connected with the third integral switch and the fourth integral switch and is used for outputting a second integral clock control signal to control the on-off states of the third integral switch and the fourth integral switch; the first integral clock control signal is a delay signal of the second integral clock control signal, and enters the falling edge after being delayed for a preset time so as to delay the on state of the first integral switch and the second integral switch to be disconnected.
As an improvement of the scheme, the first sampling switch and the second sampling switch are both grid voltage bootstrap switches; the third sampling switch, the fourth sampling switch, the first integrating switch, the second integrating switch, the third integrating switch and the fourth integrating switch are all CMOS switches.
The implementation of the invention has the following beneficial effects:
the invention is applied to a dynamic error elimination integrator of a high-precision Sigma-Delta ADC, can dynamically eliminate channel charge injection effect and clock feed-through effect to avoid influencing the sampling precision of signals, can dynamically eliminate errors caused by non-ideal factors such as nonlinear on-resistance of a switch, run-off and run-on low frequency noise and the like, and can effectively improve the precision of the whole Sigma-Delta ADC.
Specifically, the clock feedthrough effect is eliminated by adopting a fully differential symmetrical circuit structure; the channel charge injection effect is eliminated by adopting a two-phase non-overlapping clock and combining a bottom plate sampling mode of a sampling capacitor; the CMOS switch with small area, power supply to ground output range and high on-resistance linearity is adopted by part of the switches, and the grid voltage bootstrap switch is adopted on a key signal input path so as to obtain constant on-resistance, thereby reducing and eliminating errors caused by non-linearity of the on-resistance; the full differential operational amplifier of the two-stage operational amplifier with lower noise and larger output swing is adopted to prevent the overload of the integrator and reduce the overall noise of the circuit; the low-frequency noise of the operational amplifier and the DC offset of the operational amplifier are restrained by adopting a chopping technology. Therefore, the dynamic error elimination is realized by the mode, so that the precision of the whole circuit and the ADC is improved.
Drawings
FIG. 1 is a schematic diagram of a dynamic error cancellation integrator applied to a high-precision Sigma-Delta ADC;
FIG. 2 is a schematic diagram of a configuration of the dynamic error cancellation integrator of the present invention further including a chopper clock generation module;
FIG. 3 is a specific circuit diagram of a dynamic error cancellation integrator according to the present invention;
FIG. 4 is a clock structure diagram of a dynamic error cancellation integrator of the present invention;
FIG. 5 is a circuit timing diagram of a dynamic error cancellation integrator according to the present invention;
FIG. 6 is a specific circuit diagram of a fully differential operational amplifier of the present invention;
FIG. 7 is a specific circuit diagram of the gate voltage bootstrapped switch of the present invention;
fig. 8 is a specific circuit diagram of the CMOS switch of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
As shown in fig. 1, a specific embodiment of the present invention provides a dynamic error elimination integrator applied to a high-precision Sigma-Delta ADC, which includes a non-overlapping clock generation module 1, a sampling integration control circuit 2, a first chopper modulation circuit 3, a second chopper modulation circuit 4, an integration capacitor 5 and a fully differential operational amplifier 6.
The three-way input end of the sampling integration control circuit 2 is respectively connected with two corresponding differential voltage signal input ends and common-mode voltage signal input ends, the two output ends of the sampling integration control circuit 2 are respectively connected with the input end of the first chopper modulation circuit 3 and one end of the integration capacitor 5, and the other end of the integration capacitor 5 is respectively connected with the output end and the signal output end of the second chopper modulation circuit 4; the input end of the fully differential operational amplifier 6 is connected with the output end of the first chopper modulation circuit 3, and the output end of the fully differential operational amplifier 6 is connected with the input end of the second chopper modulation circuit 4 to construct a fully differential symmetrical circuit structure. The non-overlapping clock generation module 1 is connected with the sampling integration control circuit 2 and is used for outputting a two-phase non-overlapping clock control signal to control the sampling integration control circuit 2 to sample an input differential voltage signal and outputting the sampled differential voltage signal to the integration capacitor 5 and the first chopper modulation circuit 3 so as to realize the work of a sampling stage and an integration stage.
The channel charge injection effect is eliminated by adopting a two-phase non-overlapping clock and combining a bottom plate sampling mode of a sampling capacitor in the sampling integral control circuit 2; the clock feed-through effect is eliminated through the fully-differential symmetrical circuit structure, so that the influence on the sampling precision of signals is avoided. The input end of the fully differential operational amplifier 6 modulates the input signal to the odd frequency of the chopping frequency through the first chopping modulation circuit 3, then the operational amplification direct loss and the operational amplification low-frequency noise of the fully differential operational amplifier 6 are overlapped, the input end of the fully differential operational amplifier 6 modulates the input signal back to the baseband frequency through the second chopping modulation circuit 4, and the operational amplification direct loss and the operational amplification low-frequency noise are modulated to the odd frequency of the chopping frequency, so that the operational amplification direct loss and the operational amplification low-frequency noise are restrained, and the overall circuit and ADC precision are improved. Wherein these odd components will be filtered out by the low pass filter circuit of the external subsequent circuit.
As shown in fig. 2, the invention further comprises a chopper clock generating module 7, wherein the chopper clock generating module 7 is respectively connected with the first chopper modulation circuit 3 and the second chopper modulation circuit 4 and is used for outputting chopper control signals to respectively control the signal modulation operation of the first chopper modulation circuit 3 and the second chopper modulation circuit 4, and the chopper technology is controlled to inhibit the low-frequency noise of the operational amplifier and the offset of the operational amplifier and the direct current, so that the precision of the whole circuit and the ADC is improved.
The following specific circuit diagrams, clock structure diagrams and timing diagrams according to the present invention are further set forth:
as shown in fig. 3 to 4, the first chopper modulation circuit 3 includes a first chopper switch K1, a second chopper switch K2, a third chopper switch K3, and a fourth chopper switch K4; the input ends of the first chopping switch K1 and the second chopping switch K2 are respectively connected with the first output end of the sampling integration control circuit 2 and one end of the first integration capacitor 51, and the input ends of the third chopping switch K3 and the fourth chopping switch K4 are respectively connected with the second output end of the sampling integration control circuit 2 and one end of the second integration capacitor 52; the output ends of the first chopping switch K1 and the third chopping switch K3 are respectively connected with the positive input end of the fully differential operational amplifier 6, and the output ends of the second chopping switch K2 and the fourth chopping switch K4 are connected with the negative input end of the fully differential operational amplifier 6; the chopping clock generation module 7 is respectively connected with the first chopping switch K1, the second chopping switch K2, the third chopping switch K3 and the fourth chopping switch K4, and is used for outputting a first chopping control signal chop_clk to respectively control the on-off states of the first chopping switch K1 and the fourth chopping switch K4, and outputting a second chopping control signal chop_clkn to respectively control the on-off states of the second chopping switch K2 and the third chopping switch K3.
The second chopper modulation circuit 4 includes a fifth chopper switch K5, a sixth chopper switch K6, a seventh chopper switch K7, and an eighth chopper switch K8; the input ends of the fifth chopper switch K5 and the sixth chopper switch K6 are connected with the negative output end of the fully differential operational amplifier 6, and the input ends of the seventh chopper switch K7 and the eighth chopper switch K8 are connected with the positive output end of the fully differential operational amplifier 6; the output ends of the fifth chopper switch K5 and the seventh chopper switch K7 are respectively connected with the first signal output end V op The output ends of the sixth chopper switch K6 and the eighth chopper switch K8 are respectively connected with the second signal output end V on The other end of the second integrating capacitor 52 is connected; chopper clock generation modules 7 respectivelyThe fifth chopping switch K5, the sixth chopping switch K6, the seventh chopping switch K7 and the eighth chopping switch K8 are connected and are used for outputting a first chopping control signal chop_clk to respectively control the on-off states of the fifth chopping switch K5 and the eighth chopping switch K8 and outputting a second chopping control signal chop_clkn to respectively control the on-off states of the sixth chopping switch K6 and the seventh chopping switch K7.
It should be noted that the first chopping control signal chop_clk and the second chopping control signal chop_clkn are opposite to each other. Outputting a first chopping control signal chop_clk through a chopping clock generation module 7 to control the first chopping switch K1, the fourth chopping switch K4, the fifth chopping switch K5 and the eighth chopping switch K8 to be conducted; or outputting a second chopping control signal chop_clkn through the chopping clock generation module 7 to control the second chopping switch K2, the third chopping switch K3, the sixth chopping switch K6 and the seventh chopping switch K7 to be conducted; the two chopping control modes are used for realizing secondary modulation of an input signal and primary modulation of the operational amplifier low-frequency noise and the operational amplifier direct loss modulation, so that the input signal is modulated back to a baseband frequency and output, and the operational amplifier direct loss modulation and the operational amplifier low-frequency noise are modulated to the odd frequency of the chopping frequency, thereby inhibiting the operational amplifier direct loss modulation and the operational amplifier low-frequency noise, and improving the precision of the whole circuit and the ADC.
In order to prevent the overload of the integrator and reduce the overall noise of the circuit, the invention adopts a two-stage operational amplifier 6 with low noise, high gain and large output swing. The specific circuit structure of the fully differential operational amplifier 6 can be shown in fig. 6, which is a basic two-stage operational amplifier with miller compensation. Where Vbias1 and Vbias2 are bias voltages, vip and Vin are differential voltage input signals, vop and Von are differential voltage output signals. The first PMOS tube M1 and the second PMOS tube M2 are amplifying tubes of the first-stage amplifier, the first NMOS tube M3 and the second NMOS tube M4 are current source load tubes of the first-stage amplifier, the third NMOS tube M5 and the fourth NMOS tube M6 are amplifying tubes of the second-stage amplifier, the third PMOS tube M7 and the fourth PMOS tube M8 are current source load tubes of the second-stage amplifier, and the fifth PMOS tube M9 is a tail current source. In order to ensure the stability of the circuit, a first resistor R1, a second resistor R2, a first capacitor C1 and a second capacitor C2 are added between the primary amplifier and the secondary amplifier to serve as miller compensation. The fully differential operational amplifier 6 can prevent overload of an integrator, reduce the noise of the whole circuit and improve the signal gain.
As shown in fig. 3 to 4, the non-overlapping clock generation module 1 includes a sampling phase clock generation module 11 and an integration phase clock generation module 12; the sampling and integrating control circuit 2 comprises a sampling switch control circuit, an integrating switch control circuit and a sampling capacitor C S The method comprises the steps of carrying out a first treatment on the surface of the The sampling phase clock generation module 11 is connected with the sampling switch control circuit and is used for outputting a sampling clock control signal 13 to control the sampling switch control circuit to conduct the sampling capacitor C S The sampling circuit of the circuit is used for sampling the input differential voltage signal to realize the sampling stage work. The integral phase clock generation module 12 is connected with the integral switch control circuit and is used for outputting an integral clock control signal 14 to control the integral switch control circuit to conduct the sampling capacitor C S A first chopper modulation circuit 3 and an integration capacitor C i A loop between them to sample the capacitance C S The sampled differential voltage signal is output to an integrating capacitor C i And the first chopper modulation circuit 3, the integration phase operation is realized.
Sampling capacitor C when the circuit is in the integrating stage S And an integrating capacitor C i Charge in (C) is redistributed, and capacitance C is sampled S Is accumulated in integrating capacitor C i On the other hand, there are
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As shown in fig. 4-5, the sampling clock control signal 13 and the integration clock control signal 14 are two-phase non-overlapping clocks and are opposite to each other. The sampling clock control signal 13 comprises a first sampling clock control signal P1D and a second sampling clock control signal P1, and the integration clock control signal 14 comprises a first integration clock control signal P2D and a second integration clock control signal P2. A preset interval time is arranged between the sampling clock control signal 13 and the integration clock control signal 14, namely, when the sampling clock control signal 13 enters a falling edge, the integration clock control signal 14 enters a rising edge after a first preset interval time; similarly, the sampling clock control signal 13 enters the rising edge after the second predetermined interval time when the integration clock control signal 14 enters the falling edge. The first preset interval time and the second preset interval time may be set to be the same or different, and the first preset interval time and the second preset interval time are preferably 1 to 2 percent of the sampling period time, but are not limited thereto, and the specific value thereof may be adjusted according to actual requirements. Wherein, the chopping frequencies of the first chopping control signal chop_clk and the second chopping control signal chop_clkn are each preferably half of the sampling frequency of the sampling stage. Note that, the timing chart of the second chopping control signal chop_clkn is not shown in the timing chart of fig. 5.
As shown in fig. 3 to 5, the sampling switch control circuit includes a first sampling switch S1, a second sampling switch S2, a third sampling switch S5 and a fourth sampling switch S6, the integrating switch control circuit includes a first integrating switch S3, a second integrating switch S4, a third integrating switch S7 and a fourth integrating switch S8, and the sampling capacitor includes a first sampling capacitor 8 and a second sampling capacitor 9; the input ends of the first sampling switch S1 and the second sampling switch S2 are respectively connected with the corresponding differential voltage signal input end V ip And differential voltage signal input terminal V in The output end of the first sampling switch S1 is connected with the output end of the second sampling switch S2 through the first sampling capacitor 8, the third sampling switch S5, the fourth sampling switch S6, the second sampling capacitor 9The output end of the first sampling switch S1 is connected with the output end of the second sampling switch S2 through a first integrating switch S3 and a second integrating switch S4 in sequence; the connection end between the first integrating switch S3 and the second integrating switch S4 and the connection end between the third sampling switch S5 and the fourth sampling switch S6 are both connected with the common-mode voltage signal input end V cm The connection end between the top plate of the first sampling capacitor 8 and the third sampling switch S5 is respectively connected with one end of the first integrating capacitor 51 and the first input end of the first chopper modulation circuit 3 through the third integrating switch S7, and the connection end between the top plate of the second sampling capacitor 9 and the fourth sampling switch S6 is respectively connected with one end of the second integrating capacitor 52 and the second input end of the first chopper modulation circuit 3 through the fourth integrating switch S8.
As shown in fig. 3 to 5, the sampling phase clock generation module 11 includes a first sampling signal output terminal and a second sampling signal output terminal; the first sampling signal output end is respectively connected with the first sampling switch S1 and the second sampling switch S2 and is used for outputting a first sampling clock control signal P1D to control the on-off state of the first sampling switch S1 and the second sampling switch S2; the second sampling signal output end is respectively connected with the third sampling switch S5 and the fourth sampling switch S6 and is used for outputting a second sampling clock control signal P1 to control the on-off state of the third sampling switch S5 and the fourth sampling switch S6; the first sampling clock control signal P1D is a delayed signal of the second sampling clock control signal P1, and the first sampling clock control signal P1D enters the falling edge after being delayed for a preset time to delay the on state of the first sampling switch S1 and the second sampling switch S2. The rising edges of the first sampling clock control signal P1D and the second sampling clock control signal P1 are the same. The predetermined time of the delay is preferably 1 to 2 percent of the sampling period, but is not limited thereto, and the specific value thereof can be adjusted according to actual requirements.
It should be noted that, the sampling phase clock generating module 11 outputs the first sampling clock control signal P1D and the second sampling clock control signal P1 respectively, so as to control the first sampling switch S1, the second sampling switch S2, the third sampling switch S5 and the fourth sampling switch S6 to be turned on, and at this time, the first sampling capacitor 8 and the second sampling capacitor 9 sample the differential voltage signals correspondingly input respectively. When the sampling operation is completed, the second sampling clock control signal P1 enters a falling edge before the first sampling clock control signal P1D, the third sampling switch S5 and the fourth sampling switch S6 are opened in advance, top polar plates (i.e. output nodes) of the first sampling capacitor 8 and the second sampling capacitor 9 are high-resistance nodes, and no discharging passage exists for charges; when the first sampling clock control signal P1D is delayed for a preset time and then enters a falling edge, the corresponding first sampling switch S1 and the second sampling switch S2 are disconnected, and the voltage value of the top plate of the corresponding sampling capacitor cannot be influenced by charge injection generated by the corresponding switch, so that the influence of channel charge injection on the output node of the corresponding sampling capacitor is eliminated.
As shown in fig. 3-5, the integral phase clock generation module 12 includes a first integral signal output and a second integral signal output; the first integration signal output end is respectively connected with the first integration switch S3 and the second integration switch S4 and is used for outputting a first integration clock control signal P2D to control the on-off state of the first integration switch S3 and the second integration switch S4; the second integral signal output end is respectively connected with the third integral switch S7 and the fourth integral switch S8 and is used for outputting a second integral clock control signal P2 to control the on-off state of the third integral switch S7 and the fourth integral switch S8; the first integration clock control signal P2D is a delay signal of the second integration clock control signal P2, and the first integration clock control signal P2D enters the falling edge after being delayed for a preset time to delay the on state of the first integration switch S3 and the second integration switch S4. The rising edges of the first integrated clock control signal P2D and the second integrated clock control signal P2 are the same. The predetermined time of the delay is preferably 1 to 2 percent of the sampling period, but is not limited thereto, and the specific value thereof can be adjusted according to actual requirements.
It should be noted that, the integrated phase clock generating module 12 outputs the first integrated clock control signal P2D and the second integrated clock control signal P2, so as to control the first integrating switch S3, the second integrating switch S4, the third integrating switch S7, and the fourth integrating switch S8 to be turned on, and at this time, the first sampling capacitor 8 and the second sampling capacitor 9 output the sampled differential voltage signals to the corresponding integrating capacitor and the corresponding input terminal of the first chopper modulation circuit 3, respectively. When the integration operation is completed, the second integration clock control signal P2 enters a falling edge before the first integration clock control signal P2D, the third integration switch S7 and the fourth integration switch S8 are opened in advance, top plates (all high-resistance nodes) of the first sampling capacitor 8 and the second sampling capacitor 9 enter the falling edge after the first sampling clock control signal P1D delays for a preset time, and the corresponding first integration switch S3 and the second integration switch S4 are opened, so that error influence caused by channel charge injection effect is eliminated.
The clock control mode eliminates the channel charge injection effect by adopting a two-phase non-overlapping clock and combining a bottom plate sampling mode of a sampling capacitor in the sampling integral control circuit 2; the clock feed-through effect is eliminated through the fully-differential symmetrical circuit structure, so that the influence on the sampling precision of signals is avoided.
It should be noted that, the first sampling switch S1 and the second sampling switch S2 are both gate voltage bootstrap switches. The specific circuit structure of the gate voltage bootstrap switch may be shown in fig. 7, and the circuit structure and the working principle thereof will not be described in detail herein. The clk_sample signal end is an integral clock control signal, and the clk_hold signal end is a sampling clock control signal for controlling the on operation of the gate voltage bootstrap switch. The Vin signal end and the Vout signal end are respectively an input end and an output end of the grid voltage bootstrap switch.
The third sampling switch S5, the fourth sampling switch S6, the first integrating switch S3, the second integrating switch S4, the third integrating switch S7 and the fourth integrating switch S8 are all CMOS switches. The structure of a specific circuit of the CMOS switch can be shown in fig. 8, which is a complementary MOS circuit composed of an NMOS transistor and a PMOS transistor. The signal end A and the signal end Z are input ends and output ends of the CMOS switch, and the gate end of the NMOS tube and the gate end of the PMOS tube are connected with corresponding clock control signals so as to control the on-state operation of the CMOS switch.
Compared with the existing single-tube switch, the invention adopts the CMOS switch with small area, power to ground output range and higher on-resistance linearity, has simple structure and higher on-resistance linearity than the single-tube switch, and can effectively reduce the error caused by the on-resistance nonlinearity. The gate voltage bootstrap switch with better linearity is adopted on a key signal input path, and the gate source voltage of the switch is stabilized through a charge pump boosting technology, so that the on-resistance is stabilized and is not changed along with the change of an input signal, errors caused by the nonlinear on-resistance are avoided, and the circuit precision is improved.
In summary, the invention is applied to the dynamic error elimination integrator of the high-precision Sigma-Delta ADC, can dynamically eliminate the channel charge injection effect and the clock feed-through effect to avoid influencing the sampling precision of signals, can dynamically eliminate the errors caused by non-ideal factors such as nonlinear on-resistance of the switch, operational amplifier direct loss, operational amplifier low-frequency noise and the like, and can effectively improve the precision of the whole Sigma-Delta ADC.
Specifically, the clock feedthrough effect is eliminated by adopting a fully differential symmetrical circuit structure; the channel charge injection effect is eliminated by adopting a two-phase non-overlapping clock and combining a bottom plate sampling mode of a sampling capacitor; the CMOS switch with small area, power supply to ground output range and high on-resistance linearity is adopted by part of the switches, and the grid voltage bootstrap switch is adopted on a key signal input path so as to obtain constant on-resistance, thereby reducing and eliminating errors caused by non-linearity of the on-resistance; the full differential operational amplifier 6 of the two-stage operational amplifier with lower noise and larger output swing is adopted to prevent the overload of the integrator and reduce the overall noise of the circuit; the low-frequency noise of the operational amplifier and the DC offset of the operational amplifier are restrained by adopting a chopping technology. The dynamic error elimination is realized by the mode, so that the accuracy of the whole ADC is improved.
The foregoing disclosure is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the claims herein, as equivalent changes may be made in the claims herein without departing from the scope of the invention.
Claims (10)
1. The dynamic error elimination integrator applied to the high-precision Sigma-Delta ADC is characterized by comprising a non-overlapping clock generation module, a sampling integration control circuit, a first chopper modulation circuit, a second chopper modulation circuit, an integration capacitor and a fully differential operational amplifier;
the input end of the sampling integration control circuit is connected with the signal input end, two output ends of the sampling integration control circuit are respectively connected with the input end of the first chopper modulation circuit and one end of the integration capacitor, and the other end of the integration capacitor is respectively connected with the output end of the second chopper modulation circuit and the signal output end;
the input end of the fully differential operational amplifier is connected with the output end of the first chopper modulation circuit, and the output end of the fully differential operational amplifier is connected with the input end of the second chopper modulation circuit;
the non-overlapping clock generation module is connected with the sampling integral control circuit and is used for outputting a two-phase non-overlapping clock control signal to control the sampling integral control circuit to sample the input differential voltage signal and outputting the sampled differential voltage signal to the integral capacitor and the first chopper modulation circuit.
2. The dynamic error cancellation integrator of claim 1, further comprising a chopper clock generation module coupled to the first chopper modulation circuit and the second chopper modulation circuit, respectively, for outputting a chopper control signal to control signal modulation operations of the first chopper modulation circuit and the second chopper modulation circuit, respectively.
3. The dynamic error cancellation integrator of claim 2, wherein the first chopper modulation circuit includes a first chopper switch, a second chopper switch, a third chopper switch, and a fourth chopper switch;
the input ends of the first chopping switch and the second chopping switch are respectively connected with the first output end of the sampling integration control circuit and one end of the first integration capacitor, and the input ends of the third chopping switch and the fourth chopping switch are respectively connected with the second output end of the sampling integration control circuit and one end of the second integration capacitor;
the output ends of the first chopping switch and the third chopping switch are respectively connected with the positive input end of the fully differential operational amplifier, and the output ends of the second chopping switch and the fourth chopping switch are connected with the negative input end of the fully differential operational amplifier;
the chopping clock generation module is respectively connected with the first chopping switch, the second chopping switch, the third chopping switch and the fourth chopping switch and is used for outputting a first chopping control signal to respectively control the on-off states of the first chopping switch and the fourth chopping switch and outputting a second chopping control signal to respectively control the on-off states of the second chopping switch and the third chopping switch.
4. The dynamic error cancellation integrator of claim 3, wherein the second chopper modulation circuit includes a fifth chopper switch, a sixth chopper switch, a seventh chopper switch, and an eighth chopper switch;
the input ends of the fifth chopping switch and the sixth chopping switch are connected with the negative output end of the fully differential operational amplifier, and the input ends of the seventh chopping switch and the eighth chopping switch are connected with the positive output end of the fully differential operational amplifier;
the output ends of the fifth chopper switch and the seventh chopper switch are respectively connected with the first signal output end and the other end of the first integrating capacitor, and the output ends of the sixth chopper switch and the eighth chopper switch are respectively connected with the second signal output end and the other end of the second integrating capacitor;
the chopping clock generation module is respectively connected with the fifth chopping switch, the sixth chopping switch, the seventh chopping switch and the eighth chopping switch and is used for outputting a first chopping control signal to respectively control the on-off states of the fifth chopping switch and the eighth chopping switch and outputting a second chopping control signal to respectively control the on-off states of the sixth chopping switch and the seventh chopping switch.
5. The dynamic error cancellation integrator of any one of claims 3 to 4, wherein the first chopping control signal and the second chopping control signal are mutually inverted.
6. The dynamic error cancellation integrator of claim 1, wherein the non-overlapping clock generation module includes a sampling phase clock generation module and an integrating phase clock generation module; the sampling integral control circuit comprises a sampling switch control circuit, an integral switch control circuit and a sampling capacitor;
the sampling phase clock generation module is connected with the sampling switch control circuit and is used for outputting a sampling clock control signal to control the sampling switch control circuit to conduct a sampling loop of the sampling capacitor so as to sample an input differential voltage signal;
the integral phase clock generation module is connected with the integral switch control circuit and is used for outputting an integral clock control signal to control the integral switch control circuit to conduct a loop among the sampling capacitor, the first chopper modulation circuit and the integral capacitor so as to output differential voltage signals sampled by the sampling capacitor to the integral capacitor and the first chopper modulation circuit;
the sampling clock control signal and the integrating clock control signal are two-phase non-overlapping clocks and are opposite in phase.
7. The dynamic error cancellation integrator of claim 6, wherein the sampling switch control circuit includes a first sampling switch, a second sampling switch, a third sampling switch, and a fourth sampling switch, the integration switch control circuit includes a first integration switch, a second integration switch, a third integration switch, and a fourth integration switch, the sampling capacitance includes a first sampling capacitance and a second sampling capacitance;
the input ends of the first sampling switch and the second sampling switch are respectively connected with corresponding differential voltage signal input ends, the output end of the first sampling switch is connected with the output end of the second sampling switch through the first sampling capacitor, the third sampling switch, the fourth sampling switch and the second sampling capacitor in sequence, and the output end of the first sampling switch is also connected with the output end of the second sampling switch through the first integrating switch and the second integrating switch in sequence;
the connection end between the first integrating switch and the second integrating switch and the connection end between the third sampling switch and the fourth sampling switch are connected with a common-mode voltage signal input end, the connection end between the top pole plate of the first sampling capacitor and the third sampling switch is connected with one end of the first integrating capacitor and the first input end of the first chopper modulation circuit respectively through the third integrating switch, and the connection end between the top pole plate of the second sampling capacitor and the fourth sampling switch is connected with one end of the second integrating capacitor and the second input end of the first chopper modulation circuit respectively through the fourth integrating switch.
8. The dynamic error cancellation integrator of claim 7, wherein the sampling phase clock generation module includes a first sampling signal output and a second sampling signal output;
the first sampling signal output end is respectively connected with the first sampling switch and the second sampling switch and is used for outputting a first sampling clock control signal to control the on-off states of the first sampling switch and the second sampling switch;
the second sampling signal output end is respectively connected with the third sampling switch and the fourth sampling switch and is used for outputting a second sampling clock control signal to control the on-off states of the third sampling switch and the fourth sampling switch;
the first sampling clock control signal is a delay signal of the second sampling clock control signal, and enters a falling edge after being delayed for a preset time so as to delay the on state of the first sampling switch and the second sampling switch to be disconnected.
9. The dynamic error cancellation integrator of claim 7, wherein the integral phase clock generation module includes a first integral signal output and a second integral signal output;
the first integral signal output end is respectively connected with the first integral switch and the second integral switch and is used for outputting a first integral clock control signal to control the on-off states of the first integral switch and the second integral switch;
the second integral signal output end is respectively connected with the third integral switch and the fourth integral switch and is used for outputting a second integral clock control signal to control the on-off states of the third integral switch and the fourth integral switch;
the first integral clock control signal is a delay signal of the second integral clock control signal, and enters a falling edge after being delayed for a preset time so as to delay the on state of the first integral switch and the second integral switch to be disconnected.
10. The dynamic error cancellation integrator of any one of claims 7 to 9, wherein the first and second sampling switches are both gate voltage bootstrap switches;
the third sampling switch, the fourth sampling switch, the first integrating switch, the second integrating switch, the third integrating switch and the fourth integrating switch are all CMOS switches.
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