CN106292818B - Fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC - Google Patents
Fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC Download PDFInfo
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- CN106292818B CN106292818B CN201610710476.3A CN201610710476A CN106292818B CN 106292818 B CN106292818 B CN 106292818B CN 201610710476 A CN201610710476 A CN 201610710476A CN 106292818 B CN106292818 B CN 106292818B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The present invention relates to a kind of fully differential generating circuit from reference voltage and Wireless Telecom Equipment suitable for pipeline ADC.The fully differential generating circuit from reference voltage 10, including：Initial reference voltage input VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level shifter V1, second electrical level shift unit V2, common mode feedback circuit CMFB, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and first switch pipe M1, second switch pipe M2.The embodiment of the present invention can realize preferable PSRR, with good stability, and can be quickly established to stable state.The reference voltage of the high amplitude of oscillation is exported simultaneously.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of fully differential reference voltage suitable for pipeline ADC
Generation circuit and Wireless Telecom Equipment.
Background technology
With the fast development of video and wireless communication technology, Wireless Telecom Equipment is to analog-digital converter (Analog-
To-digital converter, abbreviation ADC) performance propose more strict requirements.ADC is meeting high-speed high accuracy
In the case of also need to have both good exchange performance and if sampling ability.The ADC i.e. pipeline ADC for possessing pipeline organization exists
It can realize and trade off well in terms of sampling rate, conversion accuracy, power consumption, therefore obtained extensively in high-speed, high precision field
Using.
In pipeline ADC, the effect of generating circuit from reference voltage has two：(1) provide and compare in each stage pipeline structure
Compared with the threshold voltage of device；(2) gain of multiplication surplus (MultiplyingDigitaltoAnalogConverter, abbreviation are provided
MDAC reference voltage during difference) is made.Reference voltage needs very big driving force and is quickly established to stable state, so as to protect
Card MDAC is quickly set up.With the continuous improvement of the sample rate and precision of pipeline ADC, the performance of reference voltage turns to ADC
It is transsexual will to produce significantly more influence.
Existing generating circuit from reference voltage is frequently with two single end operational amplifiers and high speed voltage buffer (buffer)
To realize the output of reference voltage.But the output voltage swing of this structural reference voltage is limited, and easily by two single-ended fortune
The influence each lacked of proper care is put, so that output reference voltage is glanced off.
Accordingly, it would be desirable to which a kind of new generating circuit from reference voltage, with good stability, and can be quickly established to
Stable state, while realizing the high amplitude of oscillation output of reference voltage.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of suitable for the complete poor of pipeline ADC
Divide generating circuit from reference voltage and Wireless Telecom Equipment, preferable PSRR (Power Supply can be realized
Rejection Ratio, abbreviation PSRR), with good stability, and stable state can be quickly established to.It is simultaneously defeated
Go out the reference voltage of the high amplitude of oscillation.
An embodiment provides a kind of fully differential generating circuit from reference voltage 10 suitable for pipeline ADC,
Including：Initial reference voltage input VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level move
Position device V1, second electrical level shift unit V2, common mode feedback circuit CMFB, first resistor R1, second resistance R2,3rd resistor R3, the
Four resistance R4, the 5th resistance R5, the 6th resistance R6 and first switch pipe M1, second switch pipe M2；Wherein,
The first switch pipe M1, the 5th resistance R5, the 6th resistance R6 and the second switch pipe M2 are successively
It is serially connected between the power end VDD and the earth terminal GND；
The first resistor R1 and the second resistance R2 are sequentially connected in series in the earth terminal GND and the first switch pipe
M1 and the 5th resistance R5 are concatenated between the node to be formed；The 3rd resistor R3 and the 4th resistance R4 are sequentially connected in series
In the initial reference voltage input VREFConcatenated with the 6th resistance R6 and the second switch pipe M2 at the node to be formed
Between；
The positive input terminal Vin+ of the Full differential operational amplifier A1 is electrically connected to the first resistor R1 and described second
Resistance R2 is concatenated at the node A to be formed, and its negative input end Vin- is electrically connected to the 3rd resistor R3 and the 4th resistance R4
Concatenate at the node B formed, its negative output terminal Vout- and the first level shifter V1 is sequentially connected in series to the first switch
Pipe M1 control end, its positive output end Vout+ and second electrical level shift unit V2 is sequentially connected in series to the second switch pipe M2
Control end；
The input of the common mode feedback circuit CMFB is electrically connected to the 5th resistance R5 and the 6th resistance R6 strings
Connect at the node C to be formed and its output end is electrically connected to the Full differential operational amplifier A1.
In one embodiment of the invention, the first switch pipe M1 is NMOS tube, and the second switch pipe M2 is
PMOS.
In one embodiment of the invention, the source of the NMOS tube is connected with the substrate terminal of the NMOS tube；It is described
The source of PMOS is connected with the substrate terminal of the PMOS.
In one embodiment of the invention, in addition to the 3rd electric capacity C3 and the 4th electric capacity C4；The 3rd electric capacity C1's
One end is electrically connected to the control end of the first switch pipe M1 and the other end is electrically connected to the earth terminal GND；4th electricity
Appearance C4 one end is electrically connected to the control end of the second switch pipe M2 and the other end is electrically connected to the earth terminal GND.
In one embodiment of the invention, the Full differential operational amplifier A1 includes：3rd switching tube M3, the 4th open
Close pipe M4, the 5th switching tube M5, the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the 9th switching tube M9, the tenth
Switching tube M10, the 11st switching tube M11, the 12nd switching tube M12, the 13rd switching tube M13, the 14th switching tube M14,
15 switching tube M15, sixteenmo close pipe M16, the 17th switching tube M17 and eighteenmo and close pipe M18；Wherein,
The 3rd switching tube M3, the 4th switching tube M4 and the 8th switching tube M8 are sequentially connected in series in the power supply
Hold between the VDD and earth terminal GND, the control end of the 3rd switching tube M3 is electrically connected to the first bias voltage Vb1, described
4th switching tube M4 control end electrically connects the negative input end Vin-, and the control end of the 8th switching tube M8 is electrically connected to institute
State the 4th switching tube M4 and the 8th switching tube M8 is concatenated at the node to be formed；
The 5th switching tube M5 and the 9th switching tube M9 are sequentially connected in series in the 3rd switching tube M3 and described
Four switching tube M4 are concatenated at the node to be formed between the earth terminal GND, the control end electrical connection of the 5th switching tube M5
The positive input terminal Vin+, the 9th switching tube M9 control end are electrically connected to the 5th switching tube M5 and opened with the described 9th
Pipe M9 is closed to concatenate at the node to be formed；
The transmission end of the 6th switching tube M6 is electrically connected the 5th switching tube M5 and the 9th switching tube M9
Concatenate at the node Y formed and earth terminal GND and its control end are electrically connected to the control end of the 8th switching tube M8；Described
Seven switching tube M7 transmission end is electrically connected the 4th switching tube M4 and concatenates the nodes X to be formed with the 8th switching tube M8
Place and earth terminal GND and its control end are electrically connected to the control end of the 9th switching tube M9；
The 17th switching tube M17, the 15th switching tube M15, the 13rd switch M13, the described 11st
Switch M11 and the tenth switching tube M10 is sequentially connected in series between the power end VDD and the earth terminal GND, and the described tenth
Seven switching tube M17 control end is electrically connected to the second bias voltage Vb2, the 15th switching tube M15 control end electrical connection
To the 3rd bias voltage Vb3, the control end of the 13rd switching tube M13 is electrically connected to the 4th bias voltage Vb4, the described tenth
One switching tube M11 control end is electrically connected to the 4th switching tube M4 and concatenates the nodes X to be formed with the 8th switching tube M8
Place, the control end of the tenth switching tube M10 is electrically connected to the input of the common mode feedback circuit CMFB, the negative output terminal
Vout- is electrically connected to the 15th switching tube M15 and the 13rd switch M13 is concatenated at the node to be formed；
The eighteenmo closes pipe M18, the sixteenmo and closes pipe M16, the 14th switch M14 and the described 12nd
Switching tube M12 is sequentially connected in series to be concatenated in the power end VDD with the 11st switching tube M11 and the tenth switching tube M10
Between the node of formation, the control end that the eighteenmo closes pipe M18 electrically connects the second bias voltage Vb2, and described the
The control end that sixteenmo closes pipe M16 electrically connects the 3rd bias voltage Vb3, the control end electricity of the 14th switching tube M14
The 4th bias voltage Vb4 is connected, the 12nd switching tube M12 is electrically connected to the 5th switching tube M5 and the described 9th
Switching tube M9 is concatenated at the node Y to be formed, and the positive output end Vout+ is electrically connected to the sixteenmo and closes pipe M16 and described
14th switch M14 is concatenated at the node to be formed.
In one embodiment of the invention, the 3rd switching tube M3, the 4th switching tube M4, the 5th switch
Pipe M5, the 15th switching tube M15, the sixteenmo close pipe M16, the 17th switching tube M17 and the described 18th
Switching tube M18 is PMOS, the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the described 9th
Switching tube M9, the tenth switching tube M10, the 11st switching tube M11, the 12nd switching tube M12, the described 13rd
Switching tube M13, the 14th switching tube M14 are NMOS tube.
In one embodiment of the invention, the first level shifter V1 includes：First switch K1, second switch
K2, the 3rd switch K3, the 4th switch K4, the first electric capacity C1, the 5th electric capacity C5 and the first dc source Vbp1；Wherein, described
The one switch K1 and second switch K2 is sequentially connected in series in the first dc source Vbp1 and the Full differential operational amplifier
Between the A1 negative output terminal Vout-, the 3rd switch K3 and the 4th switch K4 are sequentially connected in series in the power end
Between VDD and the first switch pipe M1 control end；One end of the first electric capacity C1 is electrically connected to the fully differential computing
The amplifier A1 negative output terminal Vout- and the other end is electrically connected to the control end of the first switch pipe M1, the described 5th
Electric capacity C5 one end is electrically connected to the first switch K1 and second switch K2 and concatenated at the node to be formed and other end electricity
It is connected to the 3rd switch K3 and the 4th switch K4 is concatenated at the node to be formed.
In one embodiment of the invention, the second electrical level shift unit V2 includes：5th switch K5, the 6th switch
K6, the 7th switch K7, the 8th switch K8, the second electric capacity C2, the 6th electric capacity C6 and the second dc source Vbn1；Wherein, described
Five switch K5 and the 6th switch K6 are sequentially connected in series in the second dc source Vbn1 and the Full differential operational amplifier
Between the A1 positive output end Vout+, the 7th switch K7 and the 8th switch K8 are sequentially connected in series in the earth terminal
Between GND and the second switch pipe M2 control end；One end of the second electric capacity C2 is electrically connected to the fully differential computing
The amplifier A1 positive output end Vout+ and the other end is electrically connected to the control end of the second switch pipe M2, the described 6th
Electric capacity C6 one end is electrically connected to the 5th switch K5 and the 6th switch K6 is concatenated at the node to be formed and other end electricity
It is connected to the 7th switch K7 and the 8th switch K8 is concatenated at the node to be formed.
In one embodiment of the invention, in addition to：19th switching tube M19, the 20th switching tube M20, the 7th electricity
Hinder R7 and the 8th resistance R8；The 19th switching tube M19, the 7th resistance R7, the 8th resistance R8 and described second
Ten switching tube M20 are sequentially connected in series between the power end VDD and the earth terminal GND, and the 19th switching tube M19
Control end is electrically connected to the control end of the first switch pipe M1, and the control end of the 20th switching tube M20 is electrically connected to institute
Second switch pipe M2 control end is stated, the 19th switching tube M19 and the 7th resistance R7 concatenate the node to be formed output
Reference voltage high level HVREF, the 8th resistance R8 and the 20th switching tube M20 concatenate the node to be formed output reference
Voltage low level LVREF。
Another embodiment of the present invention provides a kind of Wireless Telecom Equipment, including analog-digital converter, wherein, the mould
Intending digital quantizer includes any described fully differential generating circuit from reference voltage 10 in above-described embodiment.
Compared with prior art, beneficial effects of the present invention：
(1) source electrode that the output buffer of fully differential generating circuit from reference voltage of the present invention is only made up of transistor M1 and M2
Follower realizes that circuit structure is simple, and can be reference voltage HVREFAnd LVREFVery big driving current is provided, with realize compared with
Fast reference voltage is set up.
(2) the Full differential operational amplifier A1 in fully differential generating circuit from reference voltage of the invention is by using transistor
M6-M9 forms positive feedback loop, so as to obtain great DC open-loop voltage gains, is fully differential generating circuit from reference voltage
Backfeed loop provides available sufficiently large loop gain.
(3) due to the decay and the effect of feedback factor of series capacitance, the loop of fully differential generating circuit from reference voltage increases
Benefit is a very low value.Fully differential generating circuit from reference voltage of the present invention has good stability, and can quickly set up
To stable state, so as to ensure MDAC quick foundation.
(4) generating circuit from reference voltage of the invention uses fully differential structure, can effectively resist the influence of common-mode noise,
The reference voltage of the high amplitude of oscillation can be exported simultaneously.
Brief description of the drawings
Fig. 1 is a kind of electricity of fully differential generating circuit from reference voltage suitable for pipeline ADC provided in an embodiment of the present invention
Line structure schematic diagram；
Fig. 2 is another fully differential generating circuit from reference voltage suitable for pipeline ADC provided in an embodiment of the present invention
Electrical block diagram；
Fig. 3 is a kind of electrical block diagram of Full differential operational amplifier provided in an embodiment of the present invention；
Fig. 4 is a kind of electrical block diagram of first level shifter provided in an embodiment of the present invention；
Fig. 5 is a kind of electrical block diagram of second electrical level shift unit provided in an embodiment of the present invention；
Fig. 6 for it is provided in an embodiment of the present invention another be suitable to the fully differential generating circuit from reference voltage of pipeline ADC
Electrical block diagram；
Fig. 7 is a kind of circuit theory schematic diagram of level shifter provided in an embodiment of the present invention；
Fig. 8 is a kind of friendship of fully differential generating circuit from reference voltage suitable for pipeline ADC provided in an embodiment of the present invention
Flow schematic equivalent circuit.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 to Fig. 6 is referred to, Fig. 1 is a kind of fully differential suitable for pipeline ADC provided in an embodiment of the present invention with reference to electricity
The electrical block diagram of generation circuit is pressed, Fig. 2 is another fully differential suitable for pipeline ADC provided in an embodiment of the present invention
The electrical block diagram of generating circuit from reference voltage, Fig. 3 is a kind of Full differential operational amplifier provided in an embodiment of the present invention
Electrical block diagram, Fig. 4 be a kind of electrical block diagram of first level shifter provided in an embodiment of the present invention, figure
5 be a kind of electrical block diagram of second electrical level shift unit provided in an embodiment of the present invention, and Fig. 6 provides for the embodiment of the present invention
Another be suitable to pipeline ADC fully differential generating circuit from reference voltage electrical block diagram.
Specifically, Fig. 1 is referred to, the fully differential generating circuit from reference voltage 10 includes：Initial reference voltage input
VREF, power end VDD, earth terminal GND, Full differential operational amplifier A1, the first level shifter V1, second electrical level shift unit V2,
Common mode feedback circuit CMFB, first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th
Resistance R6 and first switch pipe M1, second switch pipe M2；Wherein, the first switch pipe M1, the 5th resistance R5, described
Six resistance R6 and the second switch pipe M2 are sequentially connected in series between the power end VDD and the earth terminal GND；Described first
Resistance R1 and the second resistance R2 are sequentially connected in series in the earth terminal GND and the first switch pipe M1 and the 5th resistance
R5 is concatenated between the node to be formed；The 3rd resistor R3 and the 4th resistance R4 are sequentially connected in series in initial reference electricity
Press input VREFBetween the node to be formed being concatenated with the 6th resistance R6 and the second switch pipe M2；The fully differential
The positive input terminal Vin+ of operational amplifier A 1 is electrically connected to the first resistor R1 and the second resistance R2 concatenates the section to be formed
At point A, its negative input end Vin- is electrically connected to the 3rd resistor R3 and the 4th resistance R4 is concatenated at the node B to be formed,
Its negative output terminal Vout- and the first level shifter V1 is sequentially connected in series to the control end of the first switch pipe M1, and it is just
The output end vo ut+ and second electrical level shift unit V2 is sequentially connected in series to the control end of the second switch pipe M2；The common mode
Feedback circuit CMFB input be electrically connected to the 5th resistance R5 and the 6th resistance R6 concatenate at the node C to be formed and
Its output end is electrically connected to the Full differential operational amplifier A1.
Alternatively, the first switch pipe M1 is NMOS tube, and the second switch pipe M2 is PMOS.Further, institute
The source for stating NMOS tube is connected with the substrate terminal of the NMOS tube；The substrate terminal of the source of the PMOS and the PMOS connects
Connect.
Preferably, Fig. 2 is referred to, the fully differential generating circuit from reference voltage 10 also includes the 3rd electric capacity C3 and the 4th electric capacity
C4；The control end and the other end that one end of the 3rd electric capacity C1 is electrically connected to the first switch pipe M1 are electrically connected to described connect
Ground terminal GND；The control end and the other end that one end of the 4th electric capacity C4 is electrically connected to the second switch pipe M2 are electrically connected to
The earth terminal GND.
Alternatively, Fig. 3 is referred to, the Full differential operational amplifier A1 includes：3rd switching tube M3, the 4th switching tube
M4, the 5th switching tube M5, the 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the 9th switching tube M9, the tenth switch
Pipe M10, the 11st switching tube M11, the 12nd switching tube M12, the 13rd switching tube M13, the 14th switching tube M14, the 15th
Switching tube M15, sixteenmo close pipe M16, the 17th switching tube M17 and eighteenmo and close pipe M18；Wherein,
The 3rd switching tube M3, the 4th switching tube M4 and the 8th switching tube M8 are sequentially connected in series in the power supply
Hold between the VDD and earth terminal GND, the control end of the 3rd switching tube M3 is electrically connected to the first bias voltage Vb1, described
4th switching tube M4 control end electrically connects the negative input end Vin-, and the control end of the 8th switching tube M8 is electrically connected to institute
State the 4th switching tube M4 and the 8th switching tube M8 is concatenated at the node to be formed；
The 5th switching tube M5 and the 9th switching tube M9 are sequentially connected in series in the 3rd switching tube M3 and described
Four switching tube M4 are concatenated at the node to be formed between the earth terminal GND, the control end electrical connection of the 5th switching tube M5
The positive input terminal Vin+, the 9th switching tube M9 control end are electrically connected to the 5th switching tube M5 and opened with the described 9th
Pipe M9 is closed to concatenate at the node to be formed；
The transmission end of the 6th switching tube M6 is electrically connected the 5th switching tube M5 and the 9th switching tube M9
Concatenate at the node Y formed and earth terminal GND and its control end are electrically connected to the control end of the 8th switching tube M8；Described
Seven switching tube M7 transmission end is electrically connected the 4th switching tube M4 and concatenates the nodes X to be formed with the 8th switching tube M8
Place and earth terminal GND and its control end are electrically connected to the control end of the 9th switching tube M9；
The 17th switching tube M17, the 15th switching tube M15, the 13rd switch M13, the described 11st
Switch M11 and the tenth switching tube M10 is sequentially connected in series between the power end VDD and the earth terminal GND, and the described tenth
Seven switching tube M17 control end is electrically connected to the second bias voltage Vb2, the 15th switching tube M15 control end electrical connection
To the 3rd bias voltage Vb3, the control end of the 13rd switching tube M13 is electrically connected to the 4th bias voltage Vb4, the described tenth
One switching tube M11 control end is electrically connected to the 4th switching tube M4 and concatenates the nodes X to be formed with the 8th switching tube M8
Place, the control end of the tenth switching tube M10 is electrically connected to the input of the common mode feedback circuit CMFB, the negative output terminal
Vout- is electrically connected to the 15th switching tube M15 and the 13rd switch M13 is concatenated at the node to be formed；
The eighteenmo closes pipe M18, the sixteenmo and closes pipe M16, the 14th switch M14 and the described 12nd
Switching tube M12 is sequentially connected in series to be concatenated in the power end VDD with the 11st switching tube M11 and the tenth switching tube M10
Between the node of formation, the control end that the eighteenmo closes pipe M18 electrically connects the second bias voltage Vb2, and described the
The control end that sixteenmo closes pipe M16 electrically connects the 3rd bias voltage Vb3, the control end electricity of the 14th switching tube M14
The 4th bias voltage Vb4 is connected, the 12nd switching tube M12 is electrically connected to the 5th switching tube M5 and the described 9th
Switching tube M9 is concatenated at the node Y to be formed, and the positive output end Vout+ is electrically connected to the sixteenmo and closes pipe M16 and described
14th switch M14 is concatenated at the node to be formed.
Wherein, the 3rd switching tube M3, the 4th switching tube M4, the 5th switching tube M5, the described 15th are opened
It is PMOS to close pipe M15, the sixteenmo and close pipe M16, the 17th switching tube M17 and the eighteenmo to close pipe M18,
The 6th switching tube M6, the 7th switching tube M7, the 8th switching tube M8, the 9th switching tube M9, the described tenth
Switching tube M10, the 11st switching tube M11, the 12nd switching tube M12, the 13rd switching tube M13, described
14 switching tube M14 are NMOS tube.
Alternatively, Fig. 4 is referred to, the first level shifter V1 includes：First switch K1, second switch K2, the 3rd
Switch K3, the 4th switch K4, the first electric capacity C1, the 5th electric capacity C5 and the first dc source Vbp1；Wherein, the first switch K1
It is sequentially connected in series with the second switch K2 in described in the first dc source Vbp1 and the Full differential operational amplifier A1
Between negative output terminal Vout-, it is described 3rd switch K3 and it is described 4th switch K4 be sequentially connected in series in the power end VDD with it is described
Between first switch pipe M1 control end；One end of the first electric capacity C1 is electrically connected to the Full differential operational amplifier A1's
The negative output terminal Vout- and the other end are electrically connected to the control end of the first switch pipe M1, the one of the 5th electric capacity C5
End be electrically connected to the first switch K1 and second switch K2 concatenate at the node to be formed and the other end be electrically connected to it is described
3rd switch K3 and the 4th switch K4 are concatenated at the node to be formed.
Alternatively, Fig. 5 is referred to, the second electrical level shift unit V2 includes：5th switch K5, the 6th switch K6, the 7th
Switch K7, the 8th switch K8, the second electric capacity C2, the 6th electric capacity C6 and the second dc source Vbn1；Wherein, the 5th switch K5
It is sequentially connected in series with the described 6th switch K6 in described in the second dc source Vbn1 and the Full differential operational amplifier A1
Between positive output end Vout+, it is described 7th switch K7 and it is described 8th switch K8 be sequentially connected in series in the earth terminal GND with it is described
Between second switch pipe M2 control end；One end of the second electric capacity C2 is electrically connected to the Full differential operational amplifier A1's
The positive output end Vout+ and the other end are electrically connected to the control end of the second switch pipe M2, the one of the 6th electric capacity C6
End be electrically connected to the 5th switch K5 and the 6th switch K6 concatenate at the node to be formed and the other end be electrically connected to it is described
7th switch K7 and the 8th switch K8 are concatenated at the node to be formed.
Alternatively, Fig. 6 is referred to, the fully differential generating circuit from reference voltage 10 also includes：19th switching tube M19,
20 switching tube M20, the 7th resistance R7 and the 8th resistance R8；It is the 19th switching tube M19, the 7th resistance R7, described
8th resistance R8 and the 20th switching tube M20 are sequentially connected in series between the power end VDD and the earth terminal GND, and
The control end of the 19th switching tube M19 is electrically connected to the control end of the first switch pipe M1, the 20th switching tube
M20 control end is electrically connected to the control end of the second switch pipe M2, the 19th switching tube M19 and the 7th resistance
R7 concatenates the node output reference voltage high level HV to be formedREF, the 8th resistance R8 and the 20th switching tube M20 string
Meet the node output reference voltage low level LV to be formedREF。
The present embodiment, the source electrode that the output buffer of fully differential generating circuit from reference voltage is made up of transistor M1 and M2
Follower realizes that circuit structure is simple, and can be reference voltage HVREFAnd LVREFVery big driving current is provided, with realize compared with
Fast reference voltage is set up；Full differential operational amplifier A1 forms positive feedback loop by using transistor M6-M9, so as to obtain
Great DC open-loop voltage gains, for fully differential generating circuit from reference voltage backfeed loop provide it is available sufficiently large
Loop gain；Due to the decay and the effect of feedback factor of series capacitance, the loop of fully differential generating circuit from reference voltage increases
Benefit is a very low value.Therefore, fully differential generating circuit from reference voltage of the present invention has good stability, and can be quick
Stable state is set up, so as to ensure MDAC quick foundation.
Embodiment two
Referring again to Fig. 1 to Fig. 6, and referring also to Fig. 7 to Fig. 8, Fig. 7 are a kind of level provided in an embodiment of the present invention
The circuit theory schematic diagram of shift unit；Fig. 8 is a kind of fully differential suitable for pipeline ADC provided in an embodiment of the present invention with reference to electricity
Press the electrical block diagram of generation circuit.Fully differential reference electricity of the present embodiment on the basis of above-described embodiment to the present invention
Pressure generation circuit 10 is described in detail.It is specific as follows：
Fig. 1 is referred to, fully differential generating circuit from reference voltage 10 provided in an embodiment of the present invention is that a closed loop feedback is returned
Road.The closed feedback loop is main by a Full differential operational amplifier A1,2 level shifters and 2 output buffers
Constitute.Wherein, the source follower formed by the first transistor M1 source followers formed and by second transistor M2 is defeated
Go out buffer.The first transistor M1 is nmos pass transistor, and second transistor M2 is PMOS transistor.
Specific circuit connecting relation is as follows：
Full differential operational amplifier A1 positive input terminal Vin+ is connected to first resistor R1 one end, and first resistor R1's is another
One end is grounded.Full differential operational amplifier A1 negative input end Vin- is connected to 3rd resistor R3 one end, 3rd resistor R3's
The other end is connected to initial reference voltage VREF(VREFProduced by band-gap reference and generating circuit from reference voltage).
The V1 of Full differential operational amplifier A1 negative output terminal Vout- the first level shifters of connection one end, the first electricity
The translational shifting device V1 other end is connected to the first transistor M1 grid.The drain electrode of the first transistor M1 connects supply voltage；
Together with source electrode is connected to substrate, output reference voltage high level HVREF。
Full differential operational amplifier A1 positive output end Vout+ is connected to second electrical level shift unit V2 one end, the second electricity
The translational shifting device V2 other end is connected to second transistor M2 grid.The drain electrode of the second transistor M2 connects power supply electricity
Pressure；Source electrode links together with substrate, output reference voltage low level LVREF。
The source and substrate of the first transistor M1 and second transistor M2 link together, and reduce what Vth was brought
It is non-linear.
Second resistance R2 one end is connected to Full differential operational amplifier A1 positive input terminal vout+, and the other end is connected to
The first transistor M1 source electrode.4th resistance R4 one end is connected to Full differential operational amplifier A1 negative input end Vout-, separately
One end is connected to second transistor M2 source electrode.
5th resistance R5 one end is connected to the first transistor M1 source electrode, and the other end and the 6th resistance R6 are connected to one
Rise, the 6th resistance R6 other end is connected to second transistor M2 source electrode.
Node C and the common-mode feedback electricity of Full differential operational amplifier that 5th resistance R5 and the 6th resistance R6 link together
The input on road (CMFB) is connected.The output end of common mode feedback circuit (CMFB) is connected to the tenth crystalline substance of Full differential operational amplifier
Body pipe M10 grid.
Wherein, common mode feedback circuit (CMFB) causes the common mode value of output reference voltage to maintain VDD/2.
3rd electric capacity C3 one end is connected to the first transistor M1 grid, other end ground connection；4th electric capacity C4 one end
It is connected to second transistor M2 grid, other end ground connection.
The 3rd electric capacity C3 and the 4th electric capacity C4 is grid decoupling capacitance.The first transistor M1 grid is by decoupling electricity
Hold C3 to realize to ground decoupling, second transistor M2 grid by decoupling capacitance C4 realize to decouple.This grid passes through solution
The structure that coupling electric capacity is realized to ground decoupling has good buffer action, reduces power line to the coupling of output end, improves
The PSRR of circuit.
Referring again to Fig. 1, ADC reference voltage high level HV in the present embodimentREFThe source formed by the first transistor M1
Pole follower output, reference voltage low level LVREFThe source follower output formed by second transistor M2.
In order to meet MDAC design accuracy requirement, output reference voltage will realize a height output amplitude of oscillation, first crystal
Pipe M1 grid voltage need to be higher than VDD, and second transistor M2 grid voltage need to be less than GND.In order to being used as output buffer
Transistor rational dc point is provided, introduced respectively in the positive output end and negative output terminal of Full differential operational amplifier
Level shifter V1 and V2.
Fig. 7 is referred to, level shifter V1 includes electric capacity C1 and C5, and electric capacity C5 one end is by switching K1 and DC voltage
Vbp1 is switched on or switched off, and is switched on or switched off by the one end for switching K2 and electric capacity C1；The electric capacity C5 other end is by switching K3
It is switched on or switched off with supply voltage VDD, and is switched on or switched off by the other end for switching K4 and electric capacity C1.Electric capacity C1 one end is also
The negative output terminal Vout- of Full differential operational amplifier is connected to, the other end is additionally coupled to the first transistor M1 grid.
Level shifter V2 includes electric capacity C2 and C6, electric capacity C6 one end connected by switching K5 and DC voltage Vbn1 or
Disconnect, and be switched on or switched off by the one end for switching K6 and electric capacity C2；The electric capacity C6 other end is connected by switching K7 and ground GND
Or disconnect, and be switched on or switched off by the other end for switching K8 and electric capacity C2.Electric capacity C2 one end is additionally attached to fully differential computing
The positive output end Vout+ of amplifier, the other end is additionally coupled to second transistor M2 grid.
Wherein, Φ 1 and Φ 2 are the not overlapping clocks of two-phase of level shifter, and Vbp1 and Vbn1 are DC voltages.Φ 1 is controlled
System switch K1, K3, K5, K7 closure and unlatching；Φ 2 controlling switch K2, K4, K6, K8 closure and unlatching.
Level shifter V1 causes voltage Vout1- to add C5 (VDD-Vbp1)/(C1+C5), level than voltage Vout-
Shift unit V2 causes voltage Vout1+ to reduce C6 (Vbn1-0)/(C2+C6) than voltage Vout+.By adjusting Vbp1 and Vbn1
Size, can be biased in suitable DC operation as the first transistor M1 and second transistor M2 of output buffer
Point, so as to provide output current for output reference voltage.
From the above mentioned, the source follower that the present embodiment is only made up of as the circuit of output end transistor M1 and M2 is real
Existing, circuit structure is simple, and can provide very big driving current for reference voltage HVREF and LVREF, to realize faster ginseng
Examine Voltage Establishment.Also, there is very high input impedance and relatively low output by the source follower that transistor M1 and M2 are constituted
Impedance, can drive the capacitive load in the switched capacitor network and MDAC in comparator.
The structure of the Full differential operational amplifier A1 in the generating circuit from reference voltage is described below：
The Full differential operational amplifier uses two-layer configuration, and first order pre-amplification stage improves overall using positive feedback structure
Gain, the second level be tube-in-tube structure amplifier.
Be the circuit diagram of the Full differential operational amplifier referring again to Fig. 3, in the circuit, node Vin+ and
Vin- is respectively the positive input terminal and negative input end of amplifier, and nodes X and Y are the positive output end and negative output of pre-amplification stage respectively
End, node Vout+ and Vout- are respectively the positive output end and negative output terminal of amplifier, and node VDD and GND connect supply voltage respectively
And ground voltage.
The operational amplifier of the embodiment includes：Third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th
Transistor M6, the 7th transistor M7, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11st transistor
M11, the tenth two-transistor M12, the 13rd transistor M13, the 14th transistor M14, the 15th transistor M15, the 16th crystalline substance
Body pipe M16, the 17th transistor M17, the 18th transistor M18, transistor M3-M5, M15-M18 are PMOS transistor, crystal
Pipe M6-M14 is nmos pass transistor, wherein,
Third transistor M3 grid is connected to the input Vb1 of the first bias voltage, and drain electrode is connected to the 4th transistor M4's
The source electrode of source electrode and the 5th transistor M5, third transistor M3 source ground.
4th transistor M4 grid is connected to negative input end Vin-, and drain electrode is connected to the 6th transistor M6 grid, the 8th crystalline substance
The drain electrode of body pipe M8 grid and the 7th transistor M7.4th transistor M4 source electrode is connected to third transistor M3 drain electrode and
Five transistor M5 source electrode.
5th transistor M5 grid is connected to positive input terminal Vin+, and drain electrode is connected to the 7th transistor M7 grid, the 9th crystalline substance
The drain electrode of body pipe M9 grid and the 6th transistor M6.5th transistor M5 source electrode is connected to third transistor M3 drain electrode and
Four transistor M4 source electrode.
6th transistor M6 grid is connected to the 4th transistor M4 drain electrode, the 8th transistor M8 grid, and the 7th crystalline substance
Body pipe M7 drain electrode.6th transistor M6 drain electrode is connected to the 5th transistor M5 drain electrode, the 7th transistor M7 grid and
Nine transistor M9 grid.6th transistor M6 source ground.
7th transistor M7 grid is connected to the 5th transistor M5 drain electrode, the 9th transistor M9 grid, and the 6th crystalline substance
Body pipe M6 drain electrode.7th transistor M7 drain electrode is connected to the 4th transistor M4 drain electrode, the 6th transistor M6 grid and
Eight transistor M8 grid.7th transistor M7 source ground.
8th transistor M8 grid is connected to the drain electrode of itself, and grid, the 7th transistor with the 6th transistor M6
M7 grid connection.8th transistor M8 source ground.
9th transistor M9 grid is connected to the drain electrode of itself, and grid, the 6th transistor with the 7th transistor M7
M6 grid connection.9th transistor M9 source ground.
Tenth transistor M10 grid is connected to common-mode feedback output end CMFB, and drain electrode is connected to the 11st transistor M11 source
Pole and the tenth two-transistor M12 source electrode, the tenth transistor M10 source ground.
11st transistor M11 grid is connected to the positive output end X of pre-amplification stage, and drain electrode is connected to the 13rd transistor M13
Drain electrode, the 11st transistor M11 source electrode is connected to the drain electrode of the tenth two-transistor M12 source electrode and the tenth transistor M10.
Tenth two-transistor M12 grid is connected to the negative output terminal Y of pre-amplification stage, and drain electrode is connected to the 14th transistor M14
Drain electrode, the tenth two-transistor M12 source electrode is connected to the drain electrode of the 11st transistor M11 source electrode and the tenth transistor M10.
13rd transistor M13 grid is connected to the input Vb4 of the 4th bias voltage, and drain electrode is connected to the 15th transistor
M15 drain electrode, the source electrode of the 13rd transistor is connected to the 17th transistor M17 drain electrode.
14th transistor M14 grid is connected to the input Vb4 of the 4th bias voltage, and drain electrode is connected to the 14th transistor
M14 drain electrode, the source electrode of the 14th transistor is connected to the 16th transistor M16 drain electrode.
15th transistor M15 grid is connected to the input Vb3 of the 3rd bias voltage, and drain electrode is connected to the 13rd transistor
M13 drain electrode, the source electrode of the 15th transistor is connected to the 17th transistor M17 drain electrode.
16th transistor M16 grid is connected to the input Vb3 of the 3rd bias voltage, and drain electrode is connected to the 14th transistor
M14 drain electrode, the source electrode of the 16th transistor is connected to the 18th transistor M18 drain electrode.
17th transistor M17 grid is connected to the input Vb2 of the second bias voltage, and drain electrode is connected to the 15th transistor
M15 source electrode, the 17th transistor M17 source electrode is connected to power supply.
18th transistor M18 grid is connected to the input Vb2 of the second bias voltage, and drain electrode is connected to the 16th transistor
M16 source electrode, the 18th transistor M18 source electrode is connected to power supply.
Wherein, transistor M3-M9 constitutes the pre-amplification stage of the Full differential operational amplifier, and transistor M10-M18 is constituted
The second level tube-in-tube structure of the Full differential operational amplifier.
The Full differential operational amplifier A1 of present invention pre-amplification stage circuit has two feedback paths, and first article is by the
The series current feedback of four transistor M4 and the 5th transistor M5 common source node, this feedback network is negative-feedback；Second
Article it is the shunt voltage feedback for connecting the 6th transistor M6 and the 7th transistor M7 grids and drain electrode, this feedback network is positive and negative
Feedback.
When positive and negative feedforward coefficient is more than degeneration factor, whole pre-amplification stage shows as positive feedback.When positive and negative feedforward coefficient is small
When degeneration factor, whole pre-amplification stage shows as negative-feedback.
Output impedance at the positive output nodes X of pre-amplification stage is：
Likewise, the output impedance at negative output node Y is：
Wherein, gm6, gm7, gm8, gm9 are transistor M6, M7, M8, M9 mutual conductance respectively.
The load transistor M8's and M9 of pre-amplification stage equal sized, transistor M6 and M7 size phase in the present embodiment
Deng, and M8 and M9 size of the size slightly larger than M6 and M7.Therefore, M8 mutual conductance is slightly larger than M6, and M9 mutual conductance is slightly larger than M7.
The output impedance of pre-amplification stage tends to a very big numerical value, and pre-amplification stage feedback network shows as positive feedback, so as to obtain
Great DC open-loop gains.
The second level of the present embodiment be Telescopic cascode amplifier there is provided gain at (gmro)2/ 2 orders of magnitude.Enter
One step improves the gain of the Full differential operational amplifier.
From the above mentioned, Full differential operational amplifier A1 of the invention forms positive and negative be fed back to by using transistor M6-M9
Road, so as to obtain great DC open-loop voltage gains, for the backfeed loop of fully differential generating circuit from reference voltage, provide can profit
Sufficiently large loop gain.
Referring again to Fig. 6, as a kind of preferred scheme, the embodiment of the present invention provides another reference voltage and produces electricity
Road.Increase open-loop branch 2 on the basis of Fig. 1, open-loop branch 2 is with K:1 breadth length ratio relation is replicated according to branch road 1.Open
The current ratio relation on electric current and branch road 1 on ring branch road 2 is K:1.
Wherein, the 19th transistor M19 drain electrode is connected to power vd D, and grid is connected with the first transistor M1 grid
Together.19th transistor M19 source electrode links together with substrate, output reference voltage high level HVREF。
20th transistor M20 grounded drain, the grid of grid and second transistor M2 links together.20th is brilliant
Body pipe M20 source electrode links together with substrate, output reference voltage LVREF.
7th resistance R7 one end is connected to the source electrode of the 19th transistor, and the other end is connected with the 8th resistance R8 one end
Together.The 8th resistance R8 other end is connected to the 20th transistor M20 source electrode.
From the above mentioned, the open-loop branch 2 of the output end of generating circuit from reference voltage preferably is followed by source electrode
Device is realized.The source follower of open-loop branch 2 has good buffer action, it is to avoid the shadow of voltage dithering and closed feedback loop
Ring, output reference voltage is more stablized.Power line can be reduced simultaneously to the coupling of output end, circuit is improved
PSRR。
HV is derived below according to the fully differential generating circuit from reference voltage shown in Fig. 1REFAnd LVREFExpression formula.
Resistor satisfied following relation in the backfeed loop：
R1=R2=R3=R4
R5=R6
According to breaking (the Intrinsic virtual cutoff) effect of the void of operational amplifier, list fully differential computing and put
Row nodal voltage equation is at the corresponding node A of device A1 positive input terminals greatly：
Listing row nodal voltage equation at the corresponding node B of Full differential operational amplifier A1 negative input ends is：
(VREF-Vin-)/R3=(Vin--LVREF)/R4
According to the imaginary short effect (Intrinsic virtual short) of operational amplifier, it can obtain：
Vin+=Vin-
By the symmetry of fully differential generating circuit from reference voltage, the voltage at node C can be obtained and met:
Vcom=(HVREF+LVREF)/2
Wherein, Vcom is the median of height reference voltage, and Full differential operational amplifier A1 output common mode voltage.
Output reference voltage high level HV can be obtained by above formulaREFWith reference voltage low level LVREFExpression formula：
HVREF=Vcom+VREF/2
LVREF=Vcom-VREF/2
VREF=HVREF-LVREF
Found out by expression formula, output reference voltage HVREFAnd LVREFIt is amplifier output common mode voltage Vcom and initial reference electricity
Press VREFFunction.Wherein, common mode feedback circuit (CMFB) causes the median Vcom of output reference voltage to maintain VDD/2, and
And initial reference voltage VREFProduced by band-gap reference and generating circuit from reference voltage.
From the above mentioned, fully differential generating circuit from reference voltage of the present invention can export accurate reference voltage high level HVREF
With reference voltage low level LVREF。
The stability to fully differential generating circuit from reference voltage is analyzed below, and Fig. 8 produces for fully differential reference voltage
The ac equivalent circuit figure of circuit, wherein, the influence of level shifter is not paid attention to.
According to Fig. 8, the loop gain of generating circuit from reference voltage is listed：
Wherein, gA1RoA1Full differential operational amplifier A1 gain is represented, C3/ (C3+C1) item is that operational amplifier A 1 is drawn
Pad value of the gain entered Jing Guo series capacitance C1, C3, the output gain of integrated circuit is attenuated as original C3/ (C1+C3).
1/(1+1/(gM2(R5//RdsM2))) be source follower transfer function, can have certain decay to gain.R3/(R3+R4)
Represent that output voltage feeds back to the voltage of Full differential operational amplifier input, i.e. feedback factor.
Find out from expression formula, due to the decay and the effect of feedback factor of series capacitance, fully differential reference voltage produces electricity
The loop gain on road is a very low value.
From the above mentioned, fully differential generating circuit from reference voltage of the present invention has good stability, and can quickly set up
To stable state, so as to ensure MDAC quick foundation.
Also, the generating circuit from reference voltage of the present invention uses fully differential structure, can effectively resist the shadow of common-mode noise
Ring, while the reference voltage of the high amplitude of oscillation can be exported.
Embodiment three
Present invention also offers a kind of Wireless Telecom Equipment, changing Wireless Telecom Equipment includes analog-digital converter, wherein,
The analog-digital converter includes any described fully differential generating circuit from reference voltage 10 in above-described embodiment.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of fully differential generating circuit from reference voltage (10) suitable for pipeline ADC, it is characterised in that including：Initial reference
Voltage input end (VREF), power end (VDD), earth terminal (GND), Full differential operational amplifier (A1), the first level shifter
(V1), second electrical level shift unit (V2), common mode feedback circuit (CMFB), first resistor (R1), second resistance (R2), 3rd resistor
(R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6) and first switch pipe (M1), second switch pipe (M2)；Its
In, the first switch pipe (M1), the 5th resistance (R5), the 6th resistance (R6) and the second switch pipe (M2) according to
It is secondary to be serially connected between the power end (VDD) and the earth terminal (GND)；
The first resistor (R1) and the second resistance (R2) are sequentially connected in series in the earth terminal (GND) and the first switch
Between the node for managing (M1) and the 5th resistance (R5) concatenation formation；The 3rd resistor (R3) and the 4th resistance
(R4) it is sequentially connected in series in the initial reference voltage input (VREF) and the 6th resistance (R6) and the second switch pipe
(M2) between the node that concatenation is formed；
The positive input terminal (Vin+) of the Full differential operational amplifier (A1) is electrically connected to the first resistor (R1) and described
Node (A) place that two resistance (R2) concatenation is formed, its negative input end (Vin-) is electrically connected to the 3rd resistor (R3) and described
Node (B) place that 4th resistance (R4) concatenation is formed, its negative output terminal (Vout-) and first level shifter (V1) are successively
Concatenate to the control end of the first switch pipe (M1), its positive output end (Vout+) and the second electrical level shift unit (V2) according to
It is secondary to concatenate to the control end of the second switch pipe (M2)；
The input of the common mode feedback circuit (CMFB) is electrically connected to the 5th resistance (R5) and the 6th resistance (R6)
Concatenate node (C) place formed and its output end is electrically connected to the Full differential operational amplifier (A1).
2. circuit (10) according to claim 1, it is characterised in that the first switch pipe (M1) is NMOS tube, described
Second switch pipe (M2) is PMOS.
3. circuit (10) according to claim 2, it is characterised in that the lining of the source of the NMOS tube and the NMOS tube
Bottom is connected；The source of the PMOS is connected with the substrate terminal of the PMOS.
4. circuit (10) according to claim 1, it is characterised in that also including the 3rd electric capacity (C3) and the 4th electric capacity
(C4)；The control end and the other end that one end of 3rd electric capacity (C3) is electrically connected to the first switch pipe (M1) are electrically connected to
The earth terminal (GND)；One end of 4th electric capacity (C4) is electrically connected to the control end of the second switch pipe (M2) and another
One end is electrically connected to the earth terminal (GND).
5. circuit (10) according to claim 1, it is characterised in that the Full differential operational amplifier (A1) includes：The
Three switching tubes (M3), the 4th switching tube (M4), the 5th switching tube (M5), the 6th switching tube (M6), the 7th switching tube (M7), the 8th
Switching tube (M8), the 9th switching tube (M9), the tenth switching tube (M10), the 11st switching tube (M11), the 12nd switching tube
(M12), the 13rd switching tube (M13), the 14th switching tube (M14), the 15th switching tube (M15), sixteenmo close pipe
(M16), the 17th switching tube (M17) and eighteenmo close pipe (M18)；Wherein,
3rd switching tube (M3), the 4th switching tube (M4) and the 8th switching tube (M8) are sequentially connected in series in the electricity
Between source (VDD) and the earth terminal (GND), the control end of the 3rd switching tube (M3) is electrically connected to the first bias voltage
(Vb1), the control end of the 4th switching tube (M4) electrically connects the negative input end (Vin-), the 8th switching tube (M8)
Control end is electrically connected at the node that the 4th switching tube (M4) and the 8th switching tube (M8) concatenation are formed；
5th switching tube (M5) and the 9th switching tube (M9) are sequentially connected in series in the 3rd switching tube (M3) and described
At the node that 4th switching tube (M4) concatenation is formed between the earth terminal (GND), the control of the 5th switching tube (M5)
The end electrical connection positive input terminal (Vin+), the control end of the 9th switching tube (M9) is electrically connected to the 5th switching tube
(M5) concatenated with the 9th switching tube (M9) at the node formed；
The transmission end of 6th switching tube (M6) is electrically connected the 5th switching tube (M5) and the 9th switching tube
(M9) node (Y) place formed and earth terminal (GND) are concatenated and its control end is electrically connected to the control of the 8th switching tube (M8)
End processed；The transmission end of 7th switching tube (M7) is electrically connected the 4th switching tube (M4) and the 8th switching tube
(M8) node (X) place formed and earth terminal (GND) are concatenated and its control end is electrically connected to the control of the 9th switching tube (M9)
End processed；
17th switching tube (M17), the 15th switching tube (M15), the 13rd switch (M13), the described tenth
One switch (M11) and the tenth switching tube (M10) be sequentially connected in series in the power end (VDD) and the earth terminal (GND) it
Between, the control end of the 17th switching tube (M17) is electrically connected to the second bias voltage (Vb2), the 15th switching tube
(M15) control end is electrically connected to the 3rd bias voltage (Vb3), and the control end of the 13rd switching tube (M13) is electrically connected to
4th bias voltage (Vb4), the control end of the 11st switching tube (M11) is electrically connected to the 4th switching tube (M4) and institute
Node (X) place that the 8th switching tube (M8) concatenation is formed is stated, the control end of the tenth switching tube (M10) is electrically connected to described common
The input of cmfb circuit (CMFB), the negative output terminal (Vout-) is electrically connected to the 15th switching tube (M15) and institute
State at the node that the 13rd switch (M13) concatenation is formed；
The eighteenmo closes pipe (M18), the sixteenmo and closes pipe (M16), the 14th switch (M14) and the described tenth
Two switching tubes (M12) are sequentially connected in series in the power end (VDD) and the 11st switching tube (M11) and the tenth switching tube
(M10) between the node that concatenation is formed, the control end that the eighteenmo closes pipe (M18) electrically connects second bias voltage
(Vb2), the sixteenmo closes control end electrical connection the 3rd bias voltage (Vb3) of pipe (M16), the 14th switch
The control end for managing (M14) electrically connects the 4th bias voltage (Vb4), and the 12nd switching tube (M12) is electrically connected to described
5th switching tube (M5) concatenates node (Y) place formed with the 9th switching tube (M9), and the positive output end (Vout+) is electrically connected
The sixteenmo is connected to close at the node that pipe (M16) and the 14th switch (M14) concatenation are formed.
6. circuit (10) according to claim 5, it is characterised in that the 3rd switching tube (M3), the 4th switch
Manage (M4), the 5th switching tube (M5), the 15th switching tube (M15), the sixteenmo and close pipe (M16), described the
It is PMOS that 17 switching tubes (M17) and the eighteenmo, which close pipe (M18), and the 6th switching tube (M6), the described 7th open
Close pipe (M7), the 8th switching tube (M8), the 9th switching tube (M9), the tenth switching tube (M10), the described 11st
Switching tube (M11), the 12nd switching tube (M12), the 13rd switching tube (M13), the 14th switching tube (M14)
For NMOS tube.
7. circuit (10) according to claim 1, it is characterised in that first level shifter (V1) includes：First
Switch (K1), second switch (K2), the 3rd switch (K3), the 4th switch (K4), the first electric capacity (C1), the 5th electric capacity (C5) and the
One dc source (Vbp1)；Wherein, the first switch (K1) and the second switch (K2) are sequentially connected in series straight in described first
Flow between power supply (Vbp1) and the negative output terminal (Vout-) of the Full differential operational amplifier (A1), the 3rd switch
(K3) and the 4th switch (K4) be sequentially connected in series in the power end (VDD) and the first switch pipe (M1) control end it
Between；One end of first electric capacity (C1) is electrically connected to the negative output terminal of the Full differential operational amplifier (A1)
(Vout-) and the other end is electrically connected to the control end of the first switch pipe (M1), one end of the 5th electric capacity (C5) is electrically connected
It is connected at the node that the first switch (K1) and the second switch (K2) concatenation are formed and the other end is electrically connected to described the
At the node that three switches (K3) and the 4th switch (K4) concatenation are formed.
8. circuit (10) according to claim 1, it is characterised in that the second electrical level shift unit (V2) includes：5th
Switch (K5), the 6th switch (K6), the 7th switch (K7), the 8th switch (K8), the second electric capacity (C2), the 6th electric capacity (C6) and the
Two dc sources (Vbn1)；Wherein, the 5th switch (K5) and the 6th switch (K6) are sequentially connected in series straight in described second
Flow between power supply (Vbn1) and the positive output end (Vout+) of the Full differential operational amplifier (A1), the 7th switch
(K7) and the 8th switch (K8) be sequentially connected in series in the earth terminal (GND) and the second switch pipe (M2) control end it
Between；One end of second electric capacity (C2) is electrically connected to the positive output end (Vout of the Full differential operational amplifier (A1)
+) and the other end is electrically connected to the control end of the second switch pipe (M2), one end of the 6th electric capacity (C6) is electrically connected to institute
State at the node that the 5th switch (K5) and the 6th switch (K6) concatenation are formed and the other end is electrically connected to the 7th switch
(K7) and at the node of the 8th switch (K8) the concatenation formation.
9. circuit (10) according to claim 1, it is characterised in that also include：19th switching tube (M19), the 20th
Switching tube (M20), the 7th resistance (R7) and the 8th resistance (R8)；19th switching tube (M19), the 7th resistance
(R7), the 8th resistance (R8) and the 20th switching tube (M20) are sequentially connected in series and connect in the power end (VDD) with described
Between ground terminal (GND), and the control end of the 19th switching tube (M19) is electrically connected to the control of the first switch pipe (M1)
End, the control end of the 20th switching tube (M20) is electrically connected to the control end of the second switch pipe (M2), the described 19th
The node output reference voltage high level (HV that switching tube (M19) and the 7th resistance (R7) concatenation are formedREF), the described 8th
The node output reference voltage low level (LV that resistance (R8) and the 20th switching tube (M20) concatenation are formedREF)。
10. a kind of Wireless Telecom Equipment, including analog-digital converter, it is characterised in that the analog-digital converter includes
Fully differential generating circuit from reference voltage (10) as described in any one of claim 1~9.
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| CN110224700A (en) * | 2019-05-05 | 2019-09-10 | 西安电子科技大学 | A kind of high speed complementation type dual power supply operational amplifier |
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