CN103840827A

CN103840827A - Assembly line ADC interstage gain calibration method

Info

Publication number: CN103840827A
Application number: CN201310701595.9A
Authority: CN
Inventors: 丁洋; 王宗民; 周亮; 冯文晓; 张春义
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2013-12-19
Filing date: 2013-12-19
Publication date: 2014-06-04
Anticipated expiration: 2033-12-19
Also published as: CN103840827B

Abstract

The invention provides a pipelined ADC inter-stage gain calibration method. After the chip is taped out, firstly, measure the actual gain of the pipeline stage to be calibrated according to the inter-stage gain measurement scheme; then, use the obtained actual gain value, combined with the compensation circuit structure, to determine the required compensation capacitance value; next, the The determined compensation capacitance value is converted into a corresponding calibration signal and solidified in the chip of the pipeline ADC; finally, in the normal conversion mode of the pipeline ADC, the compensation circuit compensates the inter-stage gain error of the calibration stage according to the calibration signal to complete the calibration. The method according to the invention does not affect the normal conversion process of the ADC, the circuit consumption is small, and high-precision calibration can be realized.

Description

A pipelined ADC inter-stage gain calibration method

技术领域 technical field

本发明涉及一种流水线模/数转换器(以下简称ADC)级间增益校准方法，主要用于对流水级级间增益放大器的增益误差进行校准，属于混合信号集成电路技术领域。 The invention relates to a method for calibrating inter-stage gain of a pipeline analog/digital converter (hereinafter referred to as ADC), which is mainly used for calibrating the gain error of an inter-stage gain amplifier of a pipeline, and belongs to the technical field of mixed-signal integrated circuits. the

背景技术 Background technique

现代通信系统需要高速高精度的ADC。ADC的高精度可以防止失真和丢失弱信号的现象，而高速ADC的应用则可以减少系统的变频次数。在各种结构的ADC中，流水线型ADC以其在精度、速度、功耗三者之间的优异折衷特性成为了高性能ADC的热门研究结构。 Modern communication systems require high-speed, high-precision ADCs. The high precision of the ADC can prevent distortion and loss of weak signals, and the application of high-speed ADC can reduce the frequency conversion times of the system. Among ADCs of various structures, the pipelined ADC has become a popular research structure for high-performance ADCs due to its excellent compromise characteristics among precision, speed, and power consumption. the

流水线ADC的转换精度受到电路中各类误差的限制。系统中主要的误差源包括：噪声、时钟抖动、电容失配、运算放大器有限增益、运算放大器建立误差、比较器失调电压、开关非线性、电荷注入及时钟溃通。其中，电容失配、运算放大器有限增益、运算放大器建立误差最终都会造成流水级的级间增益放大器增益出现误差，级间增益误差是限制流水线ADC转换精度的最主要因素。若不采用校准技术，转换器的精度将被限制在10比特以内。 The conversion accuracy of the pipeline ADC is limited by various errors in the circuit. The main error sources in the system include: noise, clock jitter, capacitor mismatch, op amp finite gain, op amp settling error, comparator offset voltage, switching nonlinearity, charge injection, and clock breakdown. Among them, the capacitance mismatch, the limited gain of the operational amplifier, and the establishment error of the operational amplifier will eventually cause errors in the gain of the inter-stage gain amplifier of the pipeline stage. The inter-stage gain error is the most important factor that limits the conversion accuracy of the pipeline ADC. Without calibration techniques, the accuracy of the converter would be limited to within 10 bits. the

尤其随着流水线ADC精度和速度的提高，前端流水级越来越倾向使用每级多比特结构，这样，级间增益放大器的增益随着每级分辨比特数的增加而提高，相应反馈系数也会提高，增大了放大器设计难度的同时也意味着放大器的增益误差会更大。因此，针对此误差的校准技术在高精度流水线ADC的设计中是必需的精度保证手段。 Especially with the improvement of the accuracy and speed of the pipeline ADC, the front-end pipeline stage is more and more inclined to use a multi-bit structure per stage. In this way, the gain of the inter-stage gain amplifier increases with the increase of the number of resolution bits per stage, and the corresponding feedback coefficient will also increase. Improvement increases the difficulty of amplifier design and also means that the gain error of the amplifier will be greater. Therefore, the calibration technique aimed at this error is a necessary means of ensuring accuracy in the design of high-precision pipeline ADCs. the

如图1所示为流水线ADC的系统框图。流水线ADC由采样保持电路和多个低精度的流水级组成。在每一个流水级中，子ADC对输入信号进行量化，得到数字输出码，同时子DAC（子数/模转换器）将子ADC的量化结果转化为模拟量，之后将此模拟量从输入中减掉，放大后作为残差信号从流水级输出给下一级进行处理。这里，子DAC功能、减法功能、放大功能由一个开关电容电路实现，称为MDAC电路，级间增益放大器作为MDAC电路的一部分实现放大功能。 As shown in Fig. 1, it is the system block diagram of pipeline ADC. A pipeline ADC consists of a sample-and-hold circuit and multiple low-precision pipeline stages. In each pipeline stage, the sub-ADC quantizes the input signal to obtain a digital output code, and at the same time, the sub-DAC (sub-D/A converter) converts the quantization result of the sub-ADC into an analog value, and then converts the analog value from the input After being subtracted and amplified, it is output as a residual signal from the pipeline stage to the next stage for processing. Here, the sub-DAC function, the subtraction function, and the amplification function are realized by a switched capacitor circuit, which is called an MDAC circuit, and the interstage gain amplifier is used as a part of the MDAC circuit to realize the amplification function. the

如图2所示为流水级的级间增益放大器电路示意图。放大器采用开关电容放大器结构，采样电容C_S和反馈电容C_F的比例决定了放大器的理想增益G，表达式如公式1所示。 Figure 2 is a schematic diagram of the inter-stage gain amplifier circuit of the pipeline stage. The amplifier adopts a switched capacitor amplifier structure. The ratio of the sampling capacitor C _S to the feedback capacitor C _F determines the ideal gain G of the amplifier. The expression is shown in Equation 1.

$G G = = \frac{{C C}_{S S}}{{C C}_{F f}} - - - - - - ((11))$

在上式基础上考虑有限运算放大器增益误差和电容失配误差。首先，假使运算放大器增益为A，则G表达式如公式2；在此基础上，假设C_F有误差ΔC，则增益G表达式如公式3。 Consider the finite operational amplifier gain error and capacitance mismatch error on the basis of the above formula. First, assuming that the operational amplifier gain is A, the expression of G is as in formula 2; on this basis, assuming that _CF has an error ΔC, the expression of gain G is as in formula 3.

$G G = = \frac{{C C}_{S S}}{{C C}_{F f}} \cdot &Center Dot; ((11 - - \frac{{C C}_{S S} + + {C C}_{F f}}{A A \cdot \cdot {C C}_{F f}})) - - - - - - ((22))$

$G G = = \frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC} \cdot \cdot ((11 - - \frac{{C C}_{S S} + + {C C}_{F f} + + ΔC ΔC}{A A \cdot \cdot (({C C}_{F f} + + ΔC ΔC))})) - - - - - - ((33))$

可以看到，在各误差的作用下，级间放大器的增益偏离了理想值，会严重限制ADC的转换精度。现有的级间增益校准技术，或者是在电路中需要额外的复制流水级来测试误差，大量增加了电路消耗；或者是后台校准，会影响ADC的正常转换，且限制ADC的转换速度。 It can be seen that under the action of various errors, the gain of the interstage amplifier deviates from the ideal value, which will seriously limit the conversion accuracy of the ADC. The existing inter-stage gain calibration technology either requires an additional replication pipeline stage in the circuit to test the error, which greatly increases the circuit consumption; or the background calibration will affect the normal conversion of the ADC and limit the conversion speed of the ADC. the

发明内容 Contents of the invention

本发明要解决的技术问题是提供一种流水线ADC级间增益校准方法，其针对流水线ADC级间增益误差，实现了利用低电路消耗实现高精度校准的目的，不仅提高了流水线ADC的线性度及其动态范围，而且不影响ADC的正常数据转换过程。 The technical problem to be solved by the present invention is to provide a pipelined ADC inter-stage gain calibration method, which aims at the pipelined ADC inter-stage gain error, realizes the purpose of realizing high-precision calibration with low circuit consumption, and not only improves the linearity and Its dynamic range does not affect the normal data conversion process of the ADC. the

本发明解决上述技术问题的技术方案包括： The technical scheme that the present invention solves the problems of the technologies described above comprises:

一种流水线ADC级间增益校准方法，包括以下步骤： A pipelined ADC interstage gain calibration method, comprising the following steps:

（1）初始化流水线ADC的输入信号Vin，使待校准增益的第i级流水级的输入信号Vin_i处于该流水级转换区间的除最高转换区间外的任意位置； (1) Initialize the input signal Vin of the pipeline ADC, so that the input signal Vin_i of the i-th pipeline stage of the gain to be calibrated is in any position of the pipeline stage conversion interval except the highest conversion interval;

（2）以斜坡信号形式，缓慢增加流水线ADC的输入信号Vin，监测第i级流水级的最低位数字输出D_i_0，当D_i_0第一次发生跳变时，记录下此时流水线ADC的输入V_{in_x1}和输出D_{out_y1}； (2) In the form of a ramp signal, slowly increase the input signal Vin of the pipeline ADC, monitor the lowest digital output D_i_0 of the i-th pipeline level, and record the input V _{in_x1} of the pipeline ADC at this time when D_i_0 jumps for the first time and output D _{out_y1} ;

（3）继续缓慢增加流水线ADC的输入信号Vin，当第i级流水级的最低位数字输出D_i_0发生与步骤（2）反相的跳变时，记录下此时流水线ADC的输入V_{in_x2}和输出D_{out_y2}； (3) Continue to slowly increase the input signal Vin of the pipeline ADC. When the lowest digital output D_i_0 of the i-th pipeline level jumps in the opposite phase to that of step (2), record the input V _{in_x2} and output of the pipeline ADC at this time. D _{out_y2} ;

（4）根据步骤（2）和（3）中得到的流水线ADC的输入V_{in_x1}、V_{in_x2}和输出D_{out_y1}、D_{out_y2}，并利用下面的公式确定待校准增益的第i级流水级的实际增益Gr_i， (4) According to the input V _{in_x1} , V _{in_x2} and output D _{out_y1} , D _{out_y2} of the pipeline ADC obtained in steps (2) and (3), and use the following formula to determine the actual gain of the i-th pipeline stage whose gain is to be calibrated Gr_i,

$Gr_i = \frac{(D_{out_y 2} - D_{out_y 1}) \cdot V_{FS}}{(2^{N} - 1) \cdot (V_{in_x 2} - V_{in_x 1})}, i = 1,$ 或 $Gr_i = \frac{({D.}_{out_the y 2} - {D.}_{out_the y 1}) \cdot V_{FS}}{(2^{N} - 1) &Center Dot; (V_{in_x 2} - V_{in_x 1})}, i = 1,$ or

$Gr Gr__i i = = \frac{(({D D.}_{out out__y the y 22} - - {D D.}_{out out__y the y 11})) \cdot &Center Dot; {V V}_{FS FS}}{((22^{N N} - - 11)) \cdot &Center Dot; (({V V}_{in in__x x 22} - - {V V}_{in in__x x 11})) \cdot &Center Dot; {Π Π}_{j j = = 11}^{i i - - 11} G G__j j},, i i = = 22,, \cdot &Center Dot; \cdot &Center Dot; \cdot &Center Dot;,, n no$

其中，V_FS为流水线ADC的满量程输入范围，N为流水线ADC的分辨率，

为第i级流水级的理想增益值，Gr_i为第i级流水级的实际增益，n为流水线ADC采用的流水级级数； Among them, V _FS is the full-scale input range of the pipeline ADC, N is the resolution of the pipeline ADC,

is the ideal gain value of the i-th pipeline stage, Gr_i is the actual gain of the i-th pipeline stage, and n is the number of pipeline stages used by the pipeline ADC;

(5)在待校准增益的第i级流水级的级间增益放大器电路中连接第一和第二补偿电路，所述第i级流水级的级间增益放大器电路包括一运算放大器，所述第一和第二补偿电路相对于所述运算放大器对称地布置在所述运算放大器的正输入端侧和负输入端侧；所述第一补偿电路包括第一可调电容和第一选择器，第二补偿电路包括第二可调电容和第二选择器，其中，所述第一可调电容和第二可调电容具有相同的电容值C_{b_i}，所述第一选择器和第二选择器为同样的二选一选择器，并且其中， (5) Connect the first and second compensation circuits in the inter-stage gain amplifier circuit of the i-th pipeline stage of the gain to be calibrated, the inter-stage gain amplifier circuit of the i-level pipeline stage includes an operational amplifier, and the first The first and second compensation circuits are symmetrically arranged on the positive input side and the negative input side of the operational amplifier with respect to the operational amplifier; the first compensation circuit includes a first adjustable capacitor and a first selector, the second The second compensation circuit includes a second adjustable capacitor and a second selector, wherein the first adjustable capacitor and the second adjustable capacitor have the same capacitance C _{b_i} , and the first selector and the second selector are The same alternative selector, and where,

所述第一可调电容的远离所述第一选择器的第一端与运算放大器的正输入端连接，其靠近所述第一选择器的第二端与所述第一选择器的输出端连接；所述第一选择器的第一输入端连接流水级的正输出端,第二输入端连接流水级的负输出端，选择端连接校准信号，当所述校准信号为高电平时，所述第一选择器的输出端输出所述第一选择器的第二输入端的信号，而当所述校准信号为低电平时，所述第一选择器的输出端输出所述第一选择器的第一输入端的信号； The first end of the first adjustable capacitor far away from the first selector is connected to the positive input end of the operational amplifier, and the second end close to the first selector is connected to the output end of the first selector connection; the first input end of the first selector is connected to the positive output end of the pipeline stage, the second input end is connected to the negative output end of the pipeline stage, and the selection end is connected to the calibration signal. When the calibration signal is high, the The output terminal of the first selector outputs the signal of the second input terminal of the first selector, and when the calibration signal is low level, the output terminal of the first selector outputs the signal of the first selector the signal at the first input;

所述第二可调电容的远离所述第二选择器的第一端与运算放大器的负输入端连接，其靠近所述第二选择器的第二端与所述第二选择器的输出端连接；所述第二选择器的第一输入端连接流水级的负输出端，第二输入端连接流水级的正输出端，选择端连接所述校准信号，当所述校准信号为高电平时，所述第二选择器的输出端输出所述第二选择器的第二输入端的信号，而当所述校准信号为低电平时，所述第二选择器的输出端输出所述第二选择器的第一输入端的信号； The first end of the second adjustable capacitor far away from the second selector is connected to the negative input end of the operational amplifier, and the second end close to the second selector is connected to the output end of the second selector connection; the first input end of the second selector is connected to the negative output end of the pipeline stage, the second input end is connected to the positive output end of the pipeline stage, and the selection end is connected to the calibration signal, when the calibration signal is high , the output terminal of the second selector outputs the signal of the second input terminal of the second selector, and when the calibration signal is low level, the output terminal of the second selector outputs the second selection The signal at the first input terminal of the device;

所述第一可调电容和第二可调电容具有相同的电路结构，即，包括并联连接的相同数量的补偿分支电路，每个补偿分支电路包括一分支电容和一分支选择器，各个补偿分支电路中的分支选择器为相同的二选一选择器，而依次并联连接的各个补偿分支电路中的分支电容的值满足：对相邻的两个补偿分支电路中的两个分支电容，顺序在后的分支电容的值是前面分支电容的值的两倍；在每个补偿分支电路中，分支电容的靠近分支选择器的第二端连接至分支选择器的输出端，分支选择器的第一输入端接地,其选择端连接控制该分支选择器所在补偿分支电路的分支校准信号，并且所述第一可调电容和第二可调电容的相对应的补偿分支电路中的分支选择器的选择端连接相同的分支校准信号，当分支校准信号为高电平时，分支选择器的输出端输出其第二输入端的信号，而当分支校准信号为低电平时，分支选择器的输出端输出其第一输入端的信号； The first adjustable capacitor and the second adjustable capacitor have the same circuit structure, that is, include the same number of compensation branch circuits connected in parallel, each compensation branch circuit includes a branch capacitor and a branch selector, each compensation branch The branch selector in the circuit is the same one-two selector, and the value of the branch capacitance in each compensation branch circuit connected in parallel in turn satisfies: For the two branch capacitances in two adjacent compensation branch circuits, the order is The value of the last branch capacitor is twice the value of the previous branch capacitor; in each compensation branch circuit, the second terminal of the branch capacitor close to the branch selector is connected to the output terminal of the branch selector, and the first terminal of the branch selector The input terminal is grounded, and its selection terminal is connected to control the branch calibration signal of the compensation branch circuit where the branch selector is located, and the selection of the branch selector in the corresponding compensation branch circuit of the first adjustable capacitor and the second adjustable capacitor The terminal is connected to the same branch calibration signal. When the branch calibration signal is high level, the output terminal of the branch selector outputs the signal of its second input terminal, and when the branch calibration signal is low level, the output terminal of the branch selector outputs the signal of its second input terminal. an input signal;

在所述第一可调电容的每个补偿分支电路中，分支电容的远离分支选择器的第一端并联连接在一起作为所述第一可调电容的第一端，其分支选择器的第二输入端并联连接在一起作为所述第一可调电容的第二端；并且 In each compensation branch circuit of the first adjustable capacitor, the first ends of the branch capacitors far away from the branch selector are connected together in parallel as the first end of the first adjustable capacitor, and the first ends of the branch selector The two input ends are connected in parallel together as the second end of the first adjustable capacitor; and

在所述第二可调电容的每个补偿分支电路中，分支电容的远离分支选择器的第一端并联连接在一起作为所述第二可调电容的第一端，其分支选择器的第二输入端并联连接在一起作为所述第二可调电容的第二端； In each compensation branch circuit of the second adjustable capacitor, the first ends of the branch capacitors far away from the branch selector are connected together in parallel as the first end of the second adjustable capacitor, and the first ends of the branch selector The two input ends are connected together in parallel as the second end of the second adjustable capacitor;

（6）根据步骤（4）中确定的待校准增益流水级的实际增益Gr_i与理想增益G_i，结合步骤（5）中连接有第一和第二补偿电路的第i级流水级的级间增益放大器电路，得到以下公式，利用该公式确定补偿所需的补偿电容值C_{b_i}， (6) According to the actual gain Gr_i and the ideal gain G_i of the to-be-calibrated gain pipeline stage determined in step (4), combined with the inter-stage gain of the i-th pipeline stage connected to the first and second compensation circuits in step (5) Amplifier circuit, get the following formula, use this formula to determine the compensation capacitor value C _{b_i} required for compensation,

${((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i} = = {C C}_{S S} \cdot &Center Dot; ((\frac{11}{G G__i i} - - \frac{11}{Gr Gr__i i}))$

式中，C_{b_i}为第i级流水级需要的补偿电容值，C_S为采样电容值，C_F为反馈电容值，F₀为连接至所述第一和第二选择器的校准信号，F₀的值为0或1； In the formula, C _{b_i} is the compensation capacitance value required by the i-th pipeline stage, C _S is the sampling capacitance value, C _F is the feedback capacitance value, F ₀ is the calibration signal connected to the first and second selectors, F The value of ₀ is 0 or 1;

（7）根据步骤（6）中确定的第i级流水级需要的补偿电容值C_{b_i}，并结合下面的公式，确定分支校准信号F₁-F_m的值，并将这些分支校准信号F₁-F_m的值以及前述的校准信号F₀的值存储在流水线ADC的芯片中； (7) According to the compensation capacitor value C _{b_i} required by the i-th pipeline stage determined in step (6), and combined with the following formula, determine the value of the branch calibration signal F ₁ -F _m , and convert these branch calibration signals F ₁ The value of -F _m and the value of the aforementioned calibration signal F ₀ are stored in the chip of the pipeline ADC;

${C C}_{b b__i i} = = {F f}_{11} \cdot &Center Dot; {C C}_{00} + + {F f}_{22} \cdot &Center Dot; 22 \cdot &Center Dot; {C C}_{00} + + . . . . . . + + {F f}_{m m} \cdot &Center Dot; 22^{m m - - 11} \cdot &Center Dot; {C C}_{00} = = {Σ Σ}_{k k = = 11}^{m m} {F f}_{k k} \cdot &Center Dot; 22^{k k - - 11} \cdot &Center Dot; {C C}_{00}$

式中，m为第一和第二可调电容中并联的补偿分支电路的数量；C₀为并联的补偿分支电路中的分支电容的单位电容值，即，第一个补偿分支电路中的分支电容的值为C₀，第二个补偿分支电路中的分支电容的值为2C₀，第三个补偿分支电路中的分支电容的值为4C₀，以此类推；F₁.....F_m分别表示连接至第一至第m个补偿分支电路中的分支选择器的选择端的分支校准信号；以及 In the formula, m is the number of parallel compensation branch circuits in the first and second adjustable capacitors; C ₀ is the unit capacitance value of the branch capacitors in the parallel compensation branch circuits, that is, the branch in the first compensation branch circuit The value of the capacitor is C ₀ , the value of the branch capacitance in the second compensation branch circuit is 2C ₀ , the value of the branch capacitance in the third compensation branch circuit is 4C ₀ , and so on; F ₁ ..... F _m respectively represent the branch calibration signals connected to the selection terminals of the branch selectors in the first to m compensation branch circuits; and

（8）在流水线ADC正常工作时，根据步骤（7）中确定的分支校准信号F₁-F_m以及校准信号F₀的值对待校准的第i级流水级的级间增益误差进行补偿。 (8) When the pipeline ADC is working normally, the inter-stage gain error of the i-th pipeline stage to be calibrated is compensated according to the values of the branch calibration signals F ₁ -F _m and the calibration signal F ₀ determined in step (7).

优选地，在执行步骤（5）之前，重复执行步骤（2）-（4）M次，并对每次计算得到的流水级实际增益值求平均值，并根据该平均值执行后面的步骤（6）-（8）。 Preferably, before performing step (5), repeat steps (2)-(4) M times, and calculate the average value of the actual gain value of the pipeline stage obtained by each calculation, and perform the following steps according to the average value ( 6)-(8). the

与现有技术相比，根据本发明的流水线ADC级间增益校准方法具备有益的技术效果： Compared with the prior art, the pipeline ADC interstage gain calibration method according to the present invention has beneficial technical effects:

1、作为厂家校准的一种，它不会影响ADC的正常转换过程； 1. As a kind of factory calibration, it will not affect the normal conversion process of ADC;

2、仅需将ADC内部流水级电路的最低位数字输出信号引出到芯片管脚，即可对该流水级的级间增益放大器进行测量，电路消耗很小； 2. It is only necessary to lead out the lowest digital output signal of the internal pipeline circuit of the ADC to the chip pins to measure the inter-stage gain amplifier of the pipeline level, and the circuit consumption is very small;

3、补偿电路中的可变电容由多个分支电容阵列组成，增加分支电容的个数，并减小单位分支电容的大小即可实现小步长的补偿，有效提高了补偿精度。 3. The variable capacitor in the compensation circuit is composed of multiple branch capacitor arrays. Increasing the number of branch capacitors and reducing the size of the unit branch capacitor can realize small-step compensation, which effectively improves the compensation accuracy. the

附图说明 Description of drawings

图1是根据本发明的流水线ADC的系统框图； Fig. 1 is the system block diagram of pipeline ADC according to the present invention;

图2（a）和图2（b）是根据本发明的流水级放大器的结构示意图； Fig. 2 (a) and Fig. 2 (b) are the structural representations according to the pipeline level amplifier of the present invention;

图3（a）和图3（b）是根据的本发明的流水线ADC的流水级传递曲线图； Fig. 3 (a) and Fig. 3 (b) are the pipeline level transfer curve diagrams of the pipeline ADC according to the present invention;

图4是根据本发明的连接第一和第二补偿电路之后的待校准增益流水级的级间增益放大器电路补偿原理示意图；以及 Fig. 4 is the interstage gain amplifier circuit compensation schematic diagram of the gain pipeline stage to be calibrated after connecting the first and second compensation circuits according to the present invention; and

图5（a）和图5（b）是根据本发明的第一和第二补偿电路的电路连接示意图。 Fig. 5(a) and Fig. 5(b) are schematic circuit connection diagrams of the first and second compensation circuits according to the present invention. the

具体实施方式 Detailed ways

下面将结合附图和具体实施例对根据本发明的流水线ADC级间增益校准方法做进一步详细的说明。 The method for calibrating the inter-stage gain of the pipeline ADC according to the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. the

为了使本发明的目的、技术方案和优点更加清楚明白，以下结合实例和附图对本发明做进一步的详细说明。在此本发明的示意性实施例及说明用于解释和说明，但不作为本发明的限定。 In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with examples and accompanying drawings. The illustrative embodiments and descriptions of the invention are presented herein for illustration and description, but not as limitations of the invention. the

本发明的流水线ADC级间增益校准方法中，在芯片流片后，首先，根据级间增益测量方案对待校准流水级的实际增益进行测量；其后，利用得到的实际增益值，结合补偿电路结构，确定需要的补偿电容值；接下来，将确定的补偿电容值转换为相应的校准信号固化在流水线ADC的芯片中；最后，在流水线ADC的正常转换模式下，补偿电路根据校准信号对待校准级的级间增益误差进行补偿，完成校准。 In the pipeline ADC inter-stage gain calibration method of the present invention, after the chip is taped out, firstly, the actual gain of the pipeline stage to be calibrated is measured according to the inter-stage gain measurement scheme; thereafter, the actual gain value obtained is combined with the compensation circuit structure , determine the required compensation capacitance value; next, convert the determined compensation capacitance value into a corresponding calibration signal and solidify it in the chip of the pipeline ADC; finally, in the normal conversion mode of the pipeline ADC, the compensation circuit treats the calibration level according to the calibration signal The inter-stage gain error is compensated to complete the calibration. the

如图3（a）和图3（b）所示是一个3比特的流水级转换特性图，我们将以此流水级（假设该流水级为第i级）为例对根据本发明的流水线ADC级间增益校准方法进行阐述。 As shown in Figure 3(a) and Figure 3(b), it is a 3-bit pipeline level conversion characteristic diagram. We will take this pipeline level (assuming that the pipeline level is the i-th level) as an example for the pipeline ADC according to the present invention The inter-stage gain calibration method is described. the

当流水级的模拟输入信号位于不同的转换区间时，流水级相应的数字输出也如图中标注所示。可以看到，相邻的转换区间输出数字码的最低位D_i_0交替为0或1，本发明的校准方法即利用此特性进行增益的测量。在电路设计中，将待校准流水级的最低位数字输出D_i_0连至芯片输出端口，在测试模式下，从外部对此信号进行检测。 When the analog input signals of the pipeline level are in different conversion intervals, the corresponding digital output of the pipeline level is also marked as shown in the figure. It can be seen that the lowest bit D_i_0 of the output digital code in adjacent conversion intervals is alternately 0 or 1, and the calibration method of the present invention utilizes this characteristic to measure the gain. In the circuit design, the lowest digital output D_i_0 of the pipeline level to be calibrated is connected to the chip output port, and this signal is detected from the outside in the test mode. the

首先，初始化流水线ADC的输入信号Vin，使待校准增益的第i级流水级的输入信号Vin_i处于该流水级转换区间的除最高转换区间外的任意位置，如S点。 First, initialize the input signal Vin of the pipeline ADC, so that the input signal Vin_i of the i-th pipeline stage whose gain is to be calibrated is at any position in the conversion interval of the pipeline stage except the highest conversion interval, such as point S. the

之后，以斜坡信号（Ramp）形式，缓慢增加流水线ADC的输入信号Vin，监测待校准的第i级流水级的最低位数字输出D_i_0，当D_i_0第一次发生跳变时（可以是从0跳变到1，或者是从1跳变到0），即为A点，记录下此时流水线ADC的输入V_{in_x1}和输出D_{out_y1}。 Afterwards, slowly increase the input signal Vin of the pipeline ADC in the form of a ramp signal (Ramp), monitor the lowest digital output D_i_0 of the i-th pipeline stage to be calibrated, and when D_i_0 jumps for the first time (it can be a jump from 0 Change to 1, or jump from 1 to 0), which is point A, record the input V _{in_x1} and output D _{out_y1} of the pipeline ADC at this time.

接下来，继续缓慢增加流水线ADC的输入信号Vin，当D_i_0发生与步骤（2）反相的跳变时（从1跳变到0，或者从0跳变到1），记录下此时流水线ADC的输入V_{in_x2}和输出D_{out_y2}。 Next, continue to slowly increase the input signal Vin of the pipeline ADC. When D_i_0 undergoes a jump in the opposite phase to step (2) (from 1 to 0, or from 0 to 1), record the pipeline ADC at this time. input V _{in_x2} and output D _{out_y2} .

之后，根据前面记录的流水线ADC的输入V_{in_x1}、V_{in_x2}和输出D_{out_y1}、D_{out_y2}，由下面的公式4计算确定待校准增益的第i级流水级的实际增益Gr_i。 Afterwards, according to the input V _{in_x1} , V _{in_x2} and output D _{out_y1} , D _{out_y2} of the pipeline ADC recorded earlier, the actual gain Gr_i of the i-th pipeline stage to determine the gain to be calibrated is calculated by the following formula 4.

$Gr Gr__i i = = \frac{(({D D.}_{out out__y the y 22} - - {D D.}_{out out__y the y 11})) \cdot &Center Dot; {V V}_{FS FS}}{((22^{N N} - - 11)) \cdot &Center Dot; (({V V}_{in in__x x 22} - - {V V}_{in in__x x 11}))},, i i = = 11$

$Gr Gr__i i = = \frac{(({D D.}_{out out__y the y 22} - - {D D.}_{out out__y the y 11})) \cdot &Center Dot; {V V}_{FS FS}}{((22^{N N} - - 11)) \cdot &Center Dot; (({V V}_{in in__x x 22} - - {V V}_{in in__x x 11})) \cdot &Center Dot; {Π Π}_{j j = = 11}^{i i - - 11} G G__j j},, i i = = 22,, \cdot \cdot \cdot \cdot \cdot \cdot,, n no - - - - - - ((44))$

为第一级到第i级流水级的理想增益值的乘积，Gr_i是第i级流水级的实际增益，n为流水线ADC采用的流水级级数。 Among them, V _FS is the full-scale input range of the pipeline ADC, N is the resolution of the pipeline ADC,

is the product of the ideal gain values from the first stage to the i-th pipeline stage, Gr_i is the actual gain of the i-th pipeline stage, and n is the number of pipeline stages used by the pipeline ADC.

为避免偶发性误差干扰最终的测量精度，可以继续缓慢增大流水线ADC的输入信号Vin，并重复步骤（2）、（3）、（4），计算出每段转换区间的斜率，求平均得到更精确的流水级实际增益Gr_i。每重复一次步骤（2）、（3）、（4）得到一个流水级增益值Gr_i_j（其中，j表示重复步骤（2）-（4）的次数），经过M次循环后，第i级流水级的实际增益平均值由公式

得到。 In order to avoid occasional errors from interfering with the final measurement accuracy, you can continue to slowly increase the input signal Vin of the pipeline ADC, and repeat steps (2), (3), and (4) to calculate the slope of each conversion interval, and calculate the average to obtain More accurate pipeline stage actual gain Gr_i. Steps (2), (3), and (4) are repeated each time to obtain a pipeline level gain value Gr_i_j (where j represents the number of times to repeat steps (2)-(4), after M cycles, the i-th pipeline The actual gain average of the stage is given by the formula

get.

结合上面的公式（3），可以得到第i级流水级的实际增益如下面的公式（5）。测量得到Gr_i后，此等式包含ΔC和A两个变量。 Combining the above formula (3), the actual gain of the i-th pipeline stage can be obtained as the following formula (5). After measuring Gr_i, this equation contains two variables, ΔC and A. the

$\frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC} \cdot &Center Dot; ((11 - - \frac{{C C}_{S S} + + {C C}_{F f} + + ΔC ΔC}{A A \cdot \cdot (({C C}_{F f} + + ΔC ΔC))})) = = Gr Gr__i i - - - - - - ((55))$

接下来计算连入补偿电路后的流水级增益值。 Next, calculate the pipeline stage gain value connected to the compensation circuit. the

如图4所示是增益误差补偿原理示意图。补偿电路由可调电容C_b-i和相应的控制电路组成，它与流水级结合实现补偿功能。由于流水级采用全差分运算放大器，因此，需要两个补偿电路，即第一补偿电路和第二补偿电路。两个补偿电路相同，都包括一个可调电容（分别称为第一可调电容和第二可调电容）和一个二选一选择器（分别成为第一选择器和第二选择器）作为控制电路。两个补偿电路相对于流水级的运算放大器对称地布置。其中，在第一补偿电路中，第一可调电容的远离第一选择器的第一端与运算放大器的正输入端OP+连接，其靠近第一选择器的第二端与第一选择器M1的输出端连接。第一选择器M1的第一输入端IN1连接流水级的正输出端V_out+，第二输入端IN2连接流水级的负输出端V_out-，其选择端S连接外部的校准信号F₀。当外部的校准信号为高电平“1”时，第一选择器M1的输出端输出第一选择器的第二输入端的信号，而当校准信号为低电平“0”时，第一选择器的输出端输出第一选择器的第一输入端的信号。 Figure 4 is a schematic diagram of the principle of gain error compensation. Compensation circuit is made up of adjustable electric capacity _Cbi and corresponding control circuit, it realizes compensation function in combination with flow stage. Since the pipeline stage adopts a fully differential operational amplifier, two compensation circuits are required, that is, a first compensation circuit and a second compensation circuit. The two compensation circuits are the same, including an adjustable capacitor (referred to as the first adjustable capacitor and the second adjustable capacitor) and a two-to-one selector (respectively called the first selector and the second selector) as control circuit. The two compensation circuits are arranged symmetrically with respect to the operational amplifiers of the pipeline stage. Wherein, in the first compensation circuit, the first end of the first adjustable capacitor far away from the first selector is connected to the positive input end OP+ of the operational amplifier, and the second end close to the first selector is connected to the first selector M1 output connection. The first input terminal IN1 of the first selector M1 is connected to the positive output terminal V _out+ of the pipeline stage, the second input terminal IN2 is connected to the negative output terminal V _{out- of} the pipeline stage, and the selection terminal S of the first selector M1 is connected to the external calibration signal F ₀ . When the external calibration signal is high level "1", the output terminal of the first selector M1 outputs the signal of the second input terminal of the first selector, and when the calibration signal is low level "0", the first selection The output terminal of the selector outputs the signal of the first input terminal of the first selector.

在第二补偿电路中，第二可调电容的远离第二选择器M2的第一端与运算放大器的负输入端OP-连接，其靠近第二选择器M2的第二端与第二选择器M2的输出端连接。第二选择器M2的第一输入端IN1连接流水级的负输出端V_out-，第二输入端IN2连接流水级的正输出端V_out+，选择端S连接所述外部的校准信号F₀。当校准信号为高电平时，第二选择器的输出端输出第二选择器的第二输入端的信号，而当校准信号为低电平时，第二选择器的输出端输出第二选择器的第一输入端的信号。 In the second compensation circuit, the first terminal of the second adjustable capacitor far away from the second selector M2 is connected to the negative input terminal OP- of the operational amplifier, and the second terminal close to the second selector M2 is connected to the second selector M2 The output terminal of M2 is connected. The first input terminal IN1 of the second selector M2 is connected to the negative output terminal V _{out- of} the pipeline stage, the second input terminal IN2 is connected to the positive output terminal V _out+ of the pipeline stage, and the selection terminal S is connected to the external calibration signal F ₀ . When the calibration signal is high level, the output terminal of the second selector outputs the signal of the second input terminal of the second selector, and when the calibration signal is low level, the output terminal of the second selector outputs the signal of the second input terminal of the second selector A signal at the input.

上述的第一选择器M1和第二选择器M2的选择端S均连接校准信号F₀。 The selection terminals S of the first selector M1 and the second selector M2 are both connected to the calibration signal F ₀ .

当流水级处于采样相位时（如图2(a)所示），运算放大器的差分输入与差分输出端如图2（a）所示均处于短接状态，两输入端电压相同且为常数，两输出端电压也相同且为常数，因此，两条差分通路上反馈电容C_F和补偿电容C_{b_i}两极板所接电平值相同，不影响采样电容C_S采样差分输入。 When the pipeline stage is in the sampling phase (as shown in Figure 2(a)), the differential input and differential output terminals of the operational amplifier are both in a short-circuit state as shown in Figure 2(a), and the voltages of the two input terminals are the same and constant. The voltages at the two output terminals are also the same and constant. Therefore, the level values connected to the two polar plates of the feedback capacitor C _F and the compensation capacitor C _{b_i} on the two differential paths are the same, which does not affect the sampling capacitor C _S to sample the differential input.

在流水级处于放大相位时（如图2(b)所示），根据电荷守恒定律得到补偿后第i级流水级的增益Gc_i如下面的公式6。其中，C_S为采样电容，C_F为反馈电容，ΔC是C_F的失配误差，F₀为校准信号（数字信号），C_b-i为补偿电容值。 When the pipeline stage is in the amplification phase (as shown in Figure 2(b)), the gain Gc_i of the i-th pipeline stage after being compensated according to the law of charge conservation is shown in the following formula 6. Among them, C _S is the sampling capacitor, C _F is the feedback capacitor, ΔC is the mismatch error of C _F , F ₀ is the calibration signal (digital signal), and C _bi is the compensation capacitor value.

$Gc Gc__i i = = \frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i}} \cdot &Center Dot; ((11 - - \frac{{C C}_{S S} + + {C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i}}{A A \cdot &Center Dot; (({C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i}))})) - - - - - - ((66))$

可以看到，由于运算放大器增益A与电容值相比非常大，

近似为1，因此，C_b-i主要是通过直接对C_F进行补偿来实现对增益的校准。 It can be seen that since the operational amplifier gain A is very large compared to the capacitor value,

Approximate to 1, therefore, C _bi mainly realizes the calibration of the gain by directly compensating _CF.

我们的校准目标是，令补偿后的第i级流水级的增益Gc_i等于流水级的理想增益G_i，如下面的公式，这样就完成了校准。 Our calibration goal is to make the gain Gc_i of the i-th pipeline stage after compensation equal to the ideal gain G_i of the pipeline stage, as shown in the following formula, thus completing the calibration. the

$\frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i}} \cdot &Center Dot; ((11 - - \frac{{C C}_{S S} + + {C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot &Center Dot; {C C}_{b b__i i}}{A A \cdot &Center Dot; (({C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} \cdot \cdot {C C}_{b b__i i}))})) = = C C__i i - - - - - - ((77))$

结合公式5，可以得到两个关于ΔC、A和C_b的等式。根据两个等式计算得到补偿电容C_b-i的值，就可以对第i级流水级的增益误差进行补偿了。 Combined with Equation 5, two equations about ΔC, A and C _b can be obtained. The value of the compensation capacitor C _bi is calculated according to the two equations, and then the gain error of the i-th pipeline stage can be compensated.

下面介绍如何根据这两个等式得到应该补偿的C_b-i的值。由于等式只有两个，而未知量有三个，因此，无法通过计算直接得到应补偿电容C_b-i值的解析解。鉴于运算放大器的增益A非常大，公式5中的和公式7中的

近似为1，忽略该项可去掉一个变量A，这样，变量只有两个，可以计算出最终需补偿的C_b-i值。 The following describes how to obtain the value of C _bi that should be compensated according to these two equations. Since there are only two equations and three unknown quantities, the analytical solution of the value of the capacitor C _bi to be compensated cannot be directly obtained through calculation. Given that the gain A of the op amp is very large, the and in Equation 7

Approximate to 1, ignoring this item can remove a variable A, so that there are only two variables, and the final value of C _bi to be compensated can be calculated.

首先，忽略公式5和公式7括号中的误差项

与

得到下面的公式8和公式9，计算得到补偿电容C_b-i，校准信号F₀决定了补偿电容C_b-i的补偿方向，当

时，校准信号F₀应为低电平“0”，当时，校准信号F₀应为高电平“1”。 First, ignore the error term in brackets in Equation 5 and Equation 7

and

The following formula 8 and formula 9 are obtained, and the compensation capacitor C _bi is calculated. The calibration signal F ₀ determines the compensation direction of the compensation capacitor C _bi . When

When, the calibration signal F ₀ should be low level "0", when , the calibration signal F ₀ should be high level "1".

$Gr Gr__i i = = \frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC} - - - - - - ((88))$

$G G__i i = = \frac{{C C}_{S S}}{{C C}_{F f} + + ΔC ΔC + + {((- - 11))}^{{F f}_{00}} {C C}_{b b}} - - - - - - ((99))$

${((- - 11))}^{{F f}_{00}} \cdot \cdot {C C}_{b b__i i} = = {C C}_{S S} \cdot &Center Dot; ((\frac{11}{G G__i i} - - \frac{11}{Gr Gr__i i})) - - - - - - ((1010))$

如图5（a）和图5（b）所示是第一和第二可调电容的电路连接图，图5（a）和图5（b）分别是与运算放大器的两个差分输入端连接的第一和第二可调电容的电路连接图。 Figure 5(a) and Figure 5(b) are the circuit connection diagrams of the first and second adjustable capacitors, and Figure 5(a) and Figure 5(b) are the two differential input terminals of the operational amplifier respectively The circuit connection diagram of the first and second adjustable capacitors connected. the

如图5（a）所示是与运算放大器的正输入端OP+连接的第一可调电容的电路连接图。第一可调电容包括m个并联连接的补偿分支电路，每个补偿分支电路包括一分支电容和一分支选择器，各个分支电路中的分支电容的电容值分别是C₀、2C₀、4C₀、...、2^m-1C₀，呈2进制权重分布，其中C₀为并联的补偿分支电路中的分支电容的单位电容值。各个分支电路中所有分支电容的远离选择器的第一端连接在一起，作为第一可调电容的第一端，与运算放大器的正输入端OP+连接；而其靠近分支选择器的第二端则各自与其所在分支电路的选择器的输出端连接。即，如图5（a）所示，第一个分支电容C₀的一个极板与运算放大器的正输入端OP+连接，另一个极板与其所在分支电路上的分支选择器MUX(1)的输出端连接，第二个分支电容2C₀的一个极板与运算放大器的正输入端OP+连接，另一个极板与其所在分支电路上的分支选择器MUX(2)的输出端连接，依此类推。在每个补偿分支电路中，分支选择器MUX(1)、MUX(2)、MUX(m)的第一输入端IN1相连并接地，第二输入端IN2也连接在一起作为第一可调电容的第二端与第一选择器M1的输出端连接。而第一选择器M1的两个输入端IN1和IN2分别与第i级流水级的两个输出端V_out+、V_out-连接。这里，各个分支选择器MUX(1)、MUX(2)、…、MUX(m)的选择端S分别由分支校准信号F₁、F₂、…、F_m控制，而第一选择器M1的选择端由校准信号F₀控制。当分支校准信号为高电平时，分支选择器的输出端输出其第二输入端的信号，而当分支校准信号为低电平时，分支选择器的输出端输出其第一输入端的信号。 FIG. 5( a ) is a circuit connection diagram of the first adjustable capacitor connected to the positive input terminal OP+ of the operational amplifier. The first adjustable capacitor includes m compensation branch circuits connected in parallel, each compensation branch circuit includes a branch capacitor and a branch selector, and the capacitance values of the branch capacitors in each branch circuit are C ₀ , 2C ₀ , 4C ₀ , . . . , 2 ^m-1 C ₀ , in binary weight distribution, where C ₀ is the unit capacitance value of the branch capacitance in the parallel compensation branch circuit. The first ends of all branch capacitors in each branch circuit away from the selector are connected together as the first end of the first adjustable capacitor, which is connected to the positive input terminal OP+ of the operational amplifier; and the second end of it is close to the branch selector Then each is connected to the output end of the selector of the branch circuit where it is located. That is, as shown in Figure 5(a), one plate of the first branch capacitor _C0 is connected to the positive input terminal OP+ of the operational amplifier, and the other plate is connected to the branch selector MUX(1) on the branch circuit where it is located. The output terminal is connected, one plate of the second branch capacitor 2C ₀ is connected to the positive input terminal OP+ of the operational amplifier, and the other plate is connected to the output terminal of the branch selector MUX (2) on the branch circuit where it is located, and so on . In each compensation branch circuit, the first input terminals IN1 of the branch selectors MUX(1), MUX(2), MUX(m) are connected and grounded, and the second input terminals IN2 are also connected together as the first adjustable capacitor The second terminal of is connected to the output terminal of the first selector M1. The two input terminals IN1 and IN2 of the first selector M1 are respectively connected to the two output terminals V _out+ and V _out− of the i-th pipeline stage. Here, the selection terminals S of the branch selectors MUX(1), MUX(2),..., MUX(m) are respectively controlled by the branch calibration signals F ₁ , F ₂ ,..., F _m , and the first selector M1 The selection terminal is controlled by the calibration signal F ₀ . When the branch calibration signal is at high level, the output terminal of the branch selector outputs the signal at its second input terminal, and when the branch calibration signal is at low level, the output terminal of the branch selector outputs the signal at its first input terminal.

如图5（b）所示是与运算放大器的负输入端OP-连接的第二可调电容的电路连接图。第二可调电容同样包括m个并联连接的补偿分支电路。与第一可调电容相同，每个补偿分支电路包括一分支电容和一分支选择器，各个分支电路中的分支电容的电容值分别是C₀、2C₀、4C₀、...、2^m-1C₀，呈2进制权重分布，其中，C₀为并联的补偿分支电路中的分支电容的单位电容值。各个分支电路中所有分支电容的远离选择器的第一端连接在一起，作为第二可调电容的第一端，与运算放大器负输入端OP-连接，而其靠近分支选择器的第二端则各自与其所在分支电路的选择器输出端连接。即，如图5（b）所示，第一个分支电容C₀的一个极板与运算放大器的负输入端OP-连接，另一个极板与其所在分支电路上的分支选择器MUX(m+1)的输出端连接，第二个分支电容2C₀的一个极板与运算放大器的负输入端OP-连接，另一个极板与其所在分支电路上的分支选择器MUX(m+2)的输出连接，依此类推。在每个补偿分支电路中，分支选择器MUX(m+1)、MUX(m+2)、MUX(m+m)的第一输入端IN1相连并接地，第二选择端IN2也连接在一起作为第二可调电容的第二端与第二选择器M2的输出端连接。而第二选择器M2的两个输入端IN1和IN2分别与第i级流水级的两个输出端V_out-、V_out+连接。这里，各个分支选择器MUX(m+1)、MUX(m+2)、…、MUX(m+m)的选择端S分别由与第一可调电容对应的相同的分支校准信号F₁、F₂、…、F_m控制，而第二选择器M2的选择端由校准信号F₀控制。当分支校准信号为高电平时，分支选择器的输出端输出其第二输入端的信号，而当分支校准信号为低电平时，分支选择器的输出端输出其第一输入端的信号。 As shown in FIG. 5( b ), it is a circuit connection diagram of the second adjustable capacitor connected to the negative input terminal OP- of the operational amplifier. The second adjustable capacitor also includes m compensation branch circuits connected in parallel. Same as the first adjustable capacitor, each compensation branch circuit includes a branch capacitor and a branch selector, and the capacitance values of the branch capacitors in each branch circuit are C ₀ , 2C ₀ , 4C ₀ , ..., 2 ^{m -1} C ₀ , showing a binary weight distribution, wherein C ₀ is the unit capacitance value of the branch capacitance in the parallel compensation branch circuit. The first ends of all the branch capacitors in each branch circuit that are far away from the selector are connected together as the first end of the second adjustable capacitor, which is connected to the negative input terminal OP- of the operational amplifier, and it is close to the second end of the branch selector Then each is connected to the selector output end of the branch circuit where it is located. That is, as shown in Figure 5(b), one plate of the first branch capacitor _C0 is connected to the negative input terminal OP- of the operational amplifier, and the other plate is connected to the branch selector MUX(m+ 1), one plate of the second branch capacitor 2C ₀ is connected to the negative input terminal OP- of the operational amplifier, and the other plate is connected to the output of the branch selector MUX (m+2) on the branch circuit where it is located connections, and so on. In each compensation branch circuit, the first input terminals IN1 of the branch selectors MUX(m+1), MUX(m+2), MUX(m+m) are connected and grounded, and the second selection terminals IN2 are also connected together The second terminal serving as the second adjustable capacitor is connected to the output terminal of the second selector M2. The two input terminals IN1 and IN2 of the second selector M2 are respectively connected to the two output terminals V _out- and V _out+ of the i-th pipeline stage. Here, the selection terminal S of each branch selector MUX(m+1), MUX(m+2), ..., MUX(m+m) is respectively controlled by the same branch calibration signal F ₁ , corresponding to the first adjustable capacitor. F ₂ , . . . , F _m are controlled, and the selection terminal of the second selector M2 is controlled by the calibration signal F ₀ . When the branch calibration signal is at high level, the output terminal of the branch selector outputs the signal at its second input terminal, and when the branch calibration signal is at low level, the output terminal of the branch selector outputs the signal at its first input terminal.

当分支校准信号F₁、F₂、…、F_m控制使分支电容的一个极板接地，就意味着该分支电容不连入补偿电路中，可调电容的值C_b-i表达式如下。 When the branch calibration signals F ₁ _, F ₂ _, .

${C C}_{b b__i i} = = {F f}_{11} \cdot &Center Dot; {C C}_{00} + + {F f}_{22} \cdot &Center Dot; 22 \cdot &Center Dot; {C C}_{00} + + . . . . . . + + {F f}_{m m} \cdot &Center Dot; 22^{m m - - 11} \cdot \cdot {C C}_{00} = = {Σ Σ}_{k k = = 11}^{m m} {F f}_{k k} \cdot \cdot 22^{k k - - 11} \cdot \cdot {C C}_{00} - - - - - - ((1111))$

如果校准需要较高的补偿精度，则可以选择大的m值，即增加分支电容阵列的分支电容的个数，同时，减小单位电容值C₀。如果补偿精度要求相对较低，则可以减少分支电容阵列的分支电容的个数。 If higher compensation accuracy is required for calibration, a larger value of m can be selected, that is, the number of branch capacitors in the branch capacitor array is increased, and the unit capacitance value C ₀ is decreased at the same time. If the compensation accuracy requirement is relatively low, the number of branch capacitors in the branch capacitor array can be reduced.

由此，根据计算得到的补偿电容值C_b-i，即可得到分支校准信号F₁、F₂、…、F_m。将所有校准信号F₀、F₁、F₂、…、F_m固化在芯片中后，在ADC正常转换模式下，补偿电路即可根据校准码对待校准级的级间增益误差进行补偿，完成校准。 Thus, branch calibration signals F ₁ , F ₂ , . . . , F _m can be obtained according to the calculated compensation capacitance C _bi . After all the calibration signals F ₀ , F ₁ , F ₂ ,..., F _m are solidified in the chip, in the normal conversion mode of the ADC, the compensation circuit can compensate the inter-stage gain error of the calibration stage according to the calibration code to complete the calibration .

需要说明的是，对于本领域技术人员能够理解的是，在上面的描述中未详细描述的内容，如，通过导线将相应部件电连接在一起，或者待校准流水级的除运算放大器外的其它电路结构，是本领域技术人员结合本说明书公开的内容以及现有技术能够容易地实现的，因此，在本说明书中不做详细描述。 It should be noted that those skilled in the art can understand that the content not described in detail in the above description, such as electrically connecting the corresponding components together through wires, or other components other than the operational amplifier of the pipeline level to be calibrated The circuit structure can be easily implemented by those skilled in the art in combination with the content disclosed in this specification and the prior art, so it will not be described in detail in this specification. the

以上所述仅为本发明的优选实施例，并非用来限制本发明的保护范围。对于本领域的技术人员来说，在不付出创造性劳动的前提下，可以对本发明做出若干的修改和替换，所有这些修改和替换都应涵盖在本发明的保护范围之内。 The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. For those skilled in the art, several modifications and substitutions can be made to the present invention without any creative work, and all these modifications and substitutions should be covered within the protection scope of the present invention. the

Claims

1. a pipelined ADC interstage gain calibration method, is characterized in that, comprises the following steps:

(1) Initialize the input signal Vin of the pipeline ADC, so that the input signal Vin_i of the i-th pipeline stage of the gain to be calibrated is in any position of the pipeline stage conversion interval except the highest conversion interval;

(2) In the form of a ramp signal, slowly increase the input signal Vin of the pipeline ADC, monitor the lowest digital output D_i_0 of the i-th pipeline level, and record the input V _{in_x1} of the pipeline ADC at this time when D_i_0 jumps for the first time and output D _{out_y1} ;

(3) Continue to slowly increase the input signal Vin of the pipeline ADC. When the lowest digital output D_i_0 of the i-th pipeline level jumps in the opposite phase to that of step (2), record the input V _{in_x2} and output of the pipeline ADC at this time. D _{out_y2} ;

(4) According to the input V _{in_x1} , V _{in_x2} and output D _{out_y1} , D _{out_y2} of the pipeline ADC obtained in steps (2) and (3), and use the following formula to determine the actual gain of the i-th pipeline stage whose gain is to be calibrated Gr_i,

Gr_i = \frac{({D.}_{out_the y 2} - {D.}_{out_the y 1}) &Center Dot; V_{FS}}{(2^{N} - 1) &Center Dot; (V_{in_x 2} - V_{in_x 1})}, i = 1,

or

Gr Gr__i i = = \frac{(({D D.}_{out out__y the y 22} - - {D D.}_{out out__y the y 11})) \cdot &Center Dot; {V V}_{FS FS}}{((22^{N N} - - 11)) \cdot &Center Dot; (({V V}_{in in__x x 22} - - {V V}_{in in__x x 11})) \cdot &Center Dot; {Π Π}_{j j = = 11}^{i i - - 11} G G__j j},, i i = = 22,, \cdot &Center Dot; \cdot &Center Dot; \cdot &Center Dot;,, n no

Among them, V _FS is the full-scale input range of the pipeline ADC, N is the resolution of the pipeline ADC,

is the product of the ideal gain value from the first stage to the i-th pipeline stage, Gr_i is the actual gain of the i-th pipeline stage, and n is the number of pipeline stages used by the pipeline ADC;

(5) Connect the first and second compensation circuits in the inter-stage gain amplifier circuit of the i-th pipeline stage of the gain to be calibrated, the inter-stage gain amplifier circuit of the i-level pipeline stage includes an operational amplifier, and the first The first and second compensation circuits are symmetrically arranged on the positive input side and the negative input side of the operational amplifier with respect to the operational amplifier; the first compensation circuit includes a first adjustable capacitor and a first selector, the second The second compensation circuit includes a second adjustable capacitor and a second selector, wherein the first adjustable capacitor and the second adjustable capacitor have the same capacitance C _{b_i} , and the first selector and the second selector are The same alternative selector, and where,

The first end of the first adjustable capacitor far away from the first selector is connected to the positive input end of the operational amplifier, and the second end close to the first selector is connected to the output end of the first selector connection; the first input end of the first selector is connected to the positive output end of the pipeline stage, the second input end is connected to the negative output end of the pipeline stage, and the selection end is connected to the calibration signal. When the calibration signal is at a high level, the The output terminal of the first selector outputs the signal of the second input terminal of the first selector, and when the calibration signal is low level, the output terminal of the first selector outputs the signal of the first selector a signal at the first input;

The first end of the second adjustable capacitor far away from the second selector is connected to the negative input end of the operational amplifier, and the second end close to the second selector is connected to the output end of the second selector connection; the first input end of the second selector is connected to the negative output end of the pipeline stage, the second input end is connected to the positive output end of the pipeline stage, and the selection end is connected to the calibration signal, when the calibration signal is high , the output terminal of the second selector outputs the signal of the second input terminal of the second selector, and when the calibration signal is low level, the output terminal of the second selector outputs the second selection The signal at the first input terminal of the device;

The first adjustable capacitor and the second adjustable capacitor have the same circuit structure, that is, include the same number of compensation branch circuits connected in parallel, each compensation branch circuit includes a branch capacitor and a branch selector, each compensation branch The branch selector in the circuit is the same one-two selector, and the value of the branch capacitance in each compensation branch circuit connected in parallel in turn satisfies: For the two branch capacitances in two adjacent compensation branch circuits, the order is The value of the last branch capacitor is twice the value of the previous branch capacitor; in each compensation branch circuit, the second terminal of the branch capacitor close to the branch selector is connected to the output terminal of the branch selector, and the first terminal of the branch selector The input terminal is grounded, and its selection terminal is connected to control the branch calibration signal of the compensation branch circuit where the branch selector is located, and the selection of the branch selector in the corresponding compensation branch circuit of the first adjustable capacitor and the second adjustable capacitor The terminal is connected to the same branch calibration signal. When the branch calibration signal is high level, the output terminal of the branch selector outputs the signal of its second input terminal, and when the branch calibration signal is low level, the output terminal of the branch selector outputs the signal of its second input terminal. an input signal;

In each compensation branch circuit of the first adjustable capacitor, the first ends of the branch capacitors far away from the branch selector are connected together in parallel as the first end of the first adjustable capacitor, and the first ends of the branch selector The two input terminals are connected together in parallel as the second terminal of the first adjustable capacitor; and

In each compensation branch circuit of the second adjustable capacitor, the first ends of the branch capacitors far away from the branch selector are connected together in parallel as the first end of the second adjustable capacitor, and the first ends of the branch selector The two input ends are connected together in parallel as the second end of the second adjustable capacitor;

(6) According to the actual gain Gr_i and the ideal gain G_i of the to-be-calibrated gain pipeline stage determined in step (4), combined with the inter-stage gain of the i-th pipeline stage connected to the first and second compensation circuits in step (5) Amplifier circuit, get the following formula, use this formula to determine the compensation capacitor value C _{b_i} required for compensation,

{((- - 11))}^{{F f}_{00}} \cdot \cdot {C C}_{b b__i i} = = {C C}_{S S} \cdot &Center Dot; ((\frac{11}{G G__i i} - - \frac{11}{Gr Gr__i i}))

In the formula, C _{b_i} is the compensation capacitance value required by the i-th pipeline stage, C _S is the sampling capacitance value, C _F is the feedback capacitance value, F ₀ is the calibration signal connected to the first and second selectors, F The value of ₀ is 0 or 1;

(7) According to the compensation capacitor value C _{b_i} required by the i-th pipeline stage determined in step (6), and combined with the following formula, determine the value of the branch calibration signal F ₁ -F _m , and convert these branch calibration signals F ₁ The value of -F _m and the value of the aforementioned calibration signal F ₀ are stored in the chip of the pipeline ADC;

{C C}_{b b__i i} = = {F f}_{11} \cdot &Center Dot; {C C}_{00} + + {F f}_{22} \cdot &Center Dot; 22 \cdot &Center Dot; {C C}_{00} + + . . . . . . + + {F f}_{m m} \cdot &Center Dot; 22^{m m - - 11} \cdot &Center Dot; {C C}_{00} = = {Σ Σ}_{k k = = 11}^{m m} {F f}_{k k} \cdot &Center Dot; 22^{k k - - 11} \cdot &Center Dot; {C C}_{00}

In the formula, m is the number of parallel compensation branch circuits in the first and second adjustable capacitors; C ₀ is the unit capacitance value of the branch capacitors in the parallel compensation branch circuits, that is, the branch in the first compensation branch circuit The value of the capacitor is C ₀ , the value of the branch capacitance in the second compensation branch circuit is 2C ₀ , the value of the branch capacitance in the third compensation branch circuit is 4C ₀ , and so on; F ₁ ..... F _m respectively represent the branch calibration signals connected to the selection terminals of the branch selectors in the first to m compensation branch circuits; and

(8) When the pipeline ADC is working normally, the inter-stage gain error of the i-th pipeline stage to be calibrated is compensated according to the values of the branch calibration signals F ₁ -F _m and the calibration signal F ₀ determined in step (7).

2. The pipelined ADC inter-stage gain calibration method according to claim 1, characterized in that, before step (5), steps (2)-(4) are repeated M times, and the pipeline obtained by each calculation is Calculate the average value of the actual gain value of each stage, and perform the following steps (6)-(8) according to the average value.