CN103840827A - Assembly line ADC interstage gain calibration method - Google Patents

Abstract

The invention provides an assembly line ADC interstage gain calibration method. After a chip is manufactured in an assembly line mode, firstly according to an interstage gain measuring scheme, the practical gains of assembly stages to be calibrated are measured; secondly, by means of the obtained practical gain values, the needed compensation capacitance value is determined by combining with a compensation circuit structure; afterwards, the determined compensation capacitance value is converted to a corresponding calibration signal and solidified in the chip of an assembly line ADC; finally, under the normal conversion mode of the assembly line ADC, the compensation circuit compensates for the interstage gain errors of the stages to be calibrated to finish calibration according to a calibration signal. The normal conversion process of the ADC will not be affected, losses of the circuit are few and high-precision calibration can be achieved.

Description

A kind of pipeline ADC inter-stage gain calibration methods thereof

Technical field

The present invention relates to a kind of streamline A/D converter (hereinafter to be referred as ADC) inter-stage gain calibration methods thereof, be mainly used in the gain error of pipelining-stage inter-stage gain amplifier to calibrate, belong to technical field of composite signal integrated circuits.

Background technology

Modern Communication System needs the ADC of high-speed, high precision.The high accuracy of ADC can prevent the phenomenon of distortion and loss weak signal, and the application of high-speed ADC can reduce the frequency conversion number of times of system.In the ADC of various structures, with it, the compromise characteristic of the excellence between precision, speed, power consumption three becomes the popular research structure of High Performance ADC to pipelined ad C.

The conversion accuracy of pipeline ADC is subject to the restriction of all kinds of errors in circuit.Error source main in system comprises: noise, clock jitter, capacitance mismatch, operational amplifier finite gain, operational amplifier set up that error, comparator imbalance voltage, switch are non-linear, charge injection and clock are burst logical.Wherein, capacitance mismatch, operational amplifier finite gain, operational amplifier are set up error and finally all can be caused the inter-stage gain amplifier gain of pipelining-stage to occur that error, Inter-stage gain error are the main factors of restriction pipeline ADC conversion accuracy.If do not adopt collimation technique, the precision of transducer will be limited in 10 bits.

Especially along with the raising of pipeline ADC precision and speed, front end pipelining-stage is more and more inclined to use every grade of many bit architecture, like this, the gain of inter-stage gain amplifier improves along with the increase of every grade of resolution bit number, respective feedback coefficient also can improve, and also means that the gain error of amplifier can be larger when having increased Amplifier Design difficulty.Therefore in the design of high-precision flow line ADC, be, essential accuracy guarantee means for the collimation technique of this error.

Be illustrated in figure 1 the system block diagram of pipeline ADC.Pipeline ADC is made up of the pipelining-stage of sampling hold circuit and multiple low precision.In each pipelining-stage, sub-ADC quantizes input signal, obtain digital output code, the sub-D/A converter of sub-DAC(simultaneously) quantized result of sub-ADC is converted into analog quantity, afterwards this analog quantity is cut from input, after amplification, export to next stage as residual signals from pipelining-stage and process.Here, sub-DAC function, subtraction function, enlarging function are realized by a switched-capacitor circuit, are called MDAC circuit, and inter-stage gain amplifier is realized enlarging function as a part for MDAC circuit.

Be illustrated in figure 2 the inter-stage gain amplifier circuit schematic diagram of pipelining-stage.Amplifier adopts switched capacitor amplifier structure, sampling capacitance C _swith feedback capacity C _fratio determined the perfect Gain G of amplifier, expression formula is as shown in Equation 1.

$G=\frac{C_S}{C_F}---\left(1\right)$

On above formula basis, consider limited operational amplifier gain error and capacitance mismatch error.First,, if operational amplifier gain is A, G expression formula is as formula 2; On this basis, suppose C _fhave error delta C, gain G expression formula is as formula 3.

$G=\frac{C_S}{C_F}\·(1-\frac{C_S+C_F}{A\·C_F})---\left(2\right)$

$G=\frac{C_S}{C_F+\mathrm{\ΔC}}\·(1-\frac{C_S+C_F+\mathrm{\ΔC}}{A\·(C_F+\mathrm{\ΔC})})---\left(3\right)$

Can see, under the effect of each error, the gain of interstage amplifier has departed from ideal value, can the serious conversion accuracy that limits ADC.Existing inter-stage gain calibration technology, or in circuit, need the extra pipelining-stage that copies to carry out test error, roll up circuitry consumes; Or background calibration, can affect the normal conversion of ADC, and limit the conversion speed of ADC.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of pipeline ADC inter-stage gain calibration methods thereof, it is for pipeline ADC Inter-stage gain error, realize the object of utilizing low circuit consumption to realize high-precision calibration, not only improve the linearity and the dynamic range thereof of pipeline ADC, and do not affected the normal data transfer process of ADC.

The technical scheme that the present invention solves the problems of the technologies described above comprises:

A kind of pipeline ADC inter-stage gain calibration methods thereof, comprises the following steps:

(1) the input signal Vin of initialization pipeline ADC, the input signal Vin_i of i level pipelining-stage that makes gain to be calibrated between this pipelining-stage transition zone except Jian Wai optional position, the highest transition zone;

(2) with ramp signal form, slowly increase the input signal Vin of pipeline ADC, the least significant digit output D_i_0 of monitoring i level pipelining-stage, in the time that D_i_0 for the first time saltus step occurs, records the now input V of pipeline ADC _{in_x1}with output D _{out_y1};

(3) continue the slowly input signal Vin of increase pipeline ADC, in the time that the saltus step anti-phase with step (2) occurs the least significant digit output D_i_0 of i level pipelining-stage, record the now input V of pipeline ADC _{in_x2}with output D _{out_y2};

(4) according to the input V of the pipeline ADC obtaining in step (2) and (3) _{in_x1}, V _{in_x2}with output D _{out_y1}, D _{out_y2}, and utilize formula below to determine the actual gain Gr_i of the i level pipelining-stage of gain to be calibrated,

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\·V_{\mathrm{FS}}}{(2^N-1)\·(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})},i=1,$ Or

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\·V_{\mathrm{FS}}}{(2^N-1)\·(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})\·\underset{j=1}{\overset{i-1}{\mathrm{\Π}}}G\_j},i=2,\·\·\·,n$

Wherein, V _fSfor the full scale input range of pipeline ADC, the resolution that N is pipeline ADC,

be the ideal gain value of i level pipelining-stage, Gr_i is the actual gain of i level pipelining-stage, and n is the pipelining-stage progression that pipeline ADC adopts;

(5) in the inter-stage gain amplifier circuit of the i level pipelining-stage of gain to be calibrated, connect the first and second compensating circuits, the inter-stage gain amplifier circuit of described i level pipelining-stage comprises an operational amplifier, and the positive input that described the first and second compensating circuits are arranged in described operational amplifier symmetrically with respect to described operational amplifier is distolateral distolateral with negative input; Described the first compensating circuit comprises the first tunable capacitor and first selector, and the second compensating circuit comprises the second tunable capacitor and second selector, and wherein, described the first tunable capacitor and the second tunable capacitor have identical capacitance C _{b_i}, described first selector and second selector are same alternative selector, and wherein,

Being connected away from the first end of described first selector and the positive input terminal of operational amplifier of described the first tunable capacitor, its second end near described first selector is connected with the output of described first selector; The first input end of described first selector connects the positive output end of pipelining-stage, the second input connects the negative output terminal of pipelining-stage, selecting side connects calibrating signal, in the time that described calibrating signal is high level, the output of described first selector is exported the signal of the second input of described first selector, and in the time that described calibrating signal is low level, the output of described first selector is exported the signal of the first input end of described first selector;

Being connected away from the first end of described second selector and the negative input end of operational amplifier of described the second tunable capacitor, its second end near described second selector is connected with the output of described second selector; The first input end of described second selector connects the negative output terminal of pipelining-stage, the second input connects the positive output end of pipelining-stage, selecting side connects described calibrating signal, in the time that described calibrating signal is high level, the output of described second selector is exported the signal of the second input of described second selector, and in the time that described calibrating signal is low level, the output of described second selector is exported the signal of the first input end of described second selector;

Described the first tunable capacitor and the second tunable capacitor have identical circuit structure,, comprise the compensation branch circuit of the equal number being connected in parallel, each compensation branch circuit comprises a tap capacitance and a branching selection device, branching selection device in each compensation branch circuit is identical alternative selector, and the value of tap capacitance in each compensation branch circuit being connected in parallel successively meets: to two tap capacitances in two adjacent compensation branch circuit, the value of the posterior tap capacitance of order is the twice of the value of tap capacitance above, in each compensation branch circuit, the second end of the close branching selection device of tap capacitance is connected to the output of branching selection device, the first input end ground connection of branching selection device, its selecting side connects branch's calibrating signal of controlling this branching selection device place compensation branch circuit, and the selecting side of the branching selection device in the corresponding compensation branch circuit of described the first tunable capacitor and the second tunable capacitor is connected identical branch's calibrating signal, in the time that branch's calibrating signal is high level, the output of branching selection device is exported the signal of its second input, and in the time that branch's calibrating signal is low level, the output of branching selection device is exported the signal of its first input end,

In each compensation branch circuit of described the first tunable capacitor, the first end away from branching selection device of tap capacitance is connected in parallel the first end as described the first tunable capacitor, and the second input of its branching selection device is connected in parallel the second end as described the first tunable capacitor; And

In each compensation branch circuit of described the second tunable capacitor, the first end away from branching selection device of tap capacitance is connected in parallel the first end as described the second tunable capacitor, and the second input of its branching selection device is connected in parallel the second end as described the second tunable capacitor;

(6) according to actual gain Gr_i and the perfect Gain G_i of the gain pipelining-stage to be calibrated of determining in step (4), in integrating step (5), be connected with the inter-stage gain amplifier circuit of the i level pipelining-stage of the first and second compensating circuits, obtain following formula, utilize this formula to determine the building-out capacitor value C that compensation is required _{b_i},

${(-1)}^{F_0}\·C_{b\_i}=C_S\·(\frac{1}{G\_i}-\frac{1}{\mathrm{Gr}\_i})$

In formula, C _{b_i}be the building-out capacitor value that i level pipelining-stage needs, C _sfor sampling capacitance value, C _ffor feedback capacity value, F ₀for being connected to the calibrating signal of described the first and second selectors, F ₀value be 0 or 1;

(7) the building-out capacitor value C needing according to the i level pipelining-stage of determining in step (6) _{b_i}, and combination formula below, determine the calibrating signal F of branch ₁-F _mvalue, and by the calibrating signal F of these branches ₁-F _mvalue and aforesaid calibrating signal F ₀value be stored in the chip of pipeline ADC;

$C_{b\_i}={\mathrm{<figure-callout\; id="1"\; label="F"\; filenames="HDA0000441281540000032.png,HDA0000441281540000041.png"\; state="\{\{state\}\}">F</figure-callout>}}_1\&CenterDot;C_0+{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000441281540000032.png,HDA0000441281540000041.png"\; state="\{\{state\}\}">F</figure-callout>}}_2\&CenterDot;2\&CenterDot;C_0+...+F_m\&CenterDot;2^{m-1}\&CenterDot;C_0=\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{F}_k\&CenterDot;2^{k-1}\&CenterDot;C_0$

In formula, m is the quantity of the compensation branch circuit of parallel connection in the first and second tunable capacitors; C ₀for the specific capacitance value of the tap capacitance in compensation branch circuit in parallel, that is, the value of the tap capacitance in first compensation branch circuit is C ₀, the value of the tap capacitance in second compensation branch circuit is 2C ₀, the value of the tap capacitance in the 3rd compensation branch circuit is 4C ₀, by that analogy; F ₁... ..F _mrepresent respectively branch's calibrating signal of the selecting side that is connected to first to m branching selection device in compensation branch circuit; And

(8) in the time that pipeline ADC is normally worked, according to the calibrating signal F of branch definite in step (7) ₁-F _mand calibrating signal F ₀value the Inter-stage gain error of i level pipelining-stage to be calibrated is compensated.

Preferably, in execution step (5) before, repeated execution of steps (2)-(4) M time, and the pipelining-stage actual gain value at every turn calculating is averaged, and carry out step (6)-(8) below according to this mean value.

Compared with prior art, pipeline ADC inter-stage gain calibration methods thereof according to the present invention possesses useful technique effect:

1,, as the one of producer calibration, it can not affect the normal conversion process of ADC;

2, only need the lowest order digit word output signal of the inner pipelining-stage circuit of ADC to be drawn out to chip pin, can measure the inter-stage gain amplifier of this pipelining-stage, circuitry consumes is very little;

3, the variable capacitance in compensating circuit is made up of multiple tap capacitance arrays, increases the number of tap capacitance, and the size that reduces unit tap capacitance can realize the compensation of little step-length, has effectively improved compensation precision.

Brief description of the drawings

Fig. 1 is the system block diagram according to pipeline ADC of the present invention;

Fig. 2 (a) and Fig. 2 (b) are according to the structural representation of pipelining-stage amplifier of the present invention;

Fig. 3 (a) and Fig. 3 (b) are the pipelining-stage transfer curve figure of the pipeline ADC of the present invention of basis;

Fig. 4 is according to the inter-stage gain amplifier circuit compensation principle schematic diagram of the gain pipelining-stage to be calibrated after connection the first and second compensating circuits of the present invention; And

Fig. 5 (a) and Fig. 5 (b) are the circuit connection diagrams according to the first and second compensating circuits of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, pipeline ADC inter-stage gain calibration methods thereof according to the present invention is further described in detail.

In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with example and accompanying drawing, the present invention is described in further detail.Be used for explaining and explanation in this illustrative examples of the present invention and explanation, but not as limiting to the invention.

In pipeline ADC inter-stage gain calibration methods thereof of the present invention, after chip flow, first, treat the actual gain of calibration pipelining-stage according to inter-stage gain measurement scheme and measure; , utilize the actual gain value that obtain, in conjunction with compensating circuit structure, determine the building-out capacitor value needing thereafter; Next, definite building-out capacitor value is converted in the chip that corresponding calibrating signal is solidificated in pipeline ADC; Finally, under the normal conversion pattern of pipeline ADC, compensating circuit compensates the Inter-stage gain error of level to be calibrated according to calibrating signal, completes calibration.

As shown in Fig. 3 (a) and Fig. 3 (b), be the pipelining-stage transfer characteristic figure of 3 bits, we will set forth pipeline ADC inter-stage gain calibration methods thereof according to the present invention as an example of this pipelining-stage (supposing that this pipelining-stage is as i level) example.

In the time that the analog input signal of pipelining-stage is positioned between different transition zones, the corresponding numeral output of pipelining-stage is also as shown in mark in figure.Can see, the lowest order D_i_0 that exports digital code between adjacent transition zone is alternately 0 or 1, the measurement that calibration steps of the present invention utilizes this characteristic to gain.In circuit design, the least significant digit output D_i_0 of pipelining-stage to be calibrated is connected to chip output mouth, under test pattern, detect from outside to this signal.

First, the input signal Vin of initialization pipeline ADC, the input signal Vin_i of i level pipelining-stage that makes gain to be calibrated between this pipelining-stage transition zone except Jian Wai optional position, the highest transition zone, as S point.

Afterwards, with ramp signal (Ramp) form, slowly increase the input signal Vin of pipeline ADC, monitor the least significant digit output D_i_0 of i level pipelining-stage to be calibrated, in the time that D_i_0 for the first time saltus step occurs, (can be to jump to 1 from 0, or jump to 0 from 1), be A point, record the now input V of pipeline ADC _{in_x1}with output D _{out_y1}.

Next, continue slowly to increase the input signal Vin of pipeline ADC, in the time that the saltus step anti-phase with step (2) occurs D_i_0, (jump to 0 from 1, or jump to 1 from 0), record the now input V of pipeline ADC _{in_x2}with output D _{out_y2}.

Afterwards, according to the input V of the pipeline ADC recording above _{in_x1}, V _{in_x2}with output D _{out_y1}, D _{out_y2}, by the actual gain Gr_i of the i level pipelining-stage of formula 4 calculative determination gain to be calibrated below.

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\&CenterDot;V_{\mathrm{FS}}}{(2^N-1)\&CenterDot;(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})},i=1$

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\&CenterDot;V_{\mathrm{FS}}}{(2^N-1)\&CenterDot;(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})\&CenterDot;\underset{j=1}{\overset{i-1}{\mathrm{\&Pi;}}}G\_j},i=2,\&CenterDot;\&CenterDot;\&CenterDot;,n---\left(4\right)$

Wherein, V _fSfor the full scale input range of pipeline ADC, the resolution that N is pipeline ADC,

for the first order is to the product of the ideal gain value of i level pipelining-stage, Gr_i is the actual gain of i level pipelining-stage, and n is the pipelining-stage progression that pipeline ADC adopts.

For avoiding the final certainty of measurement of sporadic error interference, can continue slowly to increase the input signal Vin of pipeline ADC, and repeating step (2), (3), (4), calculate the slope between every section of transition zone, be averaging and obtain more accurate pipelining-stage actual gain Gr_i.A step of every repetition (2), (3), (4) obtain a pipelining-stage yield value Gr_i_j(wherein, and j represents the number of times of repeating step (2)-(4)), after M circulation, the actual gain mean value of i level pipelining-stage is by formula

obtain.

In conjunction with formula (3) above, the actual gain that can obtain i level pipelining-stage is as formula (5) below.Measure after Gr_i, this equation comprises Δ C and two variablees of A.

$\frac{C_S}{C_F+\mathrm{\&Delta;C}}\&CenterDot;(1-\frac{C_S+C_F+\mathrm{\&Delta;C}}{A\&CenterDot;(C_F+\mathrm{\&Delta;C})})=\mathrm{Gr}\_i---\left(5\right)$

Next calculate the pipelining-stage yield value being connected into after compensating circuit.

Gain error compensation principle schematic diagram as shown in Figure 4.Compensating circuit is by tunable capacitor C _b-iwith corresponding control circuit composition, it is combined and realizes compensate function with pipelining-stage.Because pipelining-stage adopts Full differential operational amplifier, therefore, need two compensating circuits, i.e. the first compensating circuit and the second compensating circuit.Two compensating circuits are identical, all comprise that a tunable capacitor (being called the first tunable capacitor and the second tunable capacitor) and an alternative selector (becoming respectively first selector and second selector) are as control circuit.Two compensating circuits are arranged symmetrically with respect to the operational amplifier of pipelining-stage.Wherein, in the first compensating circuit, the first end away from first selector of the first tunable capacitor is connected with the positive input terminal OP+ of operational amplifier, and its second end near first selector is connected with the output of first selector M1.The first input end IN1 of first selector M1 connects the positive output end V of pipelining-stage _out+, the second input IN2 connects the negative output terminal V of pipelining-stage _out-, its selecting side S connects outside calibrating signal F ₀.In the time that outside calibrating signal is high level " 1 ", the signal of the second input of the output output first selector of first selector M1, and in the time that calibrating signal is low level " 0 ", the signal of the first input end of the output output first selector of first selector.

In the second compensating circuit, the first end away from second selector M2 of the second tunable capacitor is connected with the negative input end OP-of operational amplifier, and its second end near second selector M2 is connected with the output of second selector M2.The first input end IN1 of second selector M2 connects the negative output terminal V of pipelining-stage _out-, the second input IN2 connects the positive output end V of pipelining-stage _out+, selecting side S connects the calibrating signal F of described outside ₀.In the time that calibrating signal is high level, the signal of the second input of the output output second selector of second selector, and in the time that calibrating signal is low level, the signal of the first input end of the output output second selector of second selector.

Above-mentioned first selector M1 is all connected calibrating signal F with the selecting side S of second selector M2 ₀.

When pipelining-stage is during in sampling phase (as shown in Fig. 2 (a)), the difference input of operational amplifier and difference output end are as shown in Figure 2 (a) shows all in short circuit state, two input terminal voltages are identical and be constant, two output end voltages are also identical and be constant, therefore, feedback capacity C on two difference paths _fwith building-out capacitor C _{b_i}level value that two-plate connects is identical, does not affect sampling capacitance C _sthe input of sampling difference.

At pipelining-stage, in amplifying (as shown in Fig. 2 (b)) when phase place, after being compensated according to law of conservation of charge, the gain G c_i of i level pipelining-stage is as formula 6 below.Wherein, C _sfor sampling capacitance, C _ffor feedback capacity, Δ C is C _fmismatch error, F ₀for calibrating signal (digital signal), C _b-ifor building-out capacitor value.

$\mathrm{Gc}\_i=\frac{C_S}{C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i}}\&CenterDot;(1-\frac{C_S+C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i}}{A\&CenterDot;(C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i})})---\left(6\right)$

Can see, because operational amplifier gain A is very large compared with capacitance,

be approximately 1, therefore, C _b-imainly by directly to C _fcompensate to realize the calibration to gain.

Our calibration target is that the gain G c_i of the i level pipelining-stage after order compensation equals the perfect Gain G_i of pipelining-stage, as formula below, has so just completed calibration.

$\frac{C_S}{C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i}}\&CenterDot;(1-\frac{C_S+C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i}}{A\&CenterDot;(C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}\&CenterDot;C_{b\_i})})=C\_i---\left(7\right)$

In conjunction with formula 5, can obtain two about Δ C, A and C _bequation.Calculate building-out capacitor C according to two equatioies _b-ivalue, just can compensate the gain error of i level pipelining-stage.

Introduce how to obtain the C that compensate according to these two equatioies below _b-ivalue.Because equation only has two, and unknown quantity has three, therefore, cannot directly obtain answering building-out capacitor C by calculating _b-ithe analytic solutions of value.In view of the gain A of operational amplifier very large, in formula 5 with in formula 7

be approximately 1, ignore this and can remove a variables A, like this, variable only has two, can calculate the final C that needs compensation _b-ivalue.

First, ignore the error term in formula 5 and formula 7 brackets

with

obtain formula 8 and formula 9 below, calculate building-out capacitor C _b-i, calibrating signal F ₀determine building-out capacitor C _b-icompensation direction, when

time, calibrating signal F ₀should be low level " 0 ", when time, calibrating signal F ₀should be high level " 1 ".

$\mathrm{Gr}\_i=\frac{C_S}{C_F+\mathrm{\&Delta;C}}---\left(8\right)$

$G\_i=\frac{C_S}{C_F+\mathrm{\&Delta;C}+{(-1)}^{F_0}{C}_b}---\left(9\right)$

${(-1)}^{F_0}\&CenterDot;C_{b\_i}=C_S\&CenterDot;(\frac{1}{G\_i}-\frac{1}{\mathrm{Gr}\_i})---\left(10\right)$

As shown in Fig. 5 (a) and Fig. 5 (b), be the circuit connection diagram of the first and second tunable capacitors, Fig. 5 (a) and Fig. 5 (b) are respectively the circuit connection diagrams of the first and second tunable capacitors of being connected with two differential input ends of operational amplifier.

It as shown in Fig. 5 (a), is the circuit connection diagram of the first tunable capacitor of being connected with the positive input terminal OP+ of operational amplifier.The first tunable capacitor comprises m the compensation branch circuit being connected in parallel, and each compensation branch circuit comprises a tap capacitance and a branching selection device, and the capacitance of the tap capacitance in each branch circuit is respectively C ₀, 2C ₀, 4C ₀..., 2 ^m-1c ₀, be 2 system weight distribution, wherein C ₀for the specific capacitance value of the tap capacitance in compensation branch circuit in parallel.In each branch circuit, the first end away from selector of all tap capacitances links together, and as the first end of the first tunable capacitor, is connected with the positive input terminal OP+ of operational amplifier; Its second end near branching selection device is connected with the output of the selector of its place branch circuit separately.That is, as shown in Fig. 5 (a), first tap capacitance C ₀a pole plate be connected with the positive input terminal OP+ of operational amplifier, another pole plate is connected with the output of the branching selection device MUX (1) on its place branch circuit, second tap capacitance 2C ₀a pole plate be connected with the positive input terminal OP+ of operational amplifier, another pole plate is connected with the output of the branching selection device MUX (2) on its place branch circuit, the rest may be inferred.In each compensation branch circuit, the first input end IN1 of branching selection device MUX (1), MUX (2), MUX (m) is connected and ground connection, and the second input IN2 also links together and is connected with the output of first selector M1 as the second end of the first tunable capacitor.And two input IN1 of first selector M1 and IN2 respectively with two output V of i level pipelining-stage _out+, V _out-connect.Here, each branching selection device MUX (1), MUX (2) ..., MUX (m) selecting side S respectively by the calibrating signal F of branch ₁, F ₂..., F _mcontrol, and the selecting side of first selector M1 is by calibrating signal F ₀control.In the time that branch's calibrating signal is high level, the output of branching selection device is exported the signal of its second input, and in the time that branch's calibrating signal is low level, the output of branching selection device is exported the signal of its first input end.

It as shown in Fig. 5 (b), is the circuit connection diagram of the second tunable capacitor of being connected with the negative input end OP-of operational amplifier.The second tunable capacitor comprises m the compensation branch circuit being connected in parallel equally.Identical with the first tunable capacitor, each compensation branch circuit comprises a tap capacitance and a branching selection device, and the capacitance of the tap capacitance in each branch circuit is respectively C ₀, 2C ₀, 4C ₀..., 2 ^m-1c ₀, be 2 system weight distribution, wherein, C ₀for the specific capacitance value of the tap capacitance in compensation branch circuit in parallel.In each branch circuit, the first end away from selector of all tap capacitances links together, as the first end of the second tunable capacitor, OP-is connected with operational amplifier negative input end, and its second end near branching selection device is connected with the selector output end of its place branch circuit separately.That is, as shown in Fig. 5 (b), first tap capacitance C ₀a pole plate be connected with the negative input end OP-of operational amplifier, another pole plate is connected with the output of the branching selection device MUX (m+1) on its place branch circuit, second tap capacitance 2C ₀a pole plate be connected with the negative input end OP-of operational amplifier, another pole plate is connected with the output of the branching selection device MUX (m+2) on its place branch circuit, the rest may be inferred.In each compensation branch circuit, the first input end IN1 of branching selection device MUX (m+1), MUX (m+2), MUX (m+m) is connected and ground connection, and the second selecting side IN2 also links together and is connected with the output of second selector M2 as the second end of the second tunable capacitor.And two input IN1 of second selector M2 and IN2 respectively with two output V of i level pipelining-stage _out-, V _out+connect.Here, each branching selection device MUX (m+1), MUX (m+2) ..., MUX (m+m) selecting side S respectively by the identical branch calibrating signal F corresponding with the first tunable capacitor ₁, F ₂..., F _mcontrol, and the selecting side of second selector M2 is by calibrating signal F ₀control.In the time that branch's calibrating signal is high level, the output of branching selection device is exported the signal of its second input, and in the time that branch's calibrating signal is low level, the output of branching selection device is exported the signal of its first input end.

As the calibrating signal F of branch ₁, F ₂..., F _mcontrol makes a pole plate ground connection of tap capacitance, just means that this tap capacitance is not connected in compensating circuit, the value C of tunable capacitor _b-iexpression formula is as follows.

$C_{b\_i}={\mathrm{<figure-callout\; id="1"\; label="F"\; filenames="HDA0000441281540000032.png,HDA0000441281540000041.png"\; state="\{\{state\}\}">F</figure-callout>}}_1\&CenterDot;C_0+{\mathrm{<figure-callout\; id="2"\; label="F"\; filenames="HDA0000441281540000032.png,HDA0000441281540000041.png"\; state="\{\{state\}\}">F</figure-callout>}}_2\&CenterDot;2\&CenterDot;C_0+...+F_m\&CenterDot;2^{m-1}\&CenterDot;C_0=\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{F}_k\&CenterDot;2^{k-1}\&CenterDot;C_0---\left(11\right)$

If calibration needs higher compensation precision, can select large m value, increase the number of the tap capacitance of tap capacitance array, meanwhile, reduce specific capacitance value C ₀.If it is relatively low that compensation precision requires, can reduce the number of the tap capacitance of tap capacitance array.

Thus, according to the building-out capacitor value C calculating _b-i, can obtain the calibrating signal F of branch ₁, F ₂..., F _m.By all calibrating signal F ₀, F ₁, F ₂..., F _mafter being solidificated in chip, under ADC normal conversion pattern, compensating circuit can compensate the Inter-stage gain error of level to be calibrated according to calibration code, completes calibration.

It should be noted that, what can understand for those skilled in the art is, the content of not describing in detail in superincumbent description, as, by wire, corresponding component is electrically connected, or other circuit structure outside the division operation amplifier of pipelining-stage to be calibrated, be that those skilled in the art can easily realize in conjunction with the disclosed content of this specification and prior art, therefore, be not described in detail in this manual.

The foregoing is only the preferred embodiments of the present invention, be not used for limiting the scope of the invention.For a person skilled in the art, do not paying under the prerequisite of creative work, can make some amendments and replacement to the present invention, within all such modifications and replacement all should be encompassed in protection scope of the present invention.

Claims (2)

1. a pipeline ADC inter-stage gain calibration methods thereof, is characterized in that, comprises the following steps:

(1) the input signal Vin of initialization pipeline ADC, the input signal Vin_i of i level pipelining-stage that makes gain to be calibrated between this pipelining-stage transition zone except Jian Wai optional position, the highest transition zone;

(2) with ramp signal form, slowly increase the input signal Vin of pipeline ADC, the least significant digit output D_i_0 of monitoring i level pipelining-stage, in the time that D_i_0 for the first time saltus step occurs, records the now input V of pipeline ADC _{in_x1}with output D _{out_y1};

(3) continue the slowly input signal Vin of increase pipeline ADC, in the time that the saltus step anti-phase with step (2) occurs the least significant digit output D_i_0 of i level pipelining-stage, record the now input V of pipeline ADC _{in_x2}with output D _{out_y2};

(4) according to the input V of the pipeline ADC obtaining in step (2) and (3) _{in_x1}, V _{in_x2}with output D _{out_y1}, D _{out_y2}, and utilize formula below to determine the actual gain Gr_i of the i level pipelining-stage of gain to be calibrated,

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\&CenterDot;V_{\mathrm{FS}}}{(2^N-1)\&CenterDot;(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})},i=1,$ Or

$\mathrm{Gr}\_i=\frac{(D_{\mathrm{out}\_y2}-D_{\mathrm{out}\_y1})\&CenterDot;V_{\mathrm{FS}}}{(2^N-1)\&CenterDot;(V_{\mathrm{in}\_x2}-V_{\mathrm{in}\_x1})\&CenterDot;\underset{j=1}{\overset{i-1}{\mathrm{\&Pi;}}}G\_j},i=2,\&CenterDot;\&CenterDot;\&CenterDot;,n$

Wherein, V _fSfor the full scale input range of pipeline ADC, the resolution that N is pipeline ADC,

for the first order is to the product of the ideal gain value of i level pipelining-stage, Gr_i is the actual gain of i level pipelining-stage, and n is the pipelining-stage progression that pipeline ADC adopts;

(5) in the inter-stage gain amplifier circuit of the i level pipelining-stage of gain to be calibrated, connect the first and second compensating circuits, the inter-stage gain amplifier circuit of described i level pipelining-stage comprises an operational amplifier, and the positive input that described the first and second compensating circuits are arranged in described operational amplifier symmetrically with respect to described operational amplifier is distolateral distolateral with negative input; Described the first compensating circuit comprises the first tunable capacitor and first selector, and the second compensating circuit comprises the second tunable capacitor and second selector, and wherein, described the first tunable capacitor and the second tunable capacitor have identical capacitance C _{b_i}, described first selector and second selector are same alternative selector, and wherein,

Being connected away from the first end of described first selector and the positive input terminal of operational amplifier of described the first tunable capacitor, its second end near described first selector is connected with the output of described first selector; The first input end of described first selector connects the positive output end of pipelining-stage, the second input connects the negative output terminal of pipelining-stage, selecting side connects calibrating signal, in the time that described calibrating signal is high level, the output of described first selector is exported the signal of the second input of described first selector, and in the time that described calibrating signal is low level, the output of described first selector is exported the signal of the first input end of described first selector;

Being connected away from the first end of described second selector and the negative input end of operational amplifier of described the second tunable capacitor, its second end near described second selector is connected with the output of described second selector; The first input end of described second selector connects the negative output terminal of pipelining-stage, the second input connects the positive output end of pipelining-stage, selecting side connects described calibrating signal, in the time that described calibrating signal is high level, the output of described second selector is exported the signal of the second input of described second selector, and in the time that described calibrating signal is low level, the output of described second selector is exported the signal of the first input end of described second selector;

Described the first tunable capacitor and the second tunable capacitor have identical circuit structure,, comprise the compensation branch circuit of the equal number being connected in parallel, each compensation branch circuit comprises a tap capacitance and a branching selection device, branching selection device in each compensation branch circuit is identical alternative selector, and the value of tap capacitance in each compensation branch circuit being connected in parallel successively meets: to two tap capacitances in two adjacent compensation branch circuit, the value of the posterior tap capacitance of order is the twice of the value of tap capacitance above, in each compensation branch circuit, the second end of the close branching selection device of tap capacitance is connected to the output of branching selection device, the first input end ground connection of branching selection device, its selecting side connects branch's calibrating signal of controlling this branching selection device place compensation branch circuit, and the selecting side of the branching selection device in the corresponding compensation branch circuit of described the first tunable capacitor and the second tunable capacitor is connected identical branch's calibrating signal, in the time that branch's calibrating signal is high level, the output of branching selection device is exported the signal of its second input, and in the time that branch's calibrating signal is low level, the output of branching selection device is exported the signal of its first input end,

In each compensation branch circuit of described the first tunable capacitor, the first end away from branching selection device of tap capacitance is connected in parallel the first end as described the first tunable capacitor, and the second input of its branching selection device is connected in parallel the second end as described the first tunable capacitor; And

In each compensation branch circuit of described the second tunable capacitor, the first end away from branching selection device of tap capacitance is connected in parallel the first end as described the second tunable capacitor, and the second input of its branching selection device is connected in parallel the second end as described the second tunable capacitor;

(6) according to actual gain Gr_i and the perfect Gain G_i of the gain pipelining-stage to be calibrated of determining in step (4), in integrating step (5), be connected with the inter-stage gain amplifier circuit of the i level pipelining-stage of the first and second compensating circuits, obtain following formula, utilize this formula to determine the building-out capacitor value C that compensation is required _{b_i},

${(-1)}^{F_0}\&CenterDot;C_{b\_i}=C_S\&CenterDot;(\frac{1}{G\_i}-\frac{1}{\mathrm{Gr}\_i})$

In formula, C _{b_i}be the building-out capacitor value that i level pipelining-stage needs, C _sfor sampling capacitance value, C _ffor feedback capacity value, F ₀for being connected to the calibrating signal of described the first and second selectors, F ₀value be 0 or 1;

(7) the building-out capacitor value C needing according to the i level pipelining-stage of determining in step (6) _{b_i}, and combination formula below, determine the calibrating signal F of branch ₁-F _mvalue, and by the calibrating signal F of these branches ₁-F _mvalue and aforesaid calibrating signal F ₀value be stored in the chip of pipeline ADC;

$C_{b\_i}=F_1\&CenterDot;C_0+F_2\&CenterDot;2\&CenterDot;C_0+...+F_m\&CenterDot;2^{m-1}\&CenterDot;C_0=\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{F}_k\&CenterDot;2^{k-1}\&CenterDot;C_0$

In formula, m is the quantity of the compensation branch circuit of parallel connection in the first and second tunable capacitors; C ₀for the specific capacitance value of the tap capacitance in compensation branch circuit in parallel, that is, the value of the tap capacitance in first compensation branch circuit is C ₀, the value of the tap capacitance in second compensation branch circuit is 2C ₀, the value of the tap capacitance in the 3rd compensation branch circuit is 4C ₀, by that analogy; F ₁... ..F _mrepresent respectively branch's calibrating signal of the selecting side that is connected to first to m branching selection device in compensation branch circuit; And

(8) in the time that pipeline ADC is normally worked, according to the calibrating signal F of branch definite in step (7) ₁-F _mand calibrating signal F ₀value the Inter-stage gain error of i level pipelining-stage to be calibrated is compensated.

2. pipeline ADC inter-stage gain calibration methods thereof according to claim 1, it is characterized in that, in execution step (5) before, repeated execution of steps (2)-(4) M time, and the pipelining-stage actual gain value at every turn calculating is averaged, and carry out step (6)-(8) below according to this mean value.

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