CN107453756B

CN107453756B - Front-end calibration method for pipeline ADC

Info

Publication number: CN107453756B
Application number: CN201710706615.XA
Authority: CN
Inventors: 唐鹤; 牛胜普; 高昂; 何生生; 车来晟
Original assignee: University of Electronic Science and Technology of China
Current assignee: Xinchen (Chongqing) Microelectronics Co.,Ltd.
Priority date: 2017-08-17
Filing date: 2017-08-17
Publication date: 2020-02-04
Anticipated expiration: 2037-08-17
Also published as: CN107453756A

Abstract

A front end calibration method for a pipeline ADC belongs to the technical field of analog integrated circuits. The method starts to correct from the first-stage gain of the pipeline ADC until the front N-1-stage gain of the pipeline ADC is corrected in sequence, and the error between a restored signal and an original signal can be obtained after the first-stage gain to the N-1-stage gain are obtained; specifically, each stage of gain of the pipeline ADC is searched based on an MATLAB program, then the output data of the pipeline ADC is restored, the restored signal is subjected to fast Fourier transform analysis, and when indexes such as the number of significant digits meet requirements, the gain is found correctly, so that the calibration of the pipeline ADC is realized. The method overcomes the defect of low traditional calibration precision in the high-speed high-precision pipeline ADC, has the characteristics of high efficiency, rapidness and accuracy, and is relatively suitable for calibrating the high-speed high-precision pipeline ADC.

Description

Front-end calibration method for pipeline ADC

Technical Field

The invention belongs to the field of analog integrated circuits, and particularly relates to a front-end calibration method for a pipeline ADC.

Background

The pipeline ADC structure is shown in FIG. 1, an input signal is sampled by a sample-and-hold circuit and then is sent to the pipeline unit ADC, and each unit ADC alternately performs sampling and residue difference amplification under the control of a two-phase non-overlapping clock. In the unit ADC, sampling phase time signals are simultaneously sampled by a multiplication digital-to-analog converter MDAC and a sub-ADC, and the sub-ADC generates a digital code Di through comparison; when the phase is kept, Di is subtracted from the input signal through the MDAC to generate a residual difference, the MDAC amplifies the residual difference, and the amplified residual difference is sent to the next stage to be used as the input signal of the next stage. The MDAC input-output relationship is as follows:

wherein Gain is the Gain of MDAC, A is the open loop Gain of the operational amplifier in MDAC, V_refIs a reference voltage, C_fFor feedback capacitance, C_kTo sample the capacitance, C_pThe parasitic capacitance of the input end of the operational amplifier comprises an input tube parasitic capacitance C_gs、C_gbAnd C_gd. The traditional MDAC can realize the high Gain requirement of the operational amplifier in the low-speed low-precision pipeline ADC, so that the Gain of the MDAC is approximately equal to the ideal value, namely constant

However, as the pipeline ADC develops towards high speed and high precision, the high speed and high precision pipeline ADC has higher and higher requirements on the unit gain and bandwidth product of the operational amplifier, the high bandwidth and high gain operational amplifier is difficult to realize, and the MDAC gain is not equal to a constant any more

Thereby, gain errors occur, which brings nonlinearity and further affects the performance of the ADC. In recent years, high-speed and high-precision pipeline ADCs usually sacrifice operational amplifier gain, ensure the operational amplifier speed, determine each stage of gain through a calibration algorithm, and further reduce the nonlinearity of the pipeline ADC.

Disclosure of Invention

The invention aims to provide a front-end calibration method for a pipeline ADC (analog to digital converter), which is used for calibrating the front N-1-level gain of the ADC, and has the advantages of less analog quantity required by calibration, high calibration speed and high precision. The method can be used in the field of high-speed high-precision pipeline ADC calibration.

The technical scheme of the invention is as follows:

a front-end calibration method for a pipelined ADC having N stages, where N is a positive integer greater than 1; the pipeline ADC starts to correct from the first-stage gain until the front N-1-stage gain of the pipeline ADC is corrected in sequence, and the front end of the pipeline ADC is calibrated once;

before calibration, obtaining the analog output V of each stage in the pipeline ADC by simulating the pipeline ADC circuit_outAnd a digital output D_out；

The step of correcting the nth stage gain of the pipelined ADC specifically comprises the following steps, wherein N is any one positive integer from 1 to N-1:

1.1: setting gains of other stages except the gain from the first stage to the nth stage in the pipeline ADC as ideal values, wherein the gain from the first stage to the nth-1 stage is the gain after calibration;

1.2: sequentially taking values of the nth gain from the left side and the right side of the ideal value of the nth gain in a fixed step length, and taking one nth gain value gain (n) every time to output the nth analog output V according to a calibration formula_out(n)And an nth order digital output D_out(n)Reducing to obtain nth-stage input voltage V_in(n)Said nth stage input voltage V_in(n)I.e. the analog output V of the (n-1) th stage_out(n-1)；

The calibration formula is

Wherein V_refIs a reference voltage of a pipelined ADC, C_kFor the sub-stage ADC internal sampling capacitance of the pipeline ADC, k is equal to [1, 2 ]ⁿ]；

1.3: the n-1 level digital output D obtained by analog simulation_out(n-1)And the analog output V of the n-1 th stage obtained in step 1.2_out(n-1)Reducing according to a calibration formula to obtain the n-1 th-level input voltage V_in(n-1)I.e. the analog output V of the (n-2) th stage_out(n-2)When the gain of the (n-1) th stage in the formula is the gain of the (n-1) th stage after calibration;

1.4: sequentially reducing according to the step 1.2 and the step 1.3 to obtain a first-stage input voltage V_in(1)；

1.5: to alsoThe originally obtained first-stage input voltage V_in(1)Carrying out fast Fourier transform analysis and calculation to obtain the effective digit;

1.6: and analyzing the significand obtained by calculating each nth gain value gain (n) taken in the step 1.2, wherein the value gain (n) of the nth gain corresponding to the maximum value of the significand is the nth gain after calibration.

The invention has the beneficial effects that: the calibration method provided by the invention can obviously reduce the nonlinearity of the pipeline ADC, improves the defect of low traditional calibration precision in the high-speed high-precision pipeline ADC, and has the characteristics of high efficiency, rapidness and accuracy.

Drawings

FIG. 1 is a block diagram of a pipelined ADC;

FIG. 2 is a first stage quantization error model of a pipeline ADC;

FIG. 3 is a model of the total quantization error of a pipeline ADC;

fig. 4 is a flowchart for calibrating the gain of the nth stage in the front-end calibration method for pipeline ADC according to the present invention.

Detailed Description

The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and specific embodiments:

as shown in fig. 2, for the N-bit pipeline ADC, the signal flows into the Stage1 through the sample-and-hold circuit, the sampling phase time signal is simultaneously sampled by the sub-ADC and the MDAC, and the signal is compared by the sub-ADC to generate a digital output Di; when the phase is kept, the digital code Di is restored by a DAC in the MDAC and is differed with the input signal, and then the digital code Di is amplified to generate a residual difference voltage V_res. In this process, the sub-ADC quantizes the input signal to generate a quantization error epsilon_q. The input-output relationship is as follows:

D＝V_in+ε_q(3)

V_res＝Gain*ε_q(4)

in FIG. 2, the quantization errors of the stages other than the first stage are represented by ε_qbShows that the first-stage gain G is found when the calibration algorithm is used for calibration as shown in formula (5)_d1＝G₁Then, the reduced signal can be obtainedError of original signal is

In FIG. 3, the quantization error per stage is represented by ε_qiShowing that i takes 1 to N-1, and when the gain G of the first to N-1 stages is found through calibration of a calibration algorithm_di＝G_iThen, the error between the restored signal and the original signal is obtained as

As can be seen from the formula (4), after calibration, the gain G of each stage of the pipeline ADC is calibrated_diAnd the actual gain G_iThe closer, D_outAnd V_inThe smaller the error between, the higher the calibration accuracy.

From equation (6), the quantization error ε of the first stage can be found_q1Quantization error epsilon of second stage_q2To D_outLarge influence, third-level quantization error epsilon_q3More than second-stage quantization error epsilon_q2Difference pair D_outThe influence is large, and so on in the following stages. Therefore, we calibrate each stage of Gain starting with calibrating the first stage of Gain 1.

The invention searches the gain of each stage of the pipeline ADC based on the MATLAB program.

When the first-stage Gain1 of the pipeline ADC is calibrated, the gains of other stages are set to be ideal Gain values, the first-stage Gain1 takes values from the left side and the right side of the ideal values in fixed step length, and the ideal value of each stage of Gain passes through

Determining; the first stage Gain1 uses a calibration formula to output the first stage analog output V each time it takes a value_out1And digital inputGo out D_out1Reducing to obtain a first-stage input voltage V_in1For the restored first stage input voltage V_in1And performing Fast Fourier Transform (FFT) analysis to calculate the effective digit ENOB. And storing ENOB obtained by calculating each value of Gain 1. And finally, analyzing ENOB corresponding to all the first-stage Gain values, wherein the Gain value corresponding to the maximum value of the ENOB is the first-stage Gain 1. The first-stage gain is considered to be the first-stage actual gain at this time.

For the value of the fixed step length, the smaller the step length, the more times of calibration are needed, the more accurate the calibration is, but the longer the time is needed, the one in ten thousand is taken in the embodiment; for the times of each level of gain values from the left side and the right side of the ideal value in fixed step length, errors generally do not occur when the number of the gain values is not less than ten thousand, and the tolerance range of the errors is also large.

Similar calibration is done for the second stage Gain 2. When the second-stage Gain is calibrated, the gains of other stages except the first stage are set as ideal Gain values, the second-stage Gain2 is obtained from the left side and the right side of the ideal value in fixed step length, and each value of the second-stage Gain2 is used for calibrating the second-stage analog output V by using a calibration formula_out2And a digital output D_out2Reducing to obtain a first-stage analog output V_out1Then continuing to output V to the first-stage simulation by using the calibration formula_out1Reducing to obtain a first-stage input voltage V_in1To V pair_out1Reduction is carried out to obtain V_in1The first stage Gain1 is used to Gain1 that has been calibrated in the first step. For the restored first-stage input voltage V_in1An FFT analysis was performed to calculate ENOB. And storing ENOB obtained by calculating each value of Gain 2. And finally, analyzing ENOB corresponding to all second-stage Gain values, wherein the Gain value corresponding to the maximum value of ENOB is the second-stage Gain 2. The second-stage gain is considered to be the second-stage actual gain at this time.

For the third stage, the fourth stage and the N-1 th stage gain calibration methods are similar to the second stage gain calibration method.

When the front N-1 stage gain of the pipeline ADC is calibrated, the input signal V of the pipeline ADC is obtained by restoring_inFor V after reduction_inAnd performing FFT analysis, and calculating to obtain an effective digit total harmonic distortion spurious-free dynamic range ENOB THD SFDR so as to obtain the performance of the pipeline ADC system.

In summary, the gain calibration algorithm is used for calibrating the gain of each stage of the pipeline ADC, the method has the characteristics of high efficiency, rapidness and accuracy, can help pipeline ADC designers to rapidly and accurately obtain the design performance of the analog part of the ADC, and saves a large amount of time.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A front-end calibration method for a pipeline ADC, wherein the pipeline ADC has N stages, wherein N is a positive integer greater than 1; the pipeline ADC starts to correct from the first-stage gain until the front N-1-stage gain of the pipeline ADC is corrected in sequence, and the front end of the pipeline ADC is calibrated once;

The calibration formula is

1.5: to the first-stage input voltage V obtained by reduction_in(1)Carrying out fast Fourier transform analysis and calculation to obtain the effective digit;