CN107453756B - Front-end calibration method for pipeline ADC - Google Patents

Abstract

A front-end calibration method for pipeline ADC belongs to the technical field of analog integrated circuits. In the present invention, the calibration starts from the first stage gain of the pipeline ADC, and the front-end calibration is performed once until the first N-1 stage gains of the pipeline ADC are corrected in turn. When the first stage gain to the N-1 stage gain is obtained, the restored The error between the signal and the original signal; specifically based on the MATLAB program to search for the gain of each stage of the pipeline ADC, and then by restoring the output data of the pipeline ADC, the fast Fourier transform analysis of the restored signal is carried out. When the effective number of digits and other indicators meet the requirements, it can be considered that Gain lookup is correct, enabling pipelined ADC calibration. The invention improves the shortcomings of low calibration accuracy of traditional high-speed and high-precision pipeline ADC, has the characteristics of high efficiency, fast and accurate, and is more suitable for high-speed high-precision pipeline ADC calibration.

Description

A Front-End Calibration Method for Pipeline ADCs

technical field

The invention belongs to the field of analog integrated circuits, and in particular relates to a front-end calibration method for a pipeline ADC.

Background technique

The structure of the pipeline ADC is shown in Figure 1. The input signal is sampled by the sample and hold circuit and then sent to the pipeline unit ADC. Each unit ADC performs sampling and residual amplification alternately under the control of bi-phase non-overlapping clocks. Inside the unit ADC, the phase-sampling signal is simultaneously sampled by the multiplying digital-to-analog converter MDAC and the sub-ADC, and the sub-ADC generates a digital code Di through comparison; when the phase is maintained, Di is subtracted from the input signal by the MDAC to generate a residual, and the MDAC performs the residual difference. Amplified, the residual is amplified and sent to the next stage as the input signal of the next stage. The MDAC input and output relationship is as follows:

但随着流水线ADC向高速高精度方向发展，高速高精度流水线ADC对运放单位增益带宽积要求越来越高，而高带宽高增益运放难以实现，MDAC增益不再似等于常数

从而出现增益误差，带来非线性，进而影响ADC性能。近年来高速高精度流水线ADC往往牺牲运放增益，保证运放速度，通过校准算法确定每级增益，进而降低流水线ADC的非线性。Wherein Gain is the gain of the MDAC, A is the open-loop gain of the op amp in the MDAC, V _ref is the reference voltage, C _f is the feedback capacitor, C _k is the sampling capacitor, and C _p is the parasitic capacitance at the input end of the op amp, including the input tube parasitic Capacitances C _gs , C _gb and C _gd . The traditional MDAC can achieve the high gain requirement of the op amp in the low-speed and low-precision pipeline ADC, so that the MDAC gain Gain is approximately equal to its ideal value, that is, a constant

However, with the development of pipeline ADC in the direction of high speed and high precision, high-speed and high-precision pipeline ADC has higher and higher requirements on the unity gain bandwidth product of op amps, while high bandwidth and high gain op amps are difficult to achieve, and the MDAC gain no longer seems to be equal to a constant.

This results in gain errors, which cause non-linearity, which in turn affects ADC performance. In recent years, high-speed and high-precision pipeline ADCs often sacrifice the gain of the op amp to ensure the speed of the op amp, and determine the gain of each stage through a calibration algorithm, thereby reducing the nonlinearity of the pipeline ADC.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a front-end calibration method for pipeline ADC, using this method to calibrate the gain of N-1 stage before ADC, the calibration requires less analog quantity, the calibration speed is fast and the precision is high. The method can be used in the field of high-speed and high-precision pipeline ADC calibration.

The technical scheme of the present invention is:

A front-end calibration method for a pipeline ADC, wherein the pipeline ADC has N stages, where N is a positive integer greater than 1; the pipeline ADC starts to calibrate the gain of the first stage until the front end of the pipeline ADC is corrected in sequence. The N-1 stage gain is calibrated once for the front end;

Before calibrating, obtain the analog output V _out and digital output D _out of each stage in the pipeline ADC by simulating the pipeline ADC circuit;

Correcting the gain of the nth stage of the pipeline ADC specifically includes the following steps, where n is any positive integer from 1 to N-1:

1.1: Set the gain of the other stages except the first stage gain to the nth stage gain in the pipeline ADC to the ideal value, and the first stage gain to the n-1th stage gain is the gain after calibration;

1.2: Take the value of the n-th stage gain from the left and right sides of its ideal value in order with a fixed step size. For each n-th stage gain value Gain(n), according to the calibration formula, the n-th stage analog output V _{out (n)} and the The n-stage digital output D _out(n) is restored to obtain the n-th stage input voltage V _in(n) , and the n-th stage input voltage V _{in(n) is} the n-1-th stage analog output V _{out(n- 1)} ;

其中V_ref为流水线ADC的参考电压，C_k为流水线ADC的子级ADC内部采样电容，k∈[1，2ⁿ]；The calibration formula is

where V _ref is the reference voltage of the pipeline ADC, C _k is the internal sampling capacitor of the sub-stage ADC of the pipeline ADC, k∈[1, 2 ⁿ ];

1.3: Restore the n-1st stage digital output _Dout(n-1) obtained by analog simulation and the n-1st stage analog output Vout _(n-1) obtained in step 1.2 according to the calibration formula to obtain the n-th The first stage input voltage V _in(n-1) is the analog output V _out(n-2) of the n-2 stage, and the n-1 stage gain in the formula at this time is the n-1 stage gain after calibration;

1.4: According to step 1.2 and step 1.3, restore the first-stage input voltage V _{in(1) in} turn;

1.5: Perform fast Fourier transform analysis and calculation on the restored first-stage input voltage V _in(1) to obtain the effective number of digits;

1.6: Analyze the effective number of bits calculated by each n-th gain value Gain(n) taken in 1.2. The value of the n-th level gain corresponding to the maximum effective number of digits Gain(n) is the value after calibration. The nth stage gain.

The beneficial effects of the invention are as follows: the calibration method proposed by the invention can significantly reduce the nonlinearity of the pipeline ADC, improve the shortcomings of traditional low calibration accuracy in the high-speed and high-precision pipeline ADC, and has the characteristics of high efficiency, speed and accuracy.

Description of drawings

Fig. 1 is the structure diagram of pipeline ADC;

Figure 2 shows the first-stage quantization error model of the pipeline ADC;

Figure 3 shows the total quantization error model of the pipeline ADC;

FIG. 4 is a flow chart of calibrating the nth stage gain in a front-end calibration method for a pipeline ADC provided by the present invention.

Detailed ways

Below in conjunction with the accompanying drawings and specific embodiments, the technical solutions of the present invention are described in detail:

As shown in Figure 2, for an N-bit pipeline ADC, the signal flows into the first stage Stage1 through the sample-and-hold circuit. When the phase is sampled, the signal is sampled by the sub-ADC and MDAC at the same time, and the signal is compared by the sub-ADC to generate a digital output Di; when the phase is held, the digital code Di is restored by the DAC in the MDAC and made a difference with the input signal, and then amplified to generate a residual voltage V _res . During this process, the sub-ADC quantizes the input signal, resulting in a quantization error ε _q . Its input-output relationship is as follows:

D=V _in +ε _q (3)

V _res = Gain*ε _q (4)

In Fig. 2, the total quantization error of other stages except the first stage is represented by ε _qb , as in formula (5), when the first stage gain G _d1 =G ₁ is found after calibration by the calibration algorithm, the restored signal can be obtained The error with the original signal is

In Fig. 3, the quantization error of each stage is represented by _εqi , and i is taken from 1 to N-1. When the first to N-1th stages of gain G _di =G _i are found through calibration algorithm calibration, the restored signal can be obtained. The error with the original signal is

It can be known from formula (4) that after calibration, the closer the gain G _di of each stage of the calibrated pipeline ADC is to the actual gain G _i , the smaller the error between D _out and V _in , and the higher the calibration accuracy.

From formula (6), it can be found that the quantization error ε _q1 of the first stage has a greater influence on D _out than the quantization error ε _q2 of the second stage, and the difference of the quantization error ε _q3 of the third stage is greater than that of the quantization error ε _q2 of the second stage on D _out . , and so on for the next few levels. Therefore, we calibrate the gain of each stage starting with the calibration of the first stage gain Gain1.

The invention searches the gain of each stage of the pipeline ADC based on the MATLAB program.

确定；第一级增益Gain1每取一个值则利用校准公式将第一级模拟输出V_out1和数字输出D_out1进行还原得到第一级输入电压V_in1，对还原后的第一级输入电压V_in1进行快速傅立叶变换FFT分析，计算有效位数ENOB。对Gain1每个取值计算得到的ENOB进行保存。最终对所有第一级增益取值对应的ENOB进行分析，ENOB最大值所对应的增益值即为第一级增益Gain1。认为此时第一级增益即为第一级实际增益。When calibrating the first stage gain Gain1 of the pipeline ADC, the other stage gains are set to the ideal gain value, and the first stage gain Gain1 takes values from the left and right sides of the ideal value in fixed steps, and the ideal value of each stage gain is passed through

Determine; for each value of the first-stage gain Gain1, use the calibration formula to restore the first-stage analog output V _out1 and digital output D _out1 to obtain the first-stage input voltage V _in1 , and the restored first-stage input voltage V _in1 Perform fast Fourier transform FFT analysis to calculate the effective number of bits ENOB. Save the ENOB calculated by each value of Gain1. Finally, the ENOB corresponding to all the first-stage gain values is analyzed, and the gain value corresponding to the maximum value of ENOB is the first-stage gain Gain1. It is considered that the first-stage gain at this time is the first-stage actual gain.

For the value of the fixed step size, the smaller the step size, the more times the calibration needs to be performed, and the calibration is more accurate, but the time required is longer. This embodiment takes about 1/10,000; The number of times of taking the value with a fixed step size is generally not less than 10,000 times, and there is no error, and the tolerance range of errors is also very large.

The calibration is similar for the second stage gain Gain2. When calibrating the second stage gain, set the gain of other stages except the first stage to the ideal gain value. The second stage gain Gain2 is taken from the left and right sides of the ideal value in fixed steps. Then use the calibration formula to restore the second-stage analog output V _out2 and digital output D _out2 to obtain the first-stage analog output V _out1 , and then continue to use the calibration formula to restore the first-stage analog output V _out1 to obtain the first-stage input voltage. V _in1 , when V _out1 is restored to obtain V _in1 , the first-stage gain Gain1 is used, which is the Gain1 that has been calibrated in the first step. Perform FFT analysis on the restored first-stage input voltage V _in1 to calculate ENOB. Save the ENOB calculated for each value of Gain2. Finally, the ENOB corresponding to all second-stage gain values is analyzed, and the gain value corresponding to the maximum value of ENOB is the second-stage gain Gain2. It is considered that the second stage gain is the second stage actual gain at this time.

For the third stage, the fourth stage and the N-1th stage gain calibration method is similar to the second stage gain calibration method.

After calibrating the gain of the first N-1 stages of the pipeline ADC, restore the input signal V _in of the pipeline ADC, perform FFT analysis on the restored V _in , and calculate the effective number of bits and the total harmonic distortion free dynamic range ENOB THD SFDR , the performance of the pipeline ADC system can be known.

To sum up, using the gain calibration algorithm to calibrate the gain of each stage of the pipeline ADC is efficient, fast and accurate, which can help pipeline ADC designers to quickly and accurately obtain the design performance of the analog part of the ADC, saving a lot of time.

Those skilled in the art can make various other specific modifications and combinations without departing from the essence of the present invention according to the technical teaching disclosed in the present invention, and these modifications and combinations still fall within the protection scope of the present invention.

Claims (1)

1. A front-end calibration method for pipeline ADC, characterized in that the pipeline ADC has N stages, wherein N is a positive integer greater than 1; The gain of the first N-1 stages of the pipeline ADC is calibrated once for the front end; Before calibrating, obtain the analog output V _out and digital output D _out of each stage in the pipeline ADC by simulating the pipeline ADC circuit; Correcting the gain of the nth stage of the pipeline ADC specifically includes the following steps, where n is any positive integer from 1 to N-1: 1.1: Set the gain of the other stages except the first stage gain to the nth stage gain in the pipeline ADC to the ideal value, and the first stage gain to the n-1th stage gain is the gain after calibration; 1.2: Take the value of the n-th stage gain from the left and right sides of its ideal value in order with a fixed step size. For each n-th stage gain value Gain(n), according to the calibration formula, the n-th stage analog output V _{out (n)} and the The n-stage digital output D _out(n) is restored to obtain the n-th stage input voltage V _in(n) , and the n-th stage input voltage V _{in(n) is} the n-1-th stage analog output V _{out(n- 1)} ; The calibration formula is

where V _ref is the reference voltage of the pipeline ADC, C _k is the internal sampling capacitor of the sub-stage ADC of the pipeline ADC, k∈[1, 2 ⁿ ]; 1.3: Restore the n-1st stage digital output _Dout(n-1) obtained by analog simulation and the n-1st stage analog output Vout _(n-1) obtained in step 1.2 according to the calibration formula to obtain the n-th The first stage input voltage V _in(n-1) is the analog output V _out(n-2) of the n-2 stage, and the n-1 stage gain in the formula at this time is the n-1 stage gain after calibration; 1.4: According to step 1.2 and step 1.3, restore the first-stage input voltage V _{in(1) in} turn; 1.5: Perform fast Fourier transform analysis and calculation on the restored first-stage input voltage V _in(1) to obtain the effective number of digits; 1.6: Analyze the effective number of bits calculated by each n-th gain value Gain(n) taken in 1.2. The value of the n-th level gain corresponding to the maximum effective number of digits Gain(n) is the value after calibration. The nth stage gain.

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