CN104917527A - Capacitance mismatch calibrating circuit and calibrating method applied to single-end SAR ADC - Google Patents

Abstract

The invention discloses a capacitance mismatch calibrating circuit and calibrating method applied to a single-end SAR ADC (Successive Approximation Analog-to-Digital Converter). By using the method, error caused by capacitance mismatch of the SAR ADC can be calibrated. According to the method, only two pairs of redundant capacitance need to be inserted in an analog domain for compensation of capacitance mismatch in a digital domain. A binary capacitance DAC (Digital-to-Analog Converter) containing two pairs of redundant dot capacitance includes a segmentation binary capacitance DAC and redundant capacitance Cjr+, Cjr- inserted to the lowest bit of aN MSB segment of a segmentation capacitance, and redundant capacitance Cqr+, Cqr- inserted to an LSB segment. A redundant bit calculation module adds the inserted redundant bits to other normal bits and obtains N-bit valid output. A capacitance mismatch calibrating module performs compensation to capacitance mismatch on the output result. Compared with the traditional SAR ADC structure, only two pairs of redundant capacitance are added. The calculation of mismatch compensation is performed in the digital domain, so that the layout size and analog circuit complexity is reduced.

Description

Be applied to capacitor mismatch calibration circuit and the calibration steps thereof of single-ended SAR ADC

Technical field

The present invention relates to a kind of mismatch calibration method being applied to single-ended SAR ADC electric capacity, belong to SAR ADC collimation technique.

Background technology

High accuracy SAR ADC (analog-digital converter of successive approximation register type) is due to the restriction of its capacitance mismatch, need to adopt larger electric capacity to meet the requirement of electric capacity matching degree, particularly precision is higher than the situation of more than 12-bit, generally needs can solve by capacitor mismatch calibration the impact that capacitance mismatch brings.But adopting large DAC (digital analog converter) electric capacity, thus settling time is restricted, and power consumption also can improve.The electric capacity of calibration steps traditional in addition to each needs calibration requires an independent calibration DAC array, although calibration DAC array only needs about 5bit, but once need the electric capacity of calibration more, the electric capacity of its calibration DAC array just may be suitable with the area shared by DAC array own, and this directly results in the raising of chip cost.

Although nonbinary electric capacity DAC array in recent years can realize capacitor mismatch calibration, but owing to have employed nonbinary electric capacity DAC array, the matching degree of its domain can be obviously poor than binary capacitor DAC array, and owing to will store the weight of each electric capacity in Digital Logic, its complexity also promotes a lot.

Summary of the invention

Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind of single-ended SAR ADC Capacitor Mismatch Calibration, utilizes SAR ADC binary system redundant capacitor itself to carry out capacitor mismatch calibration, to improve the precision of SAR ADC.

Technical scheme: for achieving the above object, the technical solution used in the present invention is: the capacitor mismatch calibration circuit being applied to single-ended SAR ADC, comprises binary system redundancy calibration capacitance array, comparator, single-ended SAR logical circuit, redundant digit computing module, capacitor mismatch calibration module;

Described binary system redundancy calibration capacitance array comprises segmentation binary capacitor array and at least two pairs of redundant capacitor, and described two pairs of redundant capacitor comprise and are inserted in segmentation binary capacitor array MSB section lowest order C _jother redundant capacitor C _jr+and C _jr-, and be inserted in arbitrary C in segmentation binary capacitor array LSB section _qother redundant capacitor C _qr+and C _qr-; Wherein, redundant capacitor C _jr+, C _jr-with C _jcapacitance identical, redundant capacitor C _qr+, C _qr-with C _qcapacitance is identical; The lowest order of described segmentation binary capacitor array is inserted with C _d1and C _d2, C _d1and C _d2capacitance be respectively specific capacitance C _u1/2 and 1/4; Namely the MSB section of the sectional capacitance of described binary system redundancy calibration capacitance array is C _n-1to C _jsection, comprises redundant capacitor C _jr+and C _jr-; The LSB section of the sectional capacitance of binary system redundancy calibration capacitance array is C _j-1to C ₀section, comprises redundant capacitor C _qr+, C _qr-and C _d1and C _d2; Wherein, N is the total bit of binary system redundancy calibration capacitance array;

The sampling capacitance C of described binary system redundancy calibration capacitance array _sfor C _n-1to C _j, comprise one and C _jthe electric capacity C that size is identical _j0; That is:

$C_S=\underset{k=j}{\overset{N-1}{\Σ}}{C}_k+C_{j0};$

The redundant code of two pairs of redundant capacitor is joined source code D by described redundant digit computing module _ain, obtain the output code D through overcompensation _b, described source code D _adigital code for each output of binary system redundancy calibration capacitance array:

$D_B=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{A,k}\×2^k+\underset{k=j,q}{\Σ}(s_{k+}+s_k-)2^k;$

Wherein s _k+, s _k-symbol for redundant code:

s _k+＝D _A,k×D _A,kr, $s_{k-}=-\stackrel{\‾}{D_{A,k}}\×\stackrel{\‾}{D_{A,kr}};$

Described capacitor mismatch calibration module carries out the compensation of capacitance mismatch to Output rusults.

The present invention is applied to the Capacitor Mismatch Calibration of the capacitor mismatch calibration circuit realiration of single-ended SAR ADC, and concrete steps are as follows:

Step one, acquisition unbalance of system error codes: disconnect all sampling switchs in sample phase, by the sampling capacitance C of binary system redundancy calibration capacitance array _slower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, keep sampling capacitance C _slower step be connected in reference level Vref, the conversion of single-ended SAR is from C _j-1start, and by LSB section capacitor array latter two small capacitances C _d1and C _d2also for the conversion of SAR, change the digital output code through overcompensation obtained and be designated as D Δ; By aforesaid operations repeated several times, and make mean value, obtain unbalance of system error codes

Step 2, obtain the error codes of each electric capacity: the lowest order electric capacity of the MSB section of calibrating from needing electric capacity, and the redundancy calibration capacitance identical with MSB section lowest order weight starts, and carries out electric capacity calibration to a MSB section high position; Namely need the MSB section electric capacity calibrated respectively from C _jto C _n-1, wherein C _jfor needing the minimum capacity in capacitor mismatch calibration binary system redundancy calibration capacitance array, according to the distribution of redundant capacitor, C _jthere is a pair redundant capacitor on side, is respectively C _jr+and C _jr-; The process of calibration: disconnect all sampling switchs, by C in sample phase _ilower step be connected to reference level Vref, wherein C _i∈ (C _n-1..., C _j, C _jr+, C _jr-), the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, by C _ilower step be connected to gnd, the conversion of single-ended SAR is from C _i-1start, until small capacitances C _d1and C _d2eOC; By C _n-1..., C _j, C _jr+, C _jr-several times conversion is carried out in each electric capacity calibration conversion, and averages to it, obtains the error codes of each electric capacity

Concrete, at calibration C _j, C _jr+and C _jr-during electric capacity, by the output valve D through overcompensation obtained _bdeduct the idea output of this conversion, and deduct unbalance of system error codes obtain this capacitance mismatch compensation codes D δ _i, that is:

wherein D δ _ifor D δ _j, D δ _jr+or D δ _jr-;

When carrying out C _j+1to C _n-1time capacitance error is measured, not only need the output valve D through overcompensation that will obtain _bdeduct the idea output of this conversion, and deduct unbalance of system error codes also need cumulative upper this output to be 1 capacitance mismatch value in place, obtain this capacitance mismatch compensation codes D δ _i, that is:

${\mathrm{D\δ}}_i=(\underset{k=0}{\overset{i-1}{\Σ}}{D}_{B,k}\×2^k-2^i)-\stackrel{\‾}{D\mathrm{\Δ}}+\underset{k=j}{\overset{i-1}{\Σ}}{D}_{A,k}\×{\mathrm{D\δ}}_k+(s_{j+}\×{\mathrm{D\δ}}_{jr+}+s_{j-}\×{\mathrm{D\δ}}_{jr-}),$ Wherein D δ _i=D δ _n-1~ D δ _j+1

By each measurement needing the electric capacity compensated to carry out several times capacitance error, and get its mean value, obtain the error codes of each electric capacity, be designated as

Step 3, background calibration: by the output valve D through overcompensation obtained _b, add the error codes of this conversion its result is designated as D _c:

$D_C=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k+\stackrel{\‾}{{\mathrm{D\δ}}_{tot}};$

Wherein, the error codes of this conversion be expressed as:

$\stackrel{\‾}{{\mathrm{D\δ}}_{tot}}=\underset{k=j}{\overset{N-1}{\Σ}}{D}_{A,k}\×\stackrel{\‾}{{\mathrm{D\δ}}_k}+(s_{j+}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr+}}+s_{j-}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr-}});$

The overall error of sampling capacitance is

$\stackrel{\‾}{{\mathrm{D\δ}}_S}=\underset{k=j}{\overset{N-1}{\Σ}}\stackrel{\‾}{{\mathrm{D\δ}}_k}$

Because the compensation codes of the gain error that sampling capacitance causes is:

$D_{comp}=-(\stackrel{\‾}{{\mathrm{D\δ}}_S}\×\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}{2}^k)\÷2^N$

I.e. D _cadd that gain compensation code deducts mismatch error again and can obtain final Output rusults D _fin:

$D_{fin}=D_C+D_{comp}-\stackrel{\‾}{D\mathrm{\Δ}}.$

Further, step one and the several times described in step 2 are 16 times.

Beneficial effect: the invention provides the binary capacitor array redundancy calibration steps being applied to single-ended SAR ADC, relative to prior art, tool has the following advantages:

1, binary system redundancy calibration capacitance array itself is used to carry out electric capacity calibration, relative to traditional SAR ADC Capacitor Mismatch Calibration, do not need extra calibration capacitance array, thus the electric capacity that additional calibration capacitor array is corresponding is saved, switch, and control logic, thus can save power consumption and area than traditional capacitance mismatch calibration.

2, the present invention propose single-ended SAR ADC binary capacitor array calibration steps calibration range be about ± (2 ^j+ 2 ^q) LSB, calibration range is larger than traditional SAR ADC Capacitor Mismatch Calibration.

3, the single-ended SAR ADC binary capacitor array calibration steps of the present invention's proposition, only needs the Digital Logic adding capacitor mismatch calibration on binary capacitor array redundancy calibration SAR ADC, does not change the simulation part of SAR ADC, be easy to realize.

4., because the method is based on redundancy calibration, thus incessantly can calibrate capacitance mismatch, the dynamic error in transfer process can also be calibrated.

Accompanying drawing explanation

Fig. 1 is single-ended SAR ADC redundancy calibration operation process.

Fig. 2 is that the output digital code of single-ended SAR ADC calculates schematic diagram.

Fig. 3 is the structure chart of the present invention single-ended SAR ADC capacitor mismatch calibration.

Fig. 4 is redundant capacitor distribution and the digital output code thereof of the present invention single-ended SAR ADC capacitor mismatch calibration.

Fig. 5 is the present invention single-ended SAR ADC capacitor mismatch calibration operational flowchart.

Fig. 6 is the 14-bit single-ended SAR ADC output spectrum figure of the present invention single-ended SAR ADC capacitor mismatch calibration.

Embodiment

Below in conjunction with accompanying drawing, the present invention is further described.

The present invention proposes based on single-ended 14bit binary system redundancy calibration capacitance array, and the calibration of capacitor array is carried out thus the precision of raising ADC to it.Owing to the present invention is based on redundant capacitor calibration.Thus first the redundant capacitor calibration of single-ended SAR ADC is described.

Fig. 1 is single-ended SAR ADC redundancy calibration operation process.As can be seen from the figure, the operating process of its nonredundancy position and normal single-ended SAR ADC are identical.And when being transformed into redundant digit C _jr+and C _jr-time, first to the C before redundant digit _jadjudicate, if bj is 1, then enter the branch road just compensating i.e. Cjr+; If bj is 0, then enter the branch road of negative compensation and Cjr-.Just compensate branch road when entering, its operating process is identical with normal position transfer process, and changing branch road is operate electric capacity Cjr+.And when entering the negative branch road that compensates, and first step under electric capacity is connect high level unlike normal conversion, but directly enter judgement.(specifically seeing that the patent No. is the binary capacitor array being applied to single-ended SAR ADC and the redundancy calibration steps thereof of 201510069640.2).

Fig. 2 is that the output digital code of single-ended SAR ADC calculates schematic diagram.Suppose at C in figure _ja redundant digit is inserted on side, position, namely inserts redundant capacitor C _jr+, C _jr-, its output output code produced is b _jr.Redundant digit is being calculated the formula of output digital code as shown in Figure 2.

The structure chart of Fig. 3 the present invention single-ended SAR ADC capacitor mismatch calibration.As can be seen from the figure, the system configuration of this calibration steps is based on binary system DAC capacitor array SAR ADC.The binary system DAC capacitor array basis of traditional structure adds redundant capacitor.Wherein a pair redundant capacitor C _jr+, C _jr-be positioned at the tail end of sectional capacitance MSB array, another is to redundant capacitor C _qr+, C _qr-be arranged in sectional capacitance LSB array.This calibration steps only adds these two pairs of redundant capacitor and corresponding switch at analog domain, thus can be easy to improve to existing structure.Redundant digit process and capacitor mismatch calibration is added at numeric field.Wherein, redundant digit process is the source code D that will export _aarrange, obtain representing the output digital code without electric capacity calibration.Its computational process is

$D_B=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{A,k}\×2^k+\underset{k=j,q}{\Σ}(s_{k+}+s_{k-})2^k$

Fig. 4 is redundant capacitor distribution and the digital output code thereof of the present invention single-ended SAR ADC capacitor mismatch calibration.As can be seen from the figure, the output original number character code D of electric capacity and its correspondence _abetween relation.Wherein after the minimum capacity of capacitor array, insert two electric capacity, C _d1and C _d2its capacitance is respectively specific capacitance C _u1/2 and 1/4.Adding of these two electric capacity is loss of significance in process in order to reduce electric capacity calibration caused by quantizing noise.The sampling capacitance C of described binary system redundancy calibration capacitance array _sfor C _n-1to C _j, comprise one and C _jthe electric capacity C that size is identical _j0; That is:

$C_S=\underset{k=j}{\overset{N-1}{\Σ}}{C}_k+C_{j0}.$

Fig. 5 is the flow process of proposition single-ended SAR ADC capacitance error calibration of the present invention.

The source code that ADC exports is D _a, redundant code is joined in source code, obtains the output code D through overcompensation _b:

$D_B=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{A,k}\×2^k+\underset{k=j,q}{\Σ}(s_{k+}+s_{k-})2^k$

Wherein s _k+, s _k-for the symbol of redundant digit, formula below can be passed through and obtain:

s _k+＝D _A,k×D _A,kr, $s_{k-}=-\stackrel{\‾}{D_{A,k}}\×\stackrel{\‾}{D_{A,kr}}$

Utilize binary system redundancy calibration capacitance array calibration itself capacitance error and without the need at increase extra capacitor array or extra calibration device.Capacitor array calibration steps concrete steps are as follows:

Step one, acquisition unbalance of system error codes: disconnect all sampling switchs in sample phase, by the sampling capacitance C of binary system redundancy calibration capacitance array _slower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, keep sampling capacitance C _slower step be connected in reference level Vref, the conversion of single-ended SAR is from C _j-1start, and by LSB section capacitor array latter two small capacitances C _d1and C _d2also for the conversion of SAR, change the digital output code through overcompensation obtained and be designated as D Δ; By aforesaid operations repeated several times, and make mean value, obtain unbalance of system error codes

Step 2, obtain the error codes of each electric capacity: the lowest order electric capacity of the MSB section of calibrating from needing electric capacity, and the redundancy calibration capacitance identical with MSB section lowest order weight starts, and carries out electric capacity calibration to a MSB section high position; Namely need the MSB section electric capacity calibrated respectively from C _jto C _n-1, wherein C _jfor needing the minimum capacity in capacitor mismatch calibration binary system redundancy calibration capacitance array, according to the distribution of redundant capacitor, C _jthere is a pair redundant capacitor on side, is respectively C _jr+and C _jr-; The process of calibration: disconnect all sampling switchs, by C in sample phase _ilower step be connected to reference level Vref, wherein C _i∈ (C _n-1..., C _j, C _jr+, C _jr-), the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, by C _ilower step be connected to gnd, the conversion of single-ended SAR is from C _i-1start, until small capacitances C _d1and C _d2eOC; By C _n-1..., C _j, C _jr+, C _jr-several times conversion is carried out in each electric capacity calibration conversion, and averages to it, obtains the error codes of each electric capacity

Concrete, at calibration C _j, C _jr+and C _jr-during electric capacity, by the output valve D through overcompensation obtained _bdeduct the idea output of this conversion, and deduct unbalance of system error codes obtain this capacitance mismatch compensation codes D δ _i, that is:

${\mathrm{D\δ}}_i=(\underset{k=0}{\overset{i-1}{\Σ}}{D}_{B,k}\×2^k-2^i)-\stackrel{\‾}{D\mathrm{\Δ}},$ Wherein D δ _ifor D δ _j, D δ _jr+or D δ _jr-;

When carrying out C _j+1to C _n-1time capacitance error is measured, not only need the output valve D through overcompensation that will obtain _bdeduct the idea output of this conversion, and deduct unbalance of system error codes also need cumulative upper this output to be 1 capacitance mismatch value in place, obtain this capacitance mismatch compensation codes D δ _i, that is:

${\mathrm{D\δ}}_i=(\underset{k=0}{\overset{i-1}{\Σ}}{D}_{B,k}\×2^k-2^i)-\stackrel{\‾}{D\mathrm{\Δ}}+\underset{k=j}{\overset{i-1}{\Σ}}{D}_{A,k}\×{\mathrm{D\δ}}_k+(s_{j+}\×{\mathrm{D\δ}}_{jr+}+s_{j-}\×{\mathrm{D\δ}}_{jr-}),$ Wherein D δ _i=D δ _n-1~ D δ _j+1

By each measurement needing the electric capacity compensated to carry out several times capacitance error, and get its mean value, obtain the error codes of each electric capacity, be designated as

Step 3, background calibration: after two step operations terminate, just obtain the error amount of each electric capacity needing calibration above, next only need, in normal conversion, output code is deducted corresponding error amount.Be specially normal single-ended conversion, from C _n-1to C ₀, the digital output code through redundancy compensation obtained is D _b, it is carried out to the compensation of electric capacity adaptation.By the digital output code D through redundancy compensation _badd the mismatch compensation code of this conversion its result is designated as D _c:

$D_C=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k+\stackrel{\‾}{{\mathrm{D\δ}}_{tot}};$

Wherein, the error codes of this conversion be expressed as:

$\stackrel{\‾}{{\mathrm{D\δ}}_{tot}}=\underset{k=j}{\overset{N-1}{\Σ}}{D}_{A,k}\×\stackrel{\‾}{{\mathrm{D\δ}}_k}+(s_{j+}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr+}}+s_{j-}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr-}});$

Because sampling capacitance exists capacitance mismatch, D can be caused _cexport with ideal and there is gain error, thus need to compensate gain error further.The overall error of sampling capacitance is

$\stackrel{\‾}{{\mathrm{D\δ}}_S}=\underset{k=j}{\overset{N-1}{\Σ}}\stackrel{\‾}{{\mathrm{D\δ}}_k}$

Thus, the compensation codes of gain is:

$D_{comp}=-(\stackrel{\‾}{{\mathrm{D\δ}}_S}\×\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}{2}^k)\÷2^N$

By D _cadd that gain compensation code deducts offset error again and can obtain final Output rusults D _fin:

$D_{fin}=D_C+D_{comp}-\stackrel{\‾}{D\mathrm{\Δ}}.$

Fig. 6 is that the single-ended SAR ADC of 14-bit of the present invention single-ended SAR ADC capacitor mismatch calibration calibrates design sketch.Wherein in figure, Part I is without electric capacity calibration (without calibration), and the 14-bit that there is dynamic error single-ended SARADC output spectrum figure.Its sinad ratio (SNDR) and Spurious Free Dynamic Range (SFDR) are respectively 40.7dB and 54.9dBc.In figure, Part II is after redundancy calibration and the capacitor mismatch calibration based on redundancy calibration (with dual-calibration), and its sinad ratio and Spurious Free Dynamic Range have brought up to 82.9dB and 96dBc respectively.Wherein: normalized frequency represents normalized frequency, and magnitude represents size.

The foregoing is only better embodiment of the present invention; protection scope of the present invention is not limited with above-mentioned execution mode; in every case those of ordinary skill in the art modify or change according to the equivalence that disclosed content is done, and all should include in the protection range recorded in claims.

Claims (3)

1. be applied to the capacitor mismatch calibration circuit of single-ended SAR ADC, it is characterized in that: comprise binary system redundancy calibration capacitance array, comparator, single-ended SAR logical circuit, redundant digit computing module, capacitor mismatch calibration module;

Described binary system redundancy calibration capacitance array comprises segmentation binary capacitor array and at least two pairs of redundant capacitor, and described two pairs of redundant capacitor comprise and are inserted in segmentation binary capacitor array MSB section lowest order C _jother redundant capacitor C _jr+and C _jr-, and be inserted in arbitrary C in segmentation binary capacitor array LSB section _qother redundant capacitor C _qr+and C _qr-; Wherein, redundant capacitor C _jr+, C _jr-with C _jcapacitance identical, redundant capacitor C _qr+, C _qr-with C _qcapacitance is identical; The lowest order of described segmentation binary capacitor array is inserted with C _d1and C _d2, C _d1and C _d2capacitance be respectively specific capacitance C _u1/2 and 1/4; Namely the MSB section of the sectional capacitance of described binary system redundancy calibration capacitance array is C _n-1to C _jsection, comprises redundant capacitor C _jr+and C _jr-; The LSB section of the sectional capacitance of binary system redundancy calibration capacitance array is C _j-1to C ₀section, comprises redundant capacitor C _qr+, C _qr-and C _d1and C _d2; Wherein, N is the total bit of binary system redundancy calibration capacitance array;

The sampling capacitance C of described binary system redundancy calibration capacitance array _sfor C _n-1to C _j, comprise one and C _jthe electric capacity C that size is identical _j0; That is:

$C_S=\underset{k=j}{\overset{N-1}{\Σ}}{C}_k+C_{j0};$

The redundant code of two pairs of redundant capacitor is joined source code D by described redundant digit computing module _ain, obtain the output code D through overcompensation _b, described source code D _adigital code for each output of binary system redundancy calibration capacitance array:

$D_B=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{A,k}\×2^k+\underset{k=j,q}{\Σ}(s_{k+}+s_{k-})2^k;$

Wherein s _k+, s _k-symbol for redundant code:

s _k+＝D _A,k×D _A,kr, $s_{k-}=-\stackrel{\‾}{D_{A,k}}\×\stackrel{\‾}{D_{A,kr}};$

Described capacitor mismatch calibration module carries out the compensation of capacitance mismatch to Output rusults.

2. be applied to the Capacitor Mismatch Calibration of the capacitor mismatch calibration circuit realiration of single-ended SAR ADC according to claim 1, it is characterized in that: concrete steps are as follows:

Step one, acquisition unbalance of system error codes: disconnect all sampling switchs in sample phase, by the sampling capacitance C of binary system redundancy calibration capacitance array _slower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, keep sampling capacitance C _slower step be connected in reference level Vref, the conversion of single-ended SAR is from C _j-1start, and by LSB section capacitor array latter two small capacitances C _d1and C _d2also for the conversion of SAR, change the digital output code through overcompensation obtained and be designated as D Δ; By aforesaid operations repeated several times, and make mean value, obtain unbalance of system error codes

Step 2, obtain the error codes of each electric capacity: the lowest order electric capacity of the MSB section of calibrating from needing electric capacity, and the redundancy calibration capacitance identical with MSB section lowest order weight starts, and carries out electric capacity calibration to a MSB section high position; Namely need the MSB section electric capacity calibrated respectively from C _jto C _n-1, wherein C _jfor needing the minimum capacity in capacitor mismatch calibration binary system redundancy calibration capacitance array, according to the distribution of redundant capacitor, C _jthere is a pair redundant capacitor on side, is respectively C _jr+and C _jr-; The process of calibration: disconnect all sampling switchs, by C in sample phase _ilower step be connected to reference level Vref, wherein C _i∈ (C _n-1..., C _j, C _jr+, C _jr-), the bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator; After sampling terminates, by C _ilower step be connected to gnd, the conversion of single-ended SAR is from C _i-1start, until small capacitances C _d1and C _d2eOC; By C _n-1..., C _j, C _jr+, C _jr-several times conversion is carried out in each electric capacity calibration conversion, and averages to it, obtains the error codes of each electric capacity

Concrete, at calibration C _j, C _jr+and C _jr-during electric capacity, by the output valve D through overcompensation obtained _bdeduct the idea output of this conversion, and deduct unbalance of system error codes obtain this capacitance mismatch compensation codes D δ _i, that is:

${\mathrm{D\δ}}_i=\left(\underset{k=0}{\overset{i-1}{\Σ}}{D}_{B,k}\×2^k-2^i\right)-\stackrel{\‾}{D\mathrm{\Δ}},$ Wherein D δ _ifor D δ _j, D δ _jr+or D δ _jr-;

When carrying out C _j+1to C _n-1time capacitance error is measured, not only need the output valve D through overcompensation that will obtain _bdeduct the idea output of this conversion, and deduct unbalance of system error codes also need cumulative upper this output to be 1 capacitance mismatch value in place, obtain this capacitance mismatch compensation codes D δ _i, that is:

${\mathrm{D\δ}}_i=\left(\underset{k=0}{\overset{i-1}{\Σ}}{D}_{B,k}\×2^k-2^i\right)-\stackrel{\‾}{D\mathrm{\Δ}}+\underset{k=j}{\overset{i-1}{\Σ}}{D}_{A,k}\×{\mathrm{D\δ}}_k+(s_{j+}\×{\mathrm{D\δ}}_{jr+}+s_{j-}\×{\mathrm{D\δ}}_{jr-}),$ Wherein D δ _i=D δ _n-1~ D δ _j+1

By each measurement needing the electric capacity compensated to carry out several times capacitance error, and get its mean value, obtain the error codes of each electric capacity, be designated as

Step 3, background calibration: by the output valve D through overcompensation obtained _b, add the error codes of this conversion its result is designated as D _c:

$D_C=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}=\underset{k=0}{\overset{N-1}{\Σ}}{D}_{B,k}\×2^k+\stackrel{\‾}{{\mathrm{D\δ}}_{tot}};$

Wherein, the error codes of this conversion be expressed as:

$\stackrel{\‾}{{\mathrm{D\δ}}_{tot}}=\underset{k=j}{\overset{N-1}{\Σ}}{D}_{A,k}\×\stackrel{\‾}{{\mathrm{D\δ}}_k}+(s_{j+}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr+}}+s_{j-}\×\stackrel{\‾}{{\mathrm{D\δ}}_{jr-}});$

The overall error of sampling capacitance is

$\stackrel{\‾}{{\mathrm{D\δ}}_S}=\underset{k=j}{\overset{N-1}{\Σ}}\stackrel{\‾}{{\mathrm{D\δ}}_k}$

Because the compensation codes of the gain error that sampling capacitance causes is:

$D_{comp}=-\left(\stackrel{\‾}{{\mathrm{D\δ}}_S}\×\underset{k=0}{\overset{N-1}{\Σ}}{D}_{C,k}{2}^k\right)\÷2^N$

I.e. D _cadd that gain compensation code deducts mismatch error again and can obtain final Output rusults D _fin:

$D_{fin}=D_C+D_{comp}-\stackrel{\‾}{D\mathrm{\Δ}}.$

3. be applied to the Capacitor Mismatch Calibration of the capacitor mismatch calibration circuit realiration of single-ended SAR ADC according to claim 2, it is characterized in that: step one and the several times described in step 2 are 16 times.