CN104917527B - Capacitor mismatch calibration circuit and its calibration method applied to single-ended SAR ADC - Google Patents
Capacitor mismatch calibration circuit and its calibration method applied to single-ended SAR ADC Download PDFInfo
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- CN104917527B CN104917527B CN201510374237.0A CN201510374237A CN104917527B CN 104917527 B CN104917527 B CN 104917527B CN 201510374237 A CN201510374237 A CN 201510374237A CN 104917527 B CN104917527 B CN 104917527B
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Abstract
The invention discloses one kind to be applied to single-ended SAR ADC Capacitor Mismatch Calibrations, can calibrate the error caused by SAR ADC capacitance mismatch.This method is only needed to insert two pairs of redundant capacitors in analog domain, and the compensation of capacitance mismatch is carried out in numeric field.Binary capacitor DAC wherein containing two pairs of redundant points electric capacity includes segmentation binary capacitor DAC and is inserted in sectional capacitance MSB section lowest orders CjRedundant capacitor Cjr+,Cjr‑, and the redundant capacitor C being inserted in LSB sectionsqr+,Cqr‑.Redundant digit computing module adds the redundant digit inserted effective output that N bit are calculated as with other normal positions.Capacitor mismatch calibration module carries out the compensation of capacitance mismatch to output result.The calibration method only adds two pairs of redundant capacitors in traditional SAR ADC structures, and the calculating of mismatch compensation is carried out in the digital domain, so as to reduce chip area, and analog circuit complexity.
Description
Technical field
The present invention relates to a kind of mismatch calibration method applied to single-ended SAR ADC electric capacity, belongs to SAR ADC calibration skills
Art.
Background technology
High-precision SAR ADC (analog-digital converter of successive approximation register type) due to the limitation of its capacitance mismatch,
The situation for needing the requirement for meeting electric capacity matching degree using larger electric capacity, particularly precision to be higher than more than 12-bit, typically
Need can solve influence caused by capacitance mismatch by capacitor mismatch calibration.But use big DAC (digital-to-analogue conversions
Device) electric capacity, settling time is thus restricted, and power consumption can also improve.Traditional calibration method needs to each in addition
The electric capacity of calibration requires an individually calibration DAC array, although calibration DAC arrays only need 5bit or so, once
Need the electric capacity calibrated more, its calibrate the electric capacity of DAC arrays can be suitable with the shared area of DAC array itself, this
It directly results in the raising of chip cost.
Although nonbinary electric capacity DAC arrays in recent years can realize capacitor mismatch calibration, as a result of non-
Binary capacitor DAC arrays, the matching degree of its domain can be substantially poorer than binary capacitor DAC arrays, and in Digital Logic
Due to store the weight of each electric capacity, its complexity is also lifted a lot.
The content of the invention
Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention provides a kind of single-ended SAR ADC electric capacity and lost
With calibration method, capacitor mismatch calibration is carried out in itself using SAR ADC binary systems redundant capacitors, to improve SAR ADC precision.
Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：Electricity applied to single-ended SAR ADC
Hold mismatch calibration circuit, including binary system redundancy calibration capacitance array, comparator, single-ended SAR logic circuits, redundant digit calculating mould
Block, capacitor mismatch calibration module；
The binary system redundancy calibration capacitance array includes segmentation binary capacitor array and at least two pairs of redundant capacitors,
Two pairs of redundant capacitors include being inserted in segmentation binary capacitor array MSB section lowest orders CjOther redundant capacitor Cjr+With
Cjr-, and it is inserted in any bit C in segmentation binary capacitor array LSB sectionsqOther redundant capacitor Cqr+And Cqr-；Wherein, redundancy
Electric capacity Cjr+、Cjr- and CjCapacitance it is identical, redundant capacitor Cqr+、Cqr- and CqCapacitance is identical；The segmentation binary capacitor
The lowest order of array is inserted with Cd1And Cd2,Cd1And Cd2Capacitance be respectively specific capacitance Cu1/2 and 1/4；I.e. described two
The MSB sections of the sectional capacitance of system redundancy calibration capacitance array are CN-1To CjSection, including redundant capacitor Cjr+And Cjr-；Two enter
The LSB sections of the sectional capacitance of redundancy calibration capacitance array processed are Cj-1To C0Section, including redundant capacitor Cqr+、Cqr- and Cd1And Cd2
's；Wherein, N is the total bit of binary system redundancy calibration capacitance array；
The sampling capacitance C of the binary system redundancy calibration capacitance arraySFor CN-1To Cj, including one and CjSize identical
Electric capacity Cj0；I.e.：
The redundant code of two pairs of redundant capacitors is added to source code D by the redundant digit computing moduleAIn, obtain through overcompensation
Output valve DB, the source code DAFor the digital code of each output of binary system redundancy calibration capacitance array：
Wherein sk+, sk-For the symbol of redundant code：
The capacitor mismatch calibration module carries out the compensation of capacitance mismatch to output result.
Capacitor Mismatch Calibration of the present invention applied to single-ended SAR ADC capacitor mismatch calibration circuit realiration, specifically
Step is as follows：
Step 1: obtain unbalance of system error codes：All sampling switch are disconnected in sample phase, binary system redundancy is calibrated
The sampling capacitance C of capacitor arraySLower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, compares
Two inputs of device are all connected to the common mode electrical level Vcm of comparator；After sampling terminates, sampling capacitance C is keptSLower step
It is connected in reference level Vref, single-ended SAR conversion is from Cj-1Start, and by LSB sections capacitor array most latter two small capacitances Cd1
And Cd2SAR conversion is also used for, the digital output code through overcompensation obtained by changing is designated as D △；If aforesaid operations are repeated
Dry time, and make average value, obtain unbalance of system error codes
Step 2: obtain the error codes of each electric capacity：From the lowest order electric capacity for the MSB sections for needing electric capacity calibration, Yi Jiyu
MSB section lowest order weight identical redundancy calibration capacitances start, and electric capacity calibration is carried out to MSB sections are high-order；Need the MSB calibrated
Section electric capacity is respectively from CjTo CN-1, wherein CjTo need the minimum electricity in the binary system redundancy calibration capacitance array of capacitor mismatch calibration
Hold, according to the distribution of redundant capacitor, CjThere are a pair of redundant capacitors, respectively C in sidejr+And Cjr-；The process of calibration：In sampling rank
Section disconnects all sampling switch, by CiLower step be connected to reference level Vref, wherein Ci∈(CN-1,…,Cj,Cjr+,Cjr-),
The bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator；Sampling
After end, by CiLower step be connected to gnd, single-ended SAR conversion is from Ci-1Start, until small capacitances Cd1And Cd2Change-over knot
Beam；By CN-1,…,Cj,Cjr+,Cjr- each electric capacity calibration conversion is changed several times, and it is averaged, and is obtained each
The error codes of electric capacity
Specifically, in calibration Cj、Cjr+And CjrDuring-electric capacity, the output valve D through overcompensation that will obtainBSubtract this conversion
Idea output, and subtract unbalance of system error codesObtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δiFor D δj、Dδjr+Or D δjr-；
As progress Cj+1To CN-1When capacitance error measures, the output valve D through overcompensation that will be obtained not only is neededBSubtract
The idea output of this conversion is gone, and subtracts unbalance of system error codesIt is in place for 1 institute to also need to cumulative upper this time output
Capacitance mismatch value, obtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δi=D δN-1
~D δj+1
Each electric capacity for needing to compensate is subjected to the measurement of capacitance error several times, and takes its average value, obtains each electricity
The error codes of appearance, are designated as
Step 3: background calibration：The output valve D through overcompensation that will be obtainedB, plus the error codes of this conversion
Its result is designated as DC：
Wherein, the error codes of this conversionIt is expressed as：
The overall error of sampling capacitance is
Because the gain compensation code caused by sampling capacitance is：
That is DCFinal output result D can be obtained by subtracting unbalance of system error codes again plus gain compensation codefin：
Further, step 1 and described in step 2 be 16 times several times.
Beneficial effect：The present invention provides the binary capacitor array redundancy calibration method applied to single-ended SAR ADC, relatively
In prior art, have the following advantages that：
1st, electric capacity calibration is carried out in itself using binary system redundancy calibration capacitance array, relative to traditional SAR ADC electric capacity
Mismatch calibration method, and extra calibration capacitance array is not needed, thus electric capacity corresponding to additional calibration capacitor array is saved,
Switch, and control logic, it is thus possible to save power consumption and area than traditional capacitance mismatch calibration.
2nd, single-ended SAR ADC binary capacitor array calibration methods calibration range proposed by the present invention is about ± (2j+2q)
LSB, calibration range are bigger than traditional SAR ADC Capacitor Mismatch Calibrations.
3rd, single-ended SAR ADC binary capacitor array calibration methods proposed by the present invention, it is only necessary in binary capacitor battle array
The Digital Logic of capacitor mismatch calibration is added on row redundancy calibration SAR ADC, SAR ADC analog portion is not changed, is easy to real
It is existing.
4. because this method is calibrated based on redundancy, thus capacitance mismatch can be calibrated incessantly, additionally it is possible to school
Dynamic error in quasi- transfer process.
Brief description of the drawings
Fig. 1 is single-ended SAR ADC redundancies calibration operation process.
The output digital code that Fig. 2 is single-ended SAR ADC calculates schematic diagram.
Fig. 3 is the structure chart of the single-ended SAR ADC capacitor mismatch calibrations of the present invention.
Fig. 4 is redundant capacitor distribution and its digital output code of the single-ended SAR ADC capacitor mismatch calibrations of the present invention.
Fig. 5 is the single-ended SAR ADC capacitor mismatch calibration operational flowcharts of the present invention.
Fig. 6 is the single-ended SAR ADC output spectrum figures of 14-bit of the single-ended SAR ADC capacitor mismatch calibrations of the present invention.
Embodiment
The present invention is further described below in conjunction with the accompanying drawings.
The present invention is proposed based on single-ended 14bit binary systems redundancy calibration capacitance array, and carries out capacitor array to it
Calibrate so as to improve ADC precision.Because the present invention is based on redundant capacitor calibration.Thus first to single-ended SAR ADC redundant electric
Hold calibration to illustrate.
Fig. 1 is single-ended SAR ADC redundancies calibration operation process.It can be seen that the operating process of its nonredundancy position
It is identical with normal single-ended SAR ADC.And work as and be transformed into redundant digit Cjr+And Cjr-When, first to redundant digit before
CjMake decisions, if bj is 1, enter the branch road that positive compensation is Cjr+；If bj is 0, it is Cjr-'s to enter negative compensation
Branch road.When entering positive compensation branch road, its operating process and normal position transfer process are identicals, and it is that electric capacity Cjr+ is entered to change branch road
Row operation.And when entering negative compensation branch road, be not as normal conversion first connects high level by step under electric capacity, but is directly entered and sentences
Certainly.(it is specifically shown in binary capacitor array applied to single-ended SAR ADC and its redundancy school of Patent No. 201510069640.2
Quasi- method).
The output digital code that Fig. 2 is single-ended SAR ADC calculates schematic diagram.Assume in figure in CjOne redundancy of position side insertion
Position, that is, insert redundant capacitor Cjr+, Cjr-, output output code is b caused by itjr.Calculated by redundant digit to output digital code
Formula is as shown in Figure 2.
The structure chart of the single-ended SAR ADC capacitor mismatch calibrations of Fig. 3 present invention.It can be seen that the calibration method
System architecture is based on binary system DAC capacitor array SAR ADC.On the basis of the binary system DAC capacitor arrays of traditional structure
Add redundant capacitor.One pair of which redundant capacitor Cjr+, Cjr-Positioned at the tail end of sectional capacitance MSB arrays, another pair redundant electric
Hold Cqr+, Cqr- be located in sectional capacitance LSB arrays.The calibration method only adds these two pair redundant capacitor and phase in analog domain
The switch answered, thus existing structure can be easy to be improved.Redundant digit processing and electric capacity are added in numeric field
Mismatch calibration.Wherein, redundant digit processing is by the source code D of outputAArranged, obtain representing without the defeated of electric capacity calibration
Go out digital code.Its calculating process is
Fig. 4 is redundant capacitor distribution and its digital output code of the single-ended SAR ADC capacitor mismatch calibrations of the present invention.From figure
As can be seen that electric capacity and output original number character code D corresponding to itABetween relation.Wherein in the minimum capacity of capacitor array
Two electric capacity, C are inserted belowd1And Cd2Its capacitance is respectively specific capacitance Cu1/2 and 1/4.The addition of the two electric capacity
It is to reduce the loss of significance during electric capacity is calibrated caused by quantizing noise.The binary system redundancy calibration capacitance array
Sampling capacitance CSFor CN-1To Cj, including one and CjSize identical electric capacity Cj0；I.e.：
The flow that Fig. 5 calibrates by the single-ended SAR ADC capacitance errors of institute's proposition of the present invention.
The source code of ADC outputs is DA, redundant code is added in source code, obtains the output valve D through overcompensationB：
Wherein sk+, sk-For the symbol of redundant digit, can be obtained by formula below：
Using the capacitance error of binary system redundancy calibration capacitance array calibration in itself without increasing extra electric capacity battle array
Row or extra calibration device.Capacitor array calibration method comprises the following steps that：
Step 1: obtain unbalance of system error codes：All sampling switch are disconnected in sample phase, binary system redundancy is calibrated
The sampling capacitance C of capacitor arraySLower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, compares
Two inputs of device are all connected to the common mode electrical level Vcm of comparator；After sampling terminates, sampling capacitance C is keptSLower step
It is connected in reference level Vref, single-ended SAR conversion is from Cj-1Start, and by LSB sections capacitor array most latter two small capacitances Cd1
And Cd2SAR conversion is also used for, the digital output code through overcompensation obtained by changing is designated as D △；If aforesaid operations are repeated
Dry time, and make average value, obtain unbalance of system error codes
Step 2: obtain the error codes of each electric capacity：From the lowest order electric capacity for the MSB sections for needing electric capacity calibration, Yi Jiyu
MSB section lowest order weight identical redundancy calibration capacitances start, and electric capacity calibration is carried out to MSB sections are high-order；Need the MSB calibrated
Section electric capacity is respectively from CjTo CN-1, wherein CjTo need the minimum electricity in the binary system redundancy calibration capacitance array of capacitor mismatch calibration
Hold, according to the distribution of redundant capacitor, CjThere are a pair of redundant capacitors, respectively C in sidejr+And Cjr-；The process of calibration：In sampling rank
Section disconnects all sampling switch, by CiLower step be connected to reference level Vref, wherein Ci∈(CN-1,…,Cj,Cjr+,Cjr-),
The bottom crown of other electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator；Sampling
After end, by CiLower step be connected to gnd, single-ended SAR conversion is from Ci-1Start, until small capacitances Cd1And Cd2Change-over knot
Beam；By CN-1,…,Cj,Cjr+,Cjr-Each electric capacity calibration conversion is changed several times, and it is averaged, and is obtained each
The error codes of electric capacity
Specifically, in calibration Cj、Cjr+And CjrDuring-electric capacity, the output valve D through overcompensation that will obtainBSubtract this conversion
Idea output, and subtract unbalance of system error codesObtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δiFor D δj、Dδjr+Or D δjr-；
As progress Cj+1To CN-1When capacitance error measures, the output valve D through overcompensation that will be obtained not only is neededBSubtract
The idea output of this conversion is gone, and subtracts unbalance of system error codesIt is in place for 1 institute to also need to cumulative upper this time output
Capacitance mismatch value, obtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δi=D δN-1
~D δj+1
Each electric capacity for needing to compensate is subjected to the measurement of capacitance error several times, and takes its average value, obtains each electricity
The error codes of appearance, are designated as
Step 3: background calibration：After above the operation of two steps terminates, the error for each electric capacity for needing to calibrate just is obtained
Value, next only need that output code is subtracted into corresponding error amount in normal conversion.Specially normal single-ended conversion,
From CN-1To C0, the obtained digital output value by redundancy compensation is DB, the compensation of electric capacity adaptation is carried out to it.Redundancy will be passed through
The digital output value D of compensationBPlus the mismatch compensation code of this conversionIts result is designated as DC：
Wherein, the error codes of this conversionIt is expressed as：
Because sampling capacitance has capacitance mismatch, D can be causedCGain error be present with ideal output, thus need into one
Step compensates to gain error.The overall error of sampling capacitance is
Thus, gain compensation code is：
By DCFinal output result D can be obtained by subtracting offset error again plus gain compensation codefin：
Fig. 6 is that the single-ended SAR ADC of 14-bit of the single-ended SAR ADC capacitor mismatch calibrations of the present invention calibrate design sketch.Wherein
Part I is to calibrate (without calibration) without electric capacity in figure, and the 14-bit that dynamic error be present is single-ended
SAR ADC output spectrum figures.Its sinad ratio (SNDR) and SFDR (SFDR) be respectively 40.7dB and
54.9dBc.The electric capacity of (with dual-calibration) is calibrated and calibrated based on redundancy to Part II by redundancy in figure
After mismatch calibration, 82.9dB and 96dBc has been respectively increased in its sinad ratio and SFDR.Wherein:
Normalized frequency represent normalized frequency, and magnitude represents size.
The foregoing is only the present invention better embodiment, protection scope of the present invention not using above-mentioned embodiment as
Limit, as long as equivalent modification that those of ordinary skill in the art are made according to disclosed content or change, should all include power
In protection domain described in sharp claim.
Claims (3)
1. the capacitor mismatch calibration circuit applied to single-ended SAR ADC, it is characterised in that：Including binary system redundancy calibration capacitance battle array
Row, comparator, single-ended SAR logic circuits, redundant digit computing module, capacitor mismatch calibration module；
The binary system redundancy calibration capacitance array includes segmentation binary capacitor array and at least two pairs of redundant capacitors, described
Two pairs of redundant capacitors include being inserted in segmentation binary capacitor array MSB section lowest orders CjOther redundant capacitor Cjr+And Cjr-, with
And it is inserted in any bit C in segmentation binary capacitor array LSB sectionsqOther redundant capacitor Cqr+And Cqr-；Wherein, redundant capacitor
Cjr+、Cjr-With CjCapacitance it is identical, redundant capacitor Cqr+、Cqr-With CqCapacitance is identical；The segmentation binary capacitor array
Lowest order is inserted with Cd1And Cd2,Cd1And Cd2Capacitance be respectively specific capacitance Cu1/2 and 1/4；I.e. described binary system is superfluous
The MSB sections of the sectional capacitance of remaining calibration capacitance array are CN-1To CjSection, including redundant capacitor Cjr+And Cjr-；Binary system redundancy
The LSB sections of the sectional capacitance of calibration capacitance array are Cj-1To C0Section, including redundant capacitor Cqr+、Cqr-And Cd1And Cd2；Wherein, N
For the total bit of binary system redundancy calibration capacitance array；
The sampling capacitance C of the binary system redundancy calibration capacitance arraySFor CN-1To Cj, including one and CjSize identical electric capacity
Cj0；I.e.：
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The redundant code of two pairs of redundant capacitors is added to source code D by the redundant digit computing moduleAIn, obtain through the defeated of overcompensation
Go out value DB, the source code DAFor the digital code of each output of binary system redundancy calibration capacitance array：
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sk+=DA,k×DA,kr,
The capacitor mismatch calibration module carries out the compensation of capacitance mismatch to output result.
2. it is applied to the capacitor mismatch calibration of single-ended SAR ADC capacitor mismatch calibration circuit realiration according to claim 1
Method, it is characterised in that：Comprise the following steps that：
Step 1: obtain unbalance of system error codes：All sampling switch are disconnected in sample phase, by binary system redundancy calibration capacitance
The sampling capacitance C of arraySLower step be connected to reference level Vref, the bottom crown of other electric capacity is connected to gnd, comparator
Two inputs are all connected to the common mode electrical level Vcm of comparator；After sampling terminates, sampling capacitance C is keptSLower step connection
In reference level Vref, single-ended SAR conversion is from Cj-1Start, and by LSB sections capacitor array most latter two small capacitances Cd1With
Cd2SAR conversion is also used for, the digital output code through overcompensation obtained by changing is designated as D △；Aforesaid operations are repeated some
It is secondary, and make average value, obtain unbalance of system error codes
Step 2: obtain the error codes of each electric capacity：From need electric capacity calibrate MSB sections lowest order electric capacity, and with MSB sections
Lowest order weight identical redundancy calibration capacitance starts, and electric capacity calibration is carried out to MSB sections are high-order；Need the MSB sections electricity calibrated
Hold respectively from CjTo CN-1, wherein CjTo need the minimum capacity in the binary system redundancy calibration capacitance array of capacitor mismatch calibration,
According to the distribution of redundant capacitor, CjThere are a pair of redundant capacitors, respectively C in sidejr+And Cjr-；The process of calibration：In sample phase
All sampling switch are disconnected, by CiLower step be connected to reference level Vref, wherein Ci∈(CN-1,…,Cj,Cjr+,Cjr-), its
The bottom crown of his electric capacity is connected to gnd, and two inputs of comparator are all connected to the common mode electrical level Vcm of comparator；Sampling knot
After beam, by CiLower step be connected to gnd, single-ended SAR conversion is from Ci-1Start, until small capacitances Cd1And Cd2Conversion end；
By CN-1,…,Cj,Cjr+,Cjr-Each electric capacity calibration conversion is changed several times, and it is averaged, and obtains each electric capacity
Error codes
Specifically, in calibration Cj、Cjr+And Cjr-During electric capacity, the output valve D through overcompensation that will obtainBSubtract the reason of this conversion
Think output valve, and subtract unbalance of system error codesObtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δiFor D δj、Dδjr+Or D δjr-；
As progress Cj+1To CN-1When capacitance error measures, the output valve D through overcompensation that will be obtained not only is neededBSubtract this
The idea output of secondary conversion, and subtract unbalance of system error codesAlso need to this cumulative upper time and export the electricity in place for 1
Hold mismatch value, obtain the capacitance mismatch compensation codes D δ of thisi, i.e.,：
Wherein D δi=D δN-1~D
δj+1
Each electric capacity for needing to compensate is subjected to the measurement of capacitance error several times, and takes its average value, obtains each electric capacity
Error codes, it is designated as
Step 3: background calibration：The output valve D through overcompensation that will be obtainedB, plus the error codes of this conversionIts result
It is designated as DC：
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<mrow>
<mi>j</mi>
<mo>-</mo>
</mrow>
</msub>
<mo>&times;</mo>
<mover>
<mrow>
<msub>
<mi>D&delta;</mi>
<mrow>
<mi>j</mi>
<mi>r</mi>
<mo>-</mo>
</mrow>
</msub>
</mrow>
<mo>&OverBar;</mo>
</mover>
<mo>)</mo>
</mrow>
<mo>;</mo>
</mrow>
The overall error of sampling capacitance is
<mrow>
<mover>
<mrow>
<msub>
<mi>D&delta;</mi>
<mi>S</mi>
</msub>
</mrow>
<mo>&OverBar;</mo>
</mover>
<mo>=</mo>
<munderover>
<mo>&Sigma;</mo>
<mrow>
<mi>k</mi>
<mo>=</mo>
<mi>j</mi>
</mrow>
<mrow>
<mi>N</mi>
<mo>-</mo>
<mn>1</mn>
</mrow>
</munderover>
<mover>
<mrow>
<msub>
<mi>D&delta;</mi>
<mi>k</mi>
</msub>
</mrow>
<mo>&OverBar;</mo>
</mover>
</mrow>
Because the gain compensation code caused by sampling capacitance is：
<mrow>
<msub>
<mi>D</mi>
<mrow>
<mi>c</mi>
<mi>o</mi>
<mi>m</mi>
<mi>p</mi>
</mrow>
</msub>
<mo>=</mo>
<mo>-</mo>
<mrow>
<mo>(</mo>
<mover>
<mrow>
<msub>
<mi>D&delta;</mi>
<mi>S</mi>
</msub>
</mrow>
<mo>&OverBar;</mo>
</mover>
<mo>&times;</mo>
<munderover>
<mo>&Sigma;</mo>
<mrow>
<mi>k</mi>
<mo>=</mo>
<mn>0</mn>
</mrow>
<mrow>
<mi>N</mi>
<mo>-</mo>
<mn>1</mn>
</mrow>
</munderover>
<msub>
<mi>D</mi>
<mrow>
<mi>C</mi>
<mo>,</mo>
<mi>k</mi>
</mrow>
</msub>
<msup>
<mn>2</mn>
<mi>k</mi>
</msup>
<mo>)</mo>
</mrow>
<mo>&divide;</mo>
<msup>
<mn>2</mn>
<mi>N</mi>
</msup>
</mrow>
That is DCFinal output result D can be obtained by subtracting unbalance of system error codes again plus gain compensation codefin：
<mrow>
<msub>
<mi>D</mi>
<mrow>
<mi>f</mi>
<mi>i</mi>
<mi>n</mi>
</mrow>
</msub>
<mo>=</mo>
<msub>
<mi>D</mi>
<mi>C</mi>
</msub>
<mo>+</mo>
<msub>
<mi>D</mi>
<mrow>
<mi>c</mi>
<mi>o</mi>
<mi>m</mi>
<mi>p</mi>
</mrow>
</msub>
<mo>-</mo>
<mover>
<mrow>
<mi>D</mi>
<mi>&Delta;</mi>
</mrow>
<mo>&OverBar;</mo>
</mover>
<mo>.</mo>
</mrow>
3. it is applied to the capacitor mismatch calibration of single-ended SAR ADC capacitor mismatch calibration circuit realiration according to claim 2
Method, it is characterised in that：Described in step 1 and step 2 is 16 times several times.
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| CN109802674B (en) * | 2017-11-17 | 2021-07-16 | 比亚迪半导体股份有限公司 | Successive approximation analog-to-digital converter and digital calibration method and device thereof |
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