CN108365847B - Calibration method for parasitic capacitance of charge type SAR-ADC - Google Patents
Calibration method for parasitic capacitance of charge type SAR-ADC Download PDFInfo
- Publication number
- CN108365847B CN108365847B CN201711483390.2A CN201711483390A CN108365847B CN 108365847 B CN108365847 B CN 108365847B CN 201711483390 A CN201711483390 A CN 201711483390A CN 108365847 B CN108365847 B CN 108365847B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- adc
- capacitance
- sar
- compensation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 111
- 238000005070 sampling Methods 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000013461 design Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 description 13
- 229920005994 diacetyl cellulose Polymers 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a calibration method for parasitic capacitance of a charge type SAR-ADC (synthetic aperture radar-analog converter), wherein the charge type SAR-ADC comprises an LSB (least significant bit) capacitor array, all upper polar plates of the LSB capacitor array are connected with one end of a first compensation circuit, the other end of the first compensation circuit is connected with any constant potential, and the first compensation circuit is formed by a first fixed capacitor CdlAnd a first tunable capacitor CdlAnd the parallel connection is adopted, and the nonlinear error of the SAR-ADC is adjusted by adjusting the first compensation circuit. The unit capacitance value in the LSB capacitor array is CuL bits, which are increased by 2 times from low bit to high bit, and the highest bit capacitance is 2L‑1Cu. When the total capacitance value of the LSB capacitor array is CLtIf so, the following relationship holds: cLt＝(2L‑1)·Cu+Cdl+Cdl". The calibration method aiming at the parasitic capacitance of the charge type SAR-ADC can achieve high linearity and gain adjustment precision, and is particularly suitable for the design of a high-precision ADC.
Description
Technical Field
The invention relates to the field of chip design, in particular to a calibration method for parasitic capacitance of a charge type SAR-ADC.
Background
Conversion between analog and digital signals is an important component of signal processing, and analog signals in nature, such as sound, light, electricity, and the like, are converted into digital signals through an analog-to-digital converter (ADC) before being further converted and processed by a digital system. Different systems have different index requirements on the ADC, and different ADC index requirements are adapted to the different ADC index requirements by corresponding ADC structures. With the reduction of the process size of integrated circuits and the improvement of the precision of manufacturing processes, the ADC structures which are most widely applied at present are SAR-ADCs, sigma-delta ADCs and pipeline ADCs. And a successive approximation converter (SAR-ADC) has the comprehensive advantages of medium speed, medium precision, low power consumption and low cost, and is applied to a wider field.
The basic structure of the SAR-ADC comprises a comparator, a digital-to-analog converter (DAC) and a successive approximation controller (SAR). The method compares the sampling signal with the known voltage continuously, one-bit conversion is completed in one period, N-bit conversion is completed in N periods, and the resolution and the conversion speed of the SAR-ADC are contradictory. Wherein the accuracy of the ADC is mainly determined by the accuracy of the digital-to-analog converter. The structure of the digital-to-analog converter is many, and the most widely used is a charge type digital-to-analog converter, as shown in fig. 1. The working process of the charge type digital-to-analog converter is completed by redistributing charges in the binary proportion dividing capacitor array, the input voltage is compared with the reference voltage proportion by the redistribution of the charges, the reference voltage proportion closest to the input voltage is found, and the conversion between analog and digital is realized. The accuracy and required area of the charge-type DAC are both limiting bitsNumerical, where accuracy refers to the proportional accuracy of the capacitance. The proportional accuracy of the capacitor is positively correlated with the area of the capacitor, and a larger area must be consumed to achieve higher proportional accuracy. Under the existing process conditions, the capacitance ratio accuracy can be as low as 0.1%, and the capacitance ratio accuracy of 0.1% is only suitable for the capacitance ratio close to 1, and when the ratio is increased, the accuracy is correspondingly reduced. Under the same conditions, the charge-type DAC without digital calibration can generally achieve the precision of 10-bit, namely the ratio between the maximum capacitance and the minimum capacitance in the capacitance array divided by the binary proportion is 512: 1. In order that the matching accuracy does not decrease with the increase of the DAC accuracy, one high-accuracy DAC may be divided into a plurality of sub-DACs, and each sub-DAC is connected with a scaling capacitor, as shown in fig. 2. sub-DACs with MSB and LSB respectively of M bits and L bits, and capacitor CaTo scale the capacitance, the MSB and LSB are connected into one DAC of M + L bits. In order to ensure the matching precision of each sub-DAC, the number of bits of a single sub-DAC is not too high. When the accuracy of the whole DAC is high, in order to ensure the matching accuracy of a single sub DAC, the whole capacitor array may be divided into a plurality of segments, and connected through a plurality of scaling capacitors. In order to ensure the linear relationship between the segmented DACs, the following formula needs to be satisfied:
Ca·Ceq/(Ca+Ceq)＝k·Cu
ideally the capacitor segmentation solves the problem of the matching accuracy decreasing with increasing DAC accuracy, but in non-ideal cases there is a parasitic capacitance between the upper and lower plates of the capacitor to ground and the plates, as shown in figure 3. The Top and Bottom points are two ends of the capacitor, and the Shield end is a shielding end (for shielding interference between a capacitor plate and a substrate) or the substrate of the capacitor. CpaThe parasitic capacitance of the traces at the two ends of Top and Bottom. Cp1And Cp2The parasitic capacitances between Top/Shield and Bottom/Shield, respectively. Since the parasitic capacitance is not considered at the time of design and varies with process corner, the presence of the parasitic capacitance causes non-linearity between the segmented DACs.
To adjust eachThe nonlinearity between the segmented capacitors is usually achieved by introducing an adjustable capacitor C in the circuitaShown in fig. 4. CaThe regulation of is connected A, B two points or disconnected A, B two points by means of MOS switch or FIB. Because the capacitance parasitics of the same batch are the same, the variable capacitance can be linearly adjusted through the measurement result after the chip is tapped, so that the linear requirements among the adjusted sub-DACs are met.
The following disadvantages of the prior art can be easily found through the above research on the prior art and the consideration of the application environment of the actual circuit system:
(1) in general, in order to reduce the parasitic capacitance of the scaling capacitor, the value of the scaling capacitor is relatively small. When the ADC has a high requirement for linearization, the adjustable part of the scaling capacitor needs to have a high enough precision, and a small enough capacitor is needed to achieve a high enough capacitor adjustment precision, and when the capacitor is small enough to be equivalent to the parasitic capacitor of the adjustment switch, the adjustment cannot be performed to a higher precision, which results in a limited adjustment precision.
(2) When the scaling capacitor is adjusted by adopting a MOS (metal oxide semiconductor) switch mode, the point A or the point B is inevitably connected with one end of the adjusting switch, the voltages of the point A, B are changed violently in the conversion process, the change of the voltages can cause the violent change of the parasitic capacitance of the adjusting switch, and the change of the parasitic capacitance of the point A, B can seriously affect the precision and the gain of the ADC.
(3) When the scaling capacitor is adjusted by adopting an FIB mode, the FIB adjustment needs to be carried out on each chip, and due to the fact that the FIB has economic and time cost, the cost of the chip is greatly increased and the capacity of the chip is severely limited.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a calibration method aiming at parasitic capacitance of a charge type SAR-ADC, which is used for designing a high-precision SAR-ADC.
In order to achieve the above object, the present invention provides a calibration method for parasitic capacitance of a charge type SAR-ADC, the charge type SAR-ADC comprising an LSB capacitor array, all upper plates of the LSB capacitor array being connected to one end of a first compensation circuit, the other end of the first compensation circuit being connected to an arbitrary constant potential, the first compensation circuit being connected to a first fixed capacitor CdlAnd a first tunable capacitor CdlAnd the parallel connection is adopted, and the nonlinear error of the SAR-ADC is adjusted by adjusting the first compensation circuit. The unit capacitance value in the LSB capacitor array is CuL bits, which are increased by 2 times from low bit to high bit, and the highest bit capacitance is 2L-1Cu. When the total capacitance value of the LSB capacitor array is CLtIf so, the following relationship holds: cLt＝(2L-1)·Cu+Cdl+Cdl＇。
Preferably, in the above technical solution, the first adjustable capacitor CdlIs composed of a plurality of capacitor bank circuits connected in parallel. The first adjustable capacitor CdlEach of said capacitor bank circuits of "" consists of two capacitors in series, and one of the capacitors is connected in parallel with a gating switch.
Preferably, in the above technical solution, the values of the capacitors in each capacitor bank circuit in the first adjustable capacitor are the same or different.
Preferably, in the above technical solution, the charge-type SAR-ADC further includes an MSB capacitor array, all upper plates of the MSB capacitor array are connected to one end of a second compensation circuit, one path of the other end of the second compensation circuit is connected to any constant potential through a gating switch, and the other path is connected to a sampling signal through another gating switch. The second compensation circuit is formed by connecting a second fixed capacitor and a second adjustable capacitor in parallel. Adjusting the overall gain of the SAR-ADC by adjusting the second compensation circuit. The unit capacitance value of the MSB capacitor array is CuThe total M bits are increased by 2 times from the low bit to the high bit, and the highest bit capacitance value is 2M-1Cu。
Preferably, in the above technical solution, the second adjustable capacitor is formed by connecting N capacitor bank circuits in parallel. Each capacitor bank circuit in the second adjustable capacitor is formed by connecting two capacitors in series, wherein one capacitor is connected with one gating switch in parallel.
Preferably, in the above technical solution, the values of the capacitors in each capacitor bank circuit in the second adjustable capacitor are the same or different.
Preferably, in the above technical solution, the charge-type SAR-ADC further includes a comparator. Sampling of the charge type SAR-ADC is only carried out aiming at the MSB capacitor array, in the conversion process, the lower pole plate of each weight capacitor is connected to a reference potential in a continuous mode according to the judgment result of the comparator, and when the ratio of the sampling capacitor to the total capacitor connected to the reference potential is equal to 1, the gain of the charge type SAR-ADC is 1; when the ratio of the sampling capacitor to the total capacitor connected to the reference potential is greater than 1, the gain of the charge type SAR-ADC is less than 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is less than 1, the gain of the charge type SAR-ADC is more than 1.
Compared with the prior art, the invention has the following beneficial effects: can achieve high linearity and gain adjustment precision, and is particularly suitable for the design of high-precision ADC.
Drawings
Fig. 1 is a circuit block diagram of a charge-type SAR-ADC according to the prior art.
Fig. 2 is a block diagram of a charge-type SAR-ADC circuit according to the prior art with DAC segmentation.
Fig. 3 is a capacitive parasitic diagram according to the prior art.
Fig. 4 is a block diagram of a charge-type SAR-ADC circuit framework for DAC segmentation and parasitic capacitance calibration according to the prior art.
Fig. 5 is a circuit block diagram of a SAR-ADC according to an embodiment of the present invention.
Fig. 6 is a diagram of an adjustable capacitor structure of a calibration method for parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The invention aims to provide a calibration method for parasitic capacitance of a charge type SAR-ADC. As shown in fig. 5. Fig. 5 is a circuit block diagram of a SAR-ADC according to an embodiment of the present invention.
Firstly, on the basis of a circuit with only an MSB capacitor participating in sampling, a fixed capacitor and an adjustable capacitor are respectively introduced to adjust A, B a linearity error and a gain error caused by two-point parasitic capacitance. Wherein, CdlAnd CdlFor adjusting the linear relationship between the individual segmented sub-DACs, CdmAnd CdmFor adjusting the overall gain of the ADC.
First fixed capacitor CdlAnd a first adjustable capacitor Cdl' the top plate is connected with the point A, the bottom plate is connected with the VCM, wherein the VCM is any constant potential. CdlThe DAC basically satisfies a linear relation between the two terminals of the scaling capacitor. But only C is introduced because of the parasitic capacitance of each capacitordlThe linear relation between sub-DACs under all process corners cannot be satisfied, so that C needs to be introduceddl' for accommodating variations in parasitic capacitance at different process corners.
To ensure the linear relationship between the segmented DACs, the capacitance C needs to be scaledaTwo adjacent bits at two ends keep a weight relationship of two times, namely the weight of the MSB most significant bit is two times of the weight of the LSB least significant bit, can be simply understood as inputting step voltages with equal amplitude at ① and ② points respectively, so that the voltage change caused by the step voltages at the B point is dV respectively1And dV2And requires:
dV2＝2dV1equation 1
In order to satisfy the requirement of formula 2, the values of the capacitors need to satisfy the following relationship:
k·(Ca+CLt)＝2L·Caequation 2
Wherein,
CLt＝(2L-1)·Cu+Cdl+Cdl' formula 3
By adjusting C when the capacitance is parasitic or mismatched, resulting in non-linearity between MSB and LSBdlAnd CdlI.e. its non-linearity can be compensated for so that it meets the linearity requirement. CdlTo a design standard value, Cdl' is used to counteract non-linearity errors due to process and parasitic imperfections.
Second fixed capacitor CdmAnd a second tunable capacitor CdmThe upper plate of the grid is connected with the point B, and the lower plate is respectively connected with the point V through two switchesINAnd VCMIn which V isCMIs an arbitrary constant potential.
In the invention, ADC sampling is only carried out for MSB bit, and in the conversion process, the lower electrode plate of each weight capacitor is connected to the reference potential in sequence according to the judgment result of the comparator. When the ratio of the sampling capacitance to the total capacitance connected to the reference potential is 1, the gain of the ADC is 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is greater than 1, the gain of the ADC is less than 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is less than 1, the gain of the ADC is greater than 1; therefore, the gain of the ADC can be directly adjusted by adjusting the value of the sampling capacitor without affecting the linearity of the ADC. The sampling capacitance can be adjusted by adjusting CdmAnd CdmTo make regulation, CdmTo a design standard value, CdmAdjustments are made to offset gain errors due to process and parasitic imperfections.
Fig. 6 is a diagram of an adjustable capacitor structure of a calibration method for parasitic capacitance of a charge-type SAR-ADC according to an embodiment of the present invention. The Top and Bottom plates of the adjustable capacitor are arranged at the Top and Bottom ends respectively, C1、C2…CnThe upper plate of (A) is connected with the Top terminal, C1、C2…CnRespectively with C11、C21…Cn1The upper polar plate is connected with S1、S2…Sn，C11、C21…Cn1The lower pole plate is connected with Bottom, and a node S1、S2…SnRespectively through switches SW1、SW2…SWnConnected with the Bottom end.
When SW1When the switch is closed, the capacitor C1Connecting to both ends of Top and Bottom, when SW1When the switch is off, the capacitor C1·C11/(C1+C11) Accessing both ends of Top and Bottom; when SW2When the switch is closed, the capacitor C2Connecting to both ends of Top and Bottom, when SW2When the switch is off, the capacitor C2·C21/(C2+C21) Both ends of Top and Bottom; and so on, when the SWn switch is closed, the capacitor CnConnecting to both ends of Top and Bottom, when SWnWhen the switch is off, the capacitor Cn·Cn1/(Cn+Cn1) Accessing both ends of Top and Bottom; by the above analysis, the adjustable capacitance C can be calculatedtotThe regulation range of (2) is:
C1·C11/(C1+C11)+C2·C21/(C2+C21)+…+Cn·Cn1/(Cn+Cn1)≤Ctot≤C1+C2+…+Cn
in the case of a defined process corner, the parasitic capacitance is also defined, by adjusting the adjustable capacitance C at different process cornersdlThe value of can eliminate the influence of parasitic capacitance on the linear relation among the sub-DACs, and C is adjusteddmThe value of can adjust the gain of the ADC.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (6)
1. A calibration method for parasitic capacitance of a charge type SAR-ADC (synthetic aperture radar-analog converter), wherein the charge type SAR-ADC comprises an LSB (least significant bit) capacitor array, and is characterized in that all upper polar plates of the LSB capacitor array are connected with one end of a first compensation circuit, the other end of the first compensation circuit is connected with any constant potential, and the first compensation circuit is formed by a first fixed capacitor CdlAnd a first tunable capacitor Cdl' a parallel component, adjusting a non-linearity error of the SAR-ADC by adjusting the first compensation circuit,
the unit capacitance value in the LSB capacitor array is CuL bits, which are increased by 2 times from low bit to high bit, and the highest bit capacitance is 2L-1CuAnd when the total capacitance value of the LSB capacitor array is CLtIf so, the following relationship holds:
CLt＝(2L-1)·Cu+Cdl+Cdl′；
the charge type SAR-ADC also comprises an MSB capacitor array, all upper polar plates of the MSB capacitor array are connected with one end of a second compensation circuit, one path of the other end of the second compensation circuit is connected with any constant potential through a gating switch, the other path of the other end of the second compensation circuit is connected with a sampling signal through another gating switch, the second compensation circuit is formed by connecting a second fixed capacitor and a second adjustable capacitor in parallel, the overall gain of the SAR-ADC is adjusted by adjusting the second compensation circuit,
the unit capacitance value of the MSB capacitor array is CuThe total M bits are increased by 2 times from the low bit to the high bit, and the highest bit capacitance value is 2M-1Cu。
2. The SAR-ADC parasitic capacitance for charge type of claim 1In a calibration method, characterized in that said first adjustable capacitance Cdl' is composed of a plurality of capacitor bank circuits connected in parallel,
the first adjustable capacitor Cdl' each of the capacitor bank circuits is composed of two capacitors connected in series, and one of the capacitors is connected in parallel with one of the gate switches.
3. The calibration method for parasitic capacitance of charge-type SAR-ADC according to claim 2, wherein the capacitance in each of said capacitor bank circuits of said first tunable capacitor is equal or different.
4. The calibration method for parasitic capacitance of charge-type SAR-ADC of claim 1, wherein the second adjustable capacitance is composed of N capacitance bank circuits in parallel,
each capacitor bank circuit in the second adjustable capacitor is formed by connecting two capacitors in series, and one capacitor is connected with one gating switch in parallel.
5. The calibration method for parasitic capacitance of charge-type SAR-ADC of claim 4, wherein the capacitance in each of the capacitance group circuits in the second adjustable capacitance is the same or different.
6. The method of claim 1, wherein the SAR-ADC further comprises a comparator, wherein the sampling of the SAR-ADC is performed only for the MSB capacitor array, during the conversion, the lower plate of each weight capacitor is sequentially connected to a reference potential according to the judgment result of the comparator, and when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is equal to 1, the gain of the SAR-ADC is 1; when the ratio of the sampling capacitor to the total capacitor connected to the reference potential is greater than 1, the gain of the charge type SAR-ADC is less than 1; when the ratio of the sampling capacitance to the total capacitance connected to the reference potential is less than 1, the gain of the charge type SAR-ADC is more than 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711483390.2A CN108365847B (en) | 2017-12-29 | 2017-12-29 | Calibration method for parasitic capacitance of charge type SAR-ADC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711483390.2A CN108365847B (en) | 2017-12-29 | 2017-12-29 | Calibration method for parasitic capacitance of charge type SAR-ADC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108365847A CN108365847A (en) | 2018-08-03 |
| CN108365847B true CN108365847B (en) | 2020-09-01 |
Family
ID=63010713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711483390.2A Active CN108365847B (en) | 2017-12-29 | 2017-12-29 | Calibration method for parasitic capacitance of charge type SAR-ADC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108365847B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108923786A (en) * | 2018-08-23 | 2018-11-30 | 中国电子科技集团公司第二十四研究所 | A kind of march-past capacitor array structure SAR ADC |
| CN109756229B (en) * | 2018-12-07 | 2023-01-17 | 国网天津市电力公司 | Configurable sigma delta ADC modulator suitable for wireless communication system |
| CN109818617A (en) * | 2019-01-28 | 2019-05-28 | 西安微电子技术研究所 | A kind of high-precision calibration device of SAR type ADC |
| CN110138387B (en) * | 2019-06-05 | 2020-11-03 | 中国电子科技集团公司第二十四研究所 | SAR ADC based on single-channel time interleaved sampling and sampling method |
| CN111162787B (en) * | 2019-12-27 | 2022-01-04 | 清华大学 | Successive approximation type analog-to-digital converter with passive noise shaping |
| CN112311395B (en) * | 2020-11-17 | 2022-02-01 | 北京智芯微电子科技有限公司 | Calibration method of charge type SAR ADC |
| TWI763524B (en) * | 2021-06-04 | 2022-05-01 | 瑞昱半導體股份有限公司 | Method of operating analog-to-digital converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594353A (en) * | 2011-01-13 | 2012-07-18 | 中兴通讯股份有限公司 | Digital-to-analog converter and successive approximation storage converter |
| CN103475373A (en) * | 2013-09-02 | 2013-12-25 | 深圳市汇顶科技股份有限公司 | Digital-to-analog converter with sectional capacitor array structure |
| CN104124967A (en) * | 2014-07-10 | 2014-10-29 | 天津大学 | Segmented capacitor array type successive approximation analog-digital converter calibration structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6707403B1 (en) * | 2002-11-12 | 2004-03-16 | Analog Devices, Inc. | Analog to digital converter with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital converter |
| JP2010045723A (en) * | 2008-08-18 | 2010-02-25 | Fujitsu Ltd | Digital-to-analog converter |
| DE102009010155B4 (en) * | 2009-02-23 | 2013-02-07 | Texas Instruments Deutschland Gmbh | Digital trimming of (SAR) ADCs |
| JP6102521B2 (en) * | 2013-05-29 | 2017-03-29 | 株式会社ソシオネクスト | SAR analog-digital conversion method and SAR analog-digital conversion circuit |
| CN104917527B (en) * | 2015-06-30 | 2017-12-05 | 东南大学 | Capacitor mismatch calibration circuit and its calibration method applied to single-ended SAR ADC |
| TWI591969B (en) * | 2016-04-15 | 2017-07-11 | 瑞昱半導體股份有限公司 | Calibration circuit and calibration method for DAC |
-
2017
- 2017-12-29 CN CN201711483390.2A patent/CN108365847B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594353A (en) * | 2011-01-13 | 2012-07-18 | 中兴通讯股份有限公司 | Digital-to-analog converter and successive approximation storage converter |
| CN103475373A (en) * | 2013-09-02 | 2013-12-25 | 深圳市汇顶科技股份有限公司 | Digital-to-analog converter with sectional capacitor array structure |
| CN104124967A (en) * | 2014-07-10 | 2014-10-29 | 天津大学 | Segmented capacitor array type successive approximation analog-digital converter calibration structure |
Non-Patent Citations (2)
| Title |
|---|
| A self-testing and calibration method for embedded successive approximation register ADC;Xuan-Lun Huang;《ASPDAC "11: Proceedings of the 16th Asia and South Pacific Design Automation Conference》;20110131;713-718页 * |
| 基于16位SAR模数转换器的误差校准方法;乔高帅;《微纳电子技术》;20091031;第46卷(第10期);636-639页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108365847A (en) | 2018-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108365847B (en) | Calibration method for parasitic capacitance of charge type SAR-ADC | |
| US10135457B2 (en) | Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter | |
| US9019140B2 (en) | System and method for analog to digital (A/D) conversion | |
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| CN112202448B (en) | Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment | |
| CN107346975B (en) | SAR type ADC's high accuracy calibrating device | |
| CN109347477B (en) | Successive approximation type analog-to-digital converter weight calibration method | |
| CN112636757B (en) | Successive approximation type analog-to-digital converter and offset compensation method thereof | |
| CN103873059A (en) | Digital calibration method for high-precision SAR ADC (successive approximation register analog to digital converter) | |
| CN104168020A (en) | Capacitive nonlinear calibration circuit of bit-by-bit approximation analog-digital converter and method | |
| CN112039528B (en) | Capacitor array logic control method in successive approximation analog-to-digital converter | |
| CN112803946B (en) | Capacitor mismatch and offset voltage correction method applied to high-precision successive approximation ADC (analog to digital converter) | |
| CN114050827A (en) | Digital calibration method applied to capacitance three-section successive approximation type analog-to-digital converter | |
| CN110535467B (en) | Capacitor array calibration method and device of stepwise approximation type analog-to-digital conversion device | |
| Guan et al. | A low-cost digital-domain foreground calibration for high resolution SAR ADCs | |
| CN114826263B (en) | Floating node calibration method applied to sectional type successive approximation analog-to-digital converter | |
| Wu et al. | A design method of capacitor arrays for high-resolution SAR ADCs | |
| Gu et al. | An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation | |
| Zhang et al. | Mismatch and parasitics limits in capacitors-based SAR ADCs | |
| WO2014038197A1 (en) | Capacitive digital-to-analog converter and analog-to-digital converter using same | |
| TWI751958B (en) | Successive-approximation register adc | |
| CN110071720B (en) | Self-calibrating full-capacitance successive approximation digital-to-analog conversion circuit | |
| KR20190134883A (en) | Analogue-to-digital converter based on integer-based split capacitors | |
| Mueller et al. | The impact of noise and mismatch on SAR ADCs and a calibratable capacitance array based approach for high resolutions | |
| TWI763525B (en) | Analog-to-digital converter and method of operating same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |