CN112202448B - Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment - Google Patents
Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
- H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The application discloses a successive approximation analog-to-digital converter, a digital calibration method thereof and an electronic device, wherein the analog-to-digital converter comprises: the DAC module is used for sampling an analog input signal and converting the analog input signal into an analog output voltage; a comparator for comparing the analog output voltage with the reference voltage and outputting a comparison result; the logic control module is connected with the output end of the comparator, and is used for performing successive approximation control on the DAC module according to the comparison result so that the comparator can output the comparison result successively and output corresponding transcoding signals according to the comparison result after the successive approximation control is finished; the digital calibration module is used for outputting a calibrated transcoding signal after performing calibration calculation on the comparison result or the transcoding signal according to the weight error delta q of each bit, wherein delta q=w-W idea ‑W offset . The analog-to-digital converter has higher conversion performance.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a successive approximation type analog-to-digital converter, a calibration algorithm thereof and electronic equipment.
Background
The successive approximation analog-to-digital converter (Successive Approximation Register Analog Digital Converter, SARADC) has the advantages of low delay, low power consumption and the like, and is widely applied to various fields. Most of the current high-precision successive approximation type analog-digital converters adopt a binary capacitor array structure, and digital codes corresponding to input signals are obtained from high-order to low-order through successive comparison of input voltage signals and voltage values generated by a capacitor array. The accuracy of SARADC is limited by the mismatch of noise and capacitance of each module. The mismatch of the capacitor is determined by the manufacturing process of the integrated circuit, and various uncertainties in the manufacturing process directly affect the precision and linearity of the SARADC. The capacitor mismatch problem can be improved by increasing the size of the capacitor, and the accuracy of SARADC can be improved. However, increasing the capacitance size results in an increase in chip area and cost.
The prior art can employ a segmented capacitive structure to reduce the capacitive array area. However, the segmented capacitor structure is sensitive to capacitor mismatch and parasitic capacitance across the capacitor, so a more complex capacitor mismatch calibration method is also required to improve the performance of the successive approximation type analog-to-digital converter, specifically, a calibration capacitor array needs to be added in the SARADC, and the deviation of the main capacitor array is calibrated through the compensation of analog signals. To ensure the performance of the analog-to-digital converter, an additional calibration capacitor array is added, and a relatively large capacitor area is still required.
Therefore, the size of the prior art analog-to-digital converter is still to be further reduced.
Disclosure of Invention
In view of the above, the present application provides a successive approximation type analog-to-digital converter and a calibration algorithm thereof, so as to further reduce the size of the successive approximation type analog-to-digital converter.
The application provides a successive approximation analog-to-digital converter, comprising: the DAC module is used for sampling an analog input signal and converting the analog input signal into an analog output voltage; the first input end of the comparator is connected to the DAC module, the second input end of the comparator is connected to a reference voltage, and the comparator is used for comparing the analog output voltage with the reference voltage and outputting a comparison result; the logic control module is connected with the output end of the comparator and is used for performing successive approximation control on the DAC module according to the comparison result so that the comparator outputs the comparison result successively and outputs corresponding transcoding signals according to the comparison result after the successive approximation control is finished; the digital calibration module is used for outputting a calibrated transcoding signal after performing calibration calculation on the comparison result or the transcoding signal according to the weight error delta q of each bit, wherein delta q=w-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset For a fixed offset weight.
Optionally, the DAC module includes: the low-level segment DAC unit and the high-level segment DAC unit are connected through a bridging capacitor C0, wherein each bit of the high-level segment DAC unit is correspondingly provided with a weight error delta q.
Optionally, the calibration calculation includes: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n+1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 )，D 0 ～D n-1 Binary values of 1 to n bits respectively corresponding to the low-order DAC units, D n ～D m+n-1 Binary values corresponding to n+1 to m+n bits of the high-order segment DAC unit, respectively; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal.
Optionally, the fixed offset weight W offset The difference value between the conversion code quantized by the bridge capacitor C0 and the ideal weight of the bridge capacitor C0 is obtained by adopting a low-level DAC unit.
Optionally, the measurement weight W and the weight error Δq are obtained from a bit-by-bit measurement from a low bit to a high bit in the high bit segment DAC unit.
Optionally, the high-level segment DAC unit includes at least one of an m-bit capacitor array or an m-bit resistor array, and the low-level segment DAC unit includes at least one of an n-bit resistor array or an n-bit capacitor array.
Optionally, the capacitive array comprises at least one of a binary capacitive array, an equivalent capacitive array, or a segmented capacitive array.
Optionally, n is greater than or equal to 3.
Optionally, the low-level segment DAC unit includes an n-bit resistor array, the high-level segment DAC unit includes an m-bit capacitor array, and the bridge capacitor C0 is equal to the capacitance of the lowest-level capacitor in the high-level segment DAC unit.
Optionally, the high-order segment DAC unit includes an m-bit capacitor array and at least one redundant capacitor, where the redundant capacitor is connected in parallel with a capacitor in the m-bit capacitor array, and the capacitance of the redundant capacitor is equal to the capacitance of the lowest-order capacitor in the m-bit capacitor array.
Optionally, the calibration module includes: a storage unit and a calculation unit; the storage unit is used for storing the fixed offset weight Woffset and the weight error deltaq; the calculating unit is used for obtaining the weight error delta q, carrying out calibration calculation on the transcoding signal according to the weight error delta q, and outputting the calibrated transcoding signal.
Optionally, the calculating unit is further configured to measure the weight W, the ideal weight W according to each bit idea The fixed offset weight W offset And calculating the weight error delta q and storing the weight error delta q in the storage unit.
The application also provides a digital calibration method of the successive approximation analog-to-digital converter, which comprises the following steps: the digital calibration method comprises the following steps: sampling an analog input signal by a DAC module and converting the analog input signal into an analog output voltage; comparing the analog output voltage with a reference voltage through a comparator, and outputting a comparison result; according to the comparison result, successive approximation control is adopted for the DAC module, so that the comparator outputs the comparison result successively; after successive approximation control is completed, outputting corresponding transcoding signals according to the comparison results; according to the weight error delta q of each bit, the comparison result or the transcoding signal is calibrated and calculated to output a calibrated transcoding signal, wherein delta q=W-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset To fix the offset weight, the offset weight W is fixed for each bit offset The same applies.
Optionally, the DAC module includes: the low-level segment DAC unit and the high-level segment DAC unit are connected through a bridging capacitor C0; the weight error deltaq is set only for each bit in the high-order segment DAC cell.
Optionally, the high-level segment DAC unit includes an m-bit capacitor array, and obtains the fixed offset weight W offset The method of (1) comprises: the lower electrode plates of all the capacitors of the high-level DAC unit are grounded, and the upper electrode plate of the bridging capacitor C0 is connectedTo the reference voltage, and controlling a switch array in the low-level DAC unit to enable the potential of the lower polar plate of the bridging capacitor C0 to be set voltage; disconnecting an upper polar plate of a bridging capacitor C0 from a reference voltage, and performing successive approximation control on a switch array in a low-level-section DAC unit to obtain a conversion code of the bridging capacitor C0 quantized by the low-level-section DAC unit; calculating the difference between the conversion code of the bridge capacitor C0 and the ideal weight as the fixed offset weight W offset 。
Optionally, the method for acquiring the measurement weight W of each bit in the high-order segment DAC unit includes: connecting a capacitor lower polar plate corresponding to a bit to be calibrated to a reference voltage, and grounding all capacitor lower polar plates corresponding to the bit above the bit to be calibrated; successive approximation control is carried out on a capacitor corresponding to a bit below the capacitor bit to be calibrated and a switch array of a DAC unit at a low level segment to obtain a conversion code after analog-digital conversion; and acquiring the measurement weight according to the conversion code.
Optionally, the measurement weight and the weight error are obtained from the low bit to the high bit in the high-order segment DAC unit; and when the measurement weight is obtained according to the conversion code, the method further comprises calibrating binary values corresponding to bits below the current calibration bit in the conversion code by using corresponding weight errors.
Optionally, the calibration calculation includes: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n+1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 )，D 0 ～D n-1 Binary values of 1 to n bits corresponding to the low-order segment DAC units, respectively; dn-Dm+n-1 are binary values corresponding to n+1 to m bits of the high-order segment DAC unit, respectively; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal.
The present application also provides an electronic device including: an analog to digital converter as claimed in any preceding claim.
The analog-to-digital converter comprises a digital calibration module, the digital calculation is used for calibrating the transcoding signal, an analog calibration array is not required to be additionally arranged, and the size of the analog-to-digital converter can be reduced; and, adopt error weight to calibrate and calculate, the fixed imbalance weight that the circuit module other than DAC module is out of order causes in the stated error weight, therefore, the calibration result is more accurate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a schematic diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application;
FIG. 1b is a schematic diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a capacitor array according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application;
fig. 6 is a flow chart of a digital calibration method of a successive approximation analog-to-digital converter according to an embodiment of the application.
Detailed Description
As in the background art, the size of the successive approximation type analog-to-digital converter is large due to the need to add an additional calibration capacitor array to achieve calibration.
The application provides a new successive approximation type analog-to-digital converter, which can realize calibration through digital calculation without adding an additional calibration capacitor array, and has simple realization mode.
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
Fig. 1a is a schematic diagram of a successive approximation type analog-to-digital converter according to an embodiment of the application.
The successive approximation analog-to-digital converter includes a DAC module 110, a comparator 120, a logic control module 130, and a digital calibration module 140.
The DAC module 110 is configured to sample an analog input signal Vin and convert Vin to an analog output voltage based on a reference voltage VREF of an analog-to-digital conversion process. The DAC module may include a capacitor array, a resistor array, and a corresponding switch array for controlling the connection state of the various elements within the array.
The comparator 120 has a first input terminal connected to the DAC module 110 and a second input terminal connected to a reference voltage VCM, for comparing the analog output voltage with the reference VCM voltage, and outputting a comparison result. The result of the comparison is either high or low, corresponding to binary numbers 1 or 0.
The logic control module 130 is connected to the output end of the comparator 120, and is configured to perform successive approximation control on the DAC module 110 according to the comparison result to obtain a corresponding transcoding signal. The logic control module 130 outputs a digital logic control signal to the DAC module 110 according to the comparison result currently output by the comparator 120, and controls the switch array in the DAC module 110, so that the comparator 120 outputs the comparison result again, and each comparison result corresponds to one bit in the finally output transcoding signal.
Specifically, the logic control module 130 may include a latch unit and a control unit, where the latch unit is configured to latch the comparison result output by the comparator 120 successively, and then output the comparison result corresponding to each stored bit in parallel as a transcoding signal after the approximation control process is finished; the control unit is configured to sequentially output digital logic control signals in parallel according to the stored comparison result in the latch unit, and perform successive approximation control on the switch array in the DAC module 110. For the N-bit DAC module 110, an N-bit binary transcoding signal is output through N switching and N comparison.
In some embodiments, the latch unit is an N-bit register. In an initial state, the highest bit of the latch unit is preset to be 1, and other bits are 0; the logic control module 130 outputs a corresponding N-bit logic control signal 1000 … … according to the stored data in the latch unit, controls the DAC module 110, if the comparator 120 outputs a comparison result of 0, the latch unit will have the highest bit definition of 0, and if the comparator 120 outputs a comparison result of 1, the highest bit latched by the latch unit will be kept as 1; then the second position of the N-bit register is 1, and a corresponding N-bit logic control signal is output, for example, when the highest bit comparison result is 1, the logic control signal output for the second time is 110 … … 0; the comparator 120 outputs a comparison result corresponding to the second bit and stores the comparison result; through the multiple approximation control, the comparison results of the comparators 120 are finally stored according to the bit sequence, and the transcoding signals are output in parallel.
The digital calibration module 140 is connected to the logic control module 130, and is configured to perform calibration calculation on the transcoding signal output by the logic control module 130 according to the weight error Δq of each bit, and output a calibrated transcoding signal, where Δq=w-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset To fix the offset weight, the offset weight W is fixed for each bit offset The same applies. Since the logic control module 130 will transcode signalsAnd the digital calibration module 140 receives the data of each bit of the transcoding signal at the same time and performs calibration calculation.
Due to mismatch of electronic components in the DAC module 110, the measured weight W and ideal weight W of each capacitor are caused idea With a certain deviation. Furthermore, the inventor further found that since the comparator and other circuit modules have certain offset problems in the actual conversion process, a fixed offset weight W is generated during the weight calibration offset 。
The capacitive array of fig. 2 is illustrated as an example. The capacitor array is composed of capacitors C1, C2, C3 and C4, wherein C1 is a reference capacitor, and a low-order capacitor is used for representing a high-order capacitor, so that the weight of each capacitor is obtained. The capacitors C2, C3 and C4 may be denoted by C1, and then the weights of the higher capacitors C2, C3 and C4 may be denoted by the weight of the capacitor C1.
C2＝αC1+offset＝C2 idea +ΔC2；
C3＝βC2+μC1+offset
＝βC2 idea +μC1+β(αC1-C2 idea )+(1+β)offset
＝αβC1+μC1+(1+β)offset
Wherein ΔC2 is the error amount of the capacitor C2, C2 idea For an ideal capacitance value of C2, offset is the offset that the comparator and other circuit blocks bring. The latter capacitance, when represented by the former capacitance, causes offset to accumulate. For example, C2 has an offset amount of offset, and the offset amount of C3 is increased by β times the offset amount of C2 on the basis of the fixed offset amount of offset, so that the total offset amount of C3 is (1+β) offset, where offset is the offset during measurement, and β offset is the offset introduced during calculation.
Therefore, the offset of each capacitor needs to be sequentially removed in the order from the low bit to the high bit, and accurate weights are finally obtained. For example, C2 is calibrated first, the offset of C2 is subtracted, c2=αc1; at this time, c3=βc2 when calculating C3 idea +μC1+β(αC1-C2 idea )+offset
＝αβC1+μC1+offset。
If C3 is used to represent C4, subtraction of the C3 offset is also required to avoid accumulation of C3 offset in the C4 calculation.
Therefore, if the offset is not calibrated every time, when the high-bit capacitance is represented by the low-bit capacitance, the offset of the low-bit capacitance is accumulated to the high-bit, and finally nonlinear errors are introduced to affect the calibration effect.
Thus, in this embodiment, the weight error Δq=w—w is employed idea -W offset The calibration of the weight is more accurate, the offset influence caused by other circuit elements except the DAC module 110 is eliminated, and the calibration accuracy can be improved. In addition, the calibration process is realized only through digital circuit calculation, compared with the calibration realized by adopting an analog circuit to compensate signals in the prior art, the calibration is easier to realize, the calibration hardware array is not required to be additionally added, and the size of the analog-to-digital converter can be reduced.
Fig. 1b is a schematic diagram of a successive approximation type analog-to-digital converter according to another embodiment of the present application. In this embodiment, the digital calibration module 140 is connected to the output of the comparator 120. Since the output end of the comparator 120 serially outputs the comparison result according to a certain sequence, the digital calibration module 140 sequentially performs the corresponding calibration calculation for each bit corresponding to the binary value of each bit. The digital calibration module 140 can synchronously perform calibration calculation in the successive approximation control process, so that the calibration calculation can be completed more quickly, and a calibrated transcoding signal is output.
Fig. 3 is a schematic structural diagram of a successive approximation analog-to-digital converter according to another embodiment of the present application.
In this embodiment, the DAC module 110 includes: the low-level segment DAC unit 111 and the high-level segment DAC unit 112 are connected through a bridge capacitor C0, where each bit of the high-level segment DAC unit 112 corresponds to the weight error Δq.
In this embodiment, the low-order DAC unit 111 has a small influence on conversion accuracy, and may be equivalent to an ideal DAC unit without calibration. The higher-order DAC unit 112 has a higher number of bits, and has a larger influence on the performance of analog-to-digital conversion, and requires weight calibration. In this embodiment, the weight of each bit in the high-order segment DAC unit 112 is represented by the bit corresponding to the low-order segment DAC unit.
The high-order segment DAC unit comprises at least one of an m-bit capacitor array or an m-bit resistor array, and the low-order segment DAC unit comprises at least one of an n-bit resistor array or an n-bit capacitor array. The entire analog-to-digital converter is capable of outputting an n+m bit binary code. In order for the low-order DAC cell 111 to have sufficient accuracy, n+.3 is typically set. In other embodiments, the number of bits of the low-level DAC unit 111 may be adjusted according to actual requirements.
The resistor array may include a plurality of resistors connected in series between a reference voltage VREF and a reference voltage VCM, each resistor terminal being connected by a switch to the lower plate of the bridge capacitor C0.
The capacitor array may include a plurality of capacitors each having an upper plate connected to a common terminal and a lower plate connected to the switch array. The capacitive array comprises at least one of a binary capacitive array, an equivalent capacitive array, or a segmented capacitive array.
The calibration calculation includes: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n+1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 )，D 0 ～D n-1 Binary values of 1 to n bits corresponding to the low-order segment DAC unit 111, D n ～D m+n-1 Binary values of n+1 to m+n bits corresponding to the high-order segment DAC unit 112, respectively; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal. In some embodiments of the present application, in some embodiments,the lowest order, n+1, of the high-order DAC cells is typically the ideal reference capacitance, and usually does not require calibration, thus Δq n May be 0. The capacitance corresponding to the other bits is typically an integer multiple of the reference capacitance.
Referring to fig. 4, a schematic structure of an analog-to-digital converter according to an embodiment of the application is shown.
In this embodiment, the low-order segment DAC unit 111 of the DAC module 110 includes an n-bit resistor array, and the high-order segment DAC unit 112 includes an m-bit capacitor array. The reference voltage VCM at one input of the comparator 120 is ground.
Specifically, the low-stage DAC unit 111 includes n resistors connected in series between the reference voltage VREF and the ground. The end points of the resistors are respectively connected with the switch S 0 、S 1 、……、And->Is connected to the lower plate of the bridge capacitor C0 to provide different segment voltages to the bridge capacitor C0 through different terminals. The successive approximation control can be performed on each switch according to a binary search algorithm, and corresponding segment reference voltages are output. The resistance values of the respective resistors may be the same or may be set in a regular manner. The low-stage DAC unit 111 employs a resistor array because of the small size of the resistor, and the size of the DAC module 110 can be reduced.
The high-level DAC unit 112 includes m capacitors, corresponding to m bits, as a weighted capacitor array, respectively capacitor C 1 、C 2 、C 4 、……、The upper plates of each capacitor are connected together as the output end of the high-level segment DAC unit 112, and the lower plates of each capacitor are connected to one of the input end Vin, the ground and the reference voltage VREF through a single-pole three-throw switch. Wherein C1 is the lowest capacitance thereof, which is the reference capacitance, typically the ideal unit capacitance. The ideal weights of other capacitors represented by C1 are 2, 4, 8, … … and 2 respectively m-3 、2 m-2 、2 m-1 . In other embodiments, the capacitance values in the capacitor array may be the same, or may be distributed in other ways. In other embodiments, the high-order DAC unit 112 includes at least one redundant capacitor in addition to the m-bit capacitor array, where the capacitance of the redundant capacitor is parallel to each capacitor in the m-bit capacitor array and equal to the capacitance of the capacitor corresponding to the lowest bit.
In this embodiment, the low-level DAC unit 111 is a resistor array, and the bridge capacitor C0 is equal to the capacitance of the lowest-level capacitor C1 in the high-level DAC unit 112, that is, c0=c1, so as to ensure linearity between the low-level DAC unit 111 and the high-level DAC unit 112. In other embodiments, the low-level DAC cell 111 may be a capacitor array, where the bridge capacitor C0 is sized to ensure that the bridge capacitor C0 is equivalent to the lowest capacitance of the high-level DAC cell 112 to the right when viewed from the right of the bridge capacitor C0.
Fig. 5 is a schematic structural diagram of a successive approximation type analog-to-digital converter according to an embodiment of the application.
In this embodiment, the calibration module 140 includes: a storage unit 141 and a calculation unit 142; the storage unit 141 is configured to store the fixed offset weight W offset The weight error Δq; the calculating unit 142 is configured to obtain the weight error Δq, perform calibration calculation on the transcoding signal according to the weight error Δq, and output a calibrated transcoding signal.
The calculating unit 142 is further configured to calculate a difference between the measured weight of the bridge capacitor C0 and the ideal weight to obtain the fixed offset weight W offset And according to the measured weight W, ideal weight W of each bit idea The fixed offset weight W offset Calculating the weight error delta q, and fixing the offset weight W offset And the weight error Δq is stored in the storage unit 141.
The fixed offset weightsW offset The bridge capacitor C0 can be obtained by measurement, and the specific method comprises the following steps:
the first stage: the lower electrode plates of all the capacitors of the DAC unit 112 are grounded by controlling the corresponding clamp of all the capacitors in the high-level DAC unit 112; closing switch K, shorting the two inputs of comparator 120 to each other, so that the upper plate of bridging capacitor C0 is connected to a reference voltage, which in this implementation is ground; and controls the switch array in the low-stage DAC unit 111 so that the potential output from the low-stage DAC unit 111 to the lower plate of the bridge capacitor C0 is a set voltage, so as to charge and hold the capacitor C0.
The set voltage is in the range of 0-VREF, and the value of the set voltage needs to be enough measurement margin above and below the set voltage in the process of measuring the offset through successive approximation. In one embodiment, the set voltage is VREF/2, which may be achieved by closing only the switch S 2n-1 A partial voltage VREF/2 is applied to the bottom plate of the bridge capacitor C0. In theory, the offset is not usually large, and the set voltage can take other values, such as VREF/4, VREF/8, etc.
And a second stage: the switch K is disconnected, the upper polar plate of the bridging capacitor C0 is disconnected from the reference voltage, successive approximation control is carried out on the switch array in the low-level segment DAC unit 111, the set voltage of the polar plate of the bridging capacitor C0 is redistributed in the low-level segment DAC unit 111, quantization is carried out through the low-level segment DAC unit, and finally the conversion code after analog-to-digital conversion is obtained, wherein the conversion code is the conversion code W after the set voltage is quantized by the low-level segment DAC unit 0 。
And a third stage: calculating the conversion code W of the bridging capacitor C0 0 And ideal weight W 0idea The difference value of the fixed offset weight W offset ，W offset ＝W 0 -W 0idea . Since the low-order DAC unit 111 is an ideal DAC unit, the weight error due to its own mismatch can be ignored, and thus the conversion code W 0 And ideal weight W 0idea The difference is considered to be due to fixation caused by other circuit modules such as comparatorsDetermining offset weight W offset 。
The method for obtaining the measurement weight W of each high-order capacitor in the high-order segment DAC unit 112 includes: connecting the capacitance lower plate to be calibrated to a reference voltage VREF, and grounding the capacitance lower plates corresponding to the bit above the bit to be calibrated, e.g. calibration C 2 At the time, C 4 And the lower polar plates of the capacitors are grounded; successive approximation control is performed on a capacitor corresponding to a bit below the bit to be calibrated and a switch array in the low-level DAC unit 111, so as to obtain a converted code after analog-digital conversion; and acquiring the measurement weight W according to the conversion code. Ideal weight W of each capacitor idea Depending on the capacitance size at the time of circuit design.
The measurement weight W and the ideal weight W idea Fix the detuning weight W offset All can be represented by binary codes and directly subtracted to obtain a weight error deltaq; or converting into decimal number and then calculating.
The measurement weight W may be calculated according to a binary weight calculation method from a conversion code obtained after successive approximation control, by measuring bit by bit from a low bit to a high bit for each bit capacitance in the high-bit segment DAC unit 112. And in the calculation process, the bit values of the low bits in the conversion code are calibrated by adopting the corresponding weight error delta q so as to avoid the accumulation of offset.
The analog-to-digital converter performs digital calibration calculation on the transcoding signal through the digital calibration module, and compared with analog signal compensation calibration, the analog-to-digital converter is easier to realize. In addition, in the digital calibration calculation process, weight errors caused by the imbalance of the circuit modules except the DAC module are eliminated, so that the calibration result is more accurate.
The embodiment of the application also provides electronic equipment comprising the successive approximation type analog-to-digital converter in any one of the above embodiments. The calibration of the analog-to-digital converter is completed through digital calibration calculation, so that the size of the analog-to-digital converter is smaller, and the internal integration level of the electronic equipment can be improved.
The embodiment of the application also provides a digital calibration method of the successive approximation type analog-to-digital converter.
Fig. 6 is a flow chart of a digital calibration method according to an embodiment of the application.
In this embodiment, the digital calibration method includes the steps of:
step S601, sampling an analog input signal by a DAC module and converting the analog input signal into an analog output voltage.
Step S602, comparing the analog output voltage with a reference voltage through a comparator, and outputting a comparison result.
And step S603, performing successive approximation control on the DAC module according to the comparison result, so that the comparator outputs the comparison result successively.
Step S604, outputting corresponding transcoding signals according to the comparison results after the successive approximation control is completed;
step S604, according to the weight error delta q of each bit, outputting a calibrated transcoding signal after calibration calculation, wherein delta q=W-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset To fix the offset weight, the offset weight W is fixed for each bit offset The same applies.
In one embodiment, the DAC module comprises: the low-level segment DAC unit and the high-level segment DAC unit are connected through a bridging capacitor C0; setting the weight error delta q for each bit of the high-order segment DAC single only; the low-order DAC unit can ignore the weight error due to the lower corresponding bit number, and is considered as an ideal DAC unit.
In one embodiment, the high-level segment DAC unit includes an m-bit capacitor array for obtaining the fixed offset weight W offset The method of (1) comprises: all lower polar plates of the capacitors of the high-level segment DAC unit are grounded, the upper polar plate of the bridging capacitor C0 is connected to a reference voltage, and a switch array in the low-level segment DAC unit is controlled, so that the potential of the lower polar plate of the bridging capacitor C0 is set voltage; will bridge the capacitor C0Disconnecting the upper polar plate from the reference voltage, and performing successive approximation control on a switch array in the low-level DAC unit to obtain a conversion code of the bridge capacitor C0 quantized by the low-level DAC unit; calculating the difference between the conversion code of the bridge capacitor C0 and the ideal weight as the fixed offset weight W offset . In some embodiments, the set voltage may be VREF/2, where VREF is an analog-to-digital converted reference voltage. In other embodiments, the set voltage may also be VREF/4 or VREF/8, etc.
In one embodiment, the method for acquiring the measurement weight of each high-order capacitor includes: connecting a capacitor lower polar plate to be calibrated to a reference voltage VREF, and grounding all capacitor lower polar plates corresponding to the bit above the bit to be calibrated; successive approximation control is carried out on a capacitor corresponding to a bit below the bit to be calibrated and a switch array of a DAC unit at a low-level segment to obtain a conversion code after analog-digital conversion; and acquiring the measurement weight according to the conversion code.
In one embodiment, the measurement weights are obtained bit by bit from low to high bits within the high-order segment DAC cell; and when the measurement weight is obtained according to the conversion code, the method further comprises calibrating the binary value of the low bit by using the corresponding weight error.
In one embodiment, the calibration calculation includes: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n +1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 )，D 0 ～D n-1 Binary values of 1 to n bits corresponding to the low-order segment DAC units, respectively; d (D) n ～D m+n -1 is a binary value of n+1 to m+n bits, respectively, corresponding to the high-order segment DAC cell; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal.
According to the digital calibration method, the fixed offset weight caused by offset of the circuit modules such as the comparator and the like except the DAC module of the successive approximation type analog-to-digital converter is calibrated, and the calibration accuracy is improved.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.
Claims (17)
1. A successive approximation analog-to-digital converter comprising:
a DAC module for sampling an analog input signal and converting the analog input signal to an analog output voltage, the DAC module comprising: the low-level segment DAC unit and the high-level segment DAC unit are connected through a bridging capacitor C0, wherein each bit of the high-level segment DAC unit is correspondingly provided with a weight error delta q;
the first input end of the comparator is connected to the DAC module, the second input end of the comparator is connected to a reference voltage, and the comparator is used for comparing the analog output voltage with the reference voltage and outputting a comparison result;
the logic control module is connected with the output end of the comparator and is used for performing successive approximation control on the DAC module according to the comparison result so that the comparator outputs the comparison result successively and outputs corresponding transcoding signals according to the comparison result after the successive approximation control is finished;
the digital calibration module is used for outputting a calibrated transcoding signal after performing calibration calculation on the comparison result or the transcoding signal according to the weight error deltaq of each bit, wherein deltaq=w-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset For fixing the offset weight, the offset weight W is fixed offset To adopt a low-level DAC singleThe difference between the conversion code quantized by the bridge capacitor C0 and the ideal weight of the bridge capacitor C0 is obtained.
2. The successive approximation analog-to-digital converter according to claim 1, wherein the calibration calculation comprises: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n+1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 )，D 0 ～D n-1 Binary values of 1 to n bits respectively corresponding to the low-order DAC units, D n ～D m+n-1 Binary values corresponding to n+1 to m+n bits of the high-order segment DAC unit, respectively; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal.
3. The successive approximation analog-to-digital converter according to claim 1, wherein the measurement weight W and the weight error Δq are obtained from a bit-by-bit measurement from a low bit to a high bit within the high-order segment DAC cell.
4. The successive approximation analog-to-digital converter according to claim 1, wherein the high-side DAC cell comprises at least one of an m-bit capacitor array or an m-bit resistor array, and the low-side DAC cell comprises at least one of an n-bit resistor array or an n-bit capacitor array.
5. The successive approximation analog-to-digital converter of claim 4, wherein the capacitor array comprises at least one of a binary capacitor array, an equivalent capacitor array, or a segmented capacitor array.
6. The successive approximation analog-to-digital converter of claim 4, wherein n is ≡3.
7. The successive approximation analog-to-digital converter according to claim 1, wherein the low-side DAC cell comprises an n-bit resistor array, the high-side DAC cell comprises an m-bit capacitor array, and the bridge capacitor C0 is equal to the capacitance of the lowest-side capacitor in the high-side DAC cell.
8. The successive approximation analog-to-digital converter according to claim 1, wherein the high-order segment DAC cell comprises an m-bit capacitor array and at least one redundant capacitor connected in parallel with a capacitor in the m-bit capacitor array and having a capacitance equal to a lowest-order capacitor in the m-bit capacitor array.
9. The successive approximation analog-to-digital converter according to claim 1, wherein the calibration module comprises: a storage unit and a calculation unit; the storage unit is used for storing the fixed offset weight W offset The weight error Δq; the calculating unit is used for obtaining the weight error delta q, carrying out calibration calculation on the transcoding signal according to the weight error delta q, and outputting the calibrated transcoding signal.
10. The successive approximation analog-to-digital converter according to claim 9, wherein the calculation unit is further configured to measure the weight W, the ideal weight W according to each bit idea The fixed offset weight W offset And calculating the weight error delta q and storing the weight error delta q in the storage unit.
11. A digital calibration method of a successive approximation analog-to-digital converter as set forth in claim 1, comprising:
sampling an analog input signal by a DAC module and converting the analog input signal into an analog output voltage;
comparing the analog output voltage with a reference voltage through a comparator, and outputting a comparison result;
according to the comparison result, successive approximation control is adopted for the DAC module, so that the comparator outputs the comparison result successively;
after successive approximation control is completed, outputting corresponding transcoding signals according to the comparison results;
according to the weight error delta q of each bit, the comparison result or the transcoding signal is calibrated and calculated to output a calibrated transcoding signal, wherein delta q=W-W idea -W offset W is the measurement weight of the corresponding bit, W idea Is of ideal weight, W offset To fix the offset weight, the offset weight W is fixed for each bit offset The same applies.
12. The digital calibration method of claim 11, wherein the DAC module comprises: the low-level segment DAC unit and the high-level segment DAC unit are connected through a bridging capacitor C0; the weight error deltaq is obtained only for each bit in the high-order segment DAC cell.
13. The digital calibration method of claim 12, wherein the high-side DAC cell comprises an m-bit capacitor array, and wherein the fixed offset weight W is obtained offset The method of (1) comprises: all lower polar plates of the capacitors of the high-level segment DAC unit are grounded, the upper polar plate of the bridging capacitor C0 is connected to a reference voltage, and a switch array in the low-level segment DAC unit is controlled, so that the potential of the lower polar plate of the bridging capacitor C0 is set voltage; disconnecting the upper polar plate of the bridging capacitor C0 from the reference voltage, and performing successive approximation control on a switch array in a low-level-section DAC unit to obtain a conversion code of the bridging capacitor C0 quantized by the low-level-section DAC unit; taking the difference value between the conversion code corresponding to the bridge capacitor C0 and the ideal weight as the fixed offset weight W offset 。
14. The digital calibration method of claim 13, wherein the method of obtaining the measurement weights W for each bit in the high-side DAC cell comprises: connecting a lower capacitor plate corresponding to a bit to be calibrated to a reference voltage, and grounding the lower capacitor plate corresponding to the bit above the bit to be calibrated; successive approximation control is carried out on a capacitor corresponding to a bit below the bit to be calibrated and a switch array of a DAC unit at a low-level segment to obtain a conversion code after analog-digital conversion; and acquiring the measurement weight W according to the conversion code.
15. The digital calibration method of claim 14, wherein the measurement weight W and weight error Δq are obtained bit by bit from low to high bits within the high-order segment DAC cell; and when the measurement weight W is obtained according to the conversion code, further comprising: and calibrating binary values of bits below the current calibration bit in the conversion code by using the corresponding weight error delta q.
16. The digital calibration method of claim 13, wherein the calibration calculation comprises: performing calibration calculation according to the weight error deltaq of each bit to obtain a calibrated transcoding signal value D, wherein D=D 0 ·2 0 +D 1 ·2 1 +...D n-1 ·2 n-1 +D n ·(2 n +Δq n )+D n+1 ·(2 n+1 +Δq n+1 )+...D m+n-1 ·(2 m+n-1 +Δq m+n-1 ) D0-Dn-1 are binary values corresponding to 1 to n bits of the low-order segment DAC unit, respectively; dn-Dm+n-1 are binary values corresponding to n+1 to m bits of the high-order segment DAC unit, respectively; and outputting the calibrated transcoding signal value D in a binary form to be a calibrated transcoding signal.
17. An electronic device, comprising: an analog to digital converter as claimed in any of claims 1 to 10.
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| CN114050827B (en) * | 2021-11-17 | 2024-03-19 | 东南大学 | Digital calibration method applied to capacitor three-section successive approximation analog-to-digital converter |
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