CN115589227B - Digital-to-analog conversion circuit with few digits instead of multiple digits and control method - Google Patents

Digital-to-analog conversion circuit with few digits instead of multiple digits and control method Download PDF

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CN115589227B
CN115589227B CN202211293224.7A CN202211293224A CN115589227B CN 115589227 B CN115589227 B CN 115589227B CN 202211293224 A CN202211293224 A CN 202211293224A CN 115589227 B CN115589227 B CN 115589227B
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analog conversion
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CN115589227A (en
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吕虹
宋自挺
郝铁军
李朝进
黄继露
易振波
秦明
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Guilin Stars Science And Technology Co ltd
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Guilin Stars Science And Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a digital-to-analog conversion circuit with few digits to replace a plurality of digits and a control method, which comprises a micro control unit, a high-order digital-to-analog conversion unit, a low-order digital-to-analog conversion unit, a calibration digital-to-analog conversion unit, an operation unit and a reference source to form the digital-to-analog conversion circuit, wherein the micro control unit is connected with the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit, the operation unit outputs analog voltage, an 8-bit digital-to-analog conversion chip DAC0832 is used for realizing a 16-bit resolution digital-to-analog conversion function, and a few-digit digital-to-analog conversion chip with stable performance, controllable supply chain and advantageous cost is used for replacing the multi-digit digital-to-analog conversion chip.

Description

Digital-to-analog conversion circuit with few digits instead of multiple digits and control method
Technical Field
The invention relates to the technical field of converting digital signals into analog signals, in particular to a digital-to-analog conversion circuit for realizing multi-bit chip resolution by using a few-bit digital-to-analog conversion chip.
Background
The digital-to-analog conversion chip is a chip commonly used in the field of precision measurement and control, and can convert data sent by a MPU (Microprocessor Unit) microprocessor into corresponding analog signals, wherein the digital-to-analog conversion chip has the common digits of 8 bits, 12 bits, 16 bits and 24 bits, and the resolution is sequentially 2 n . Generally, the more the number of chips, the higher the resolution, the higher the difficulty of chip design and manufacturing process, and manufacturing cost, the lower the stability, environmental adaptability, and reliability of chip performance, and the less secure and uncontrollable the supply chain.
The performance of the multi-bit digital-to-analog conversion chip is not stable enough in the occasion with strict environmental requirements, for example, in the application occasions such as special equipment with high requirements on electromagnetic compatibility, such as working temperature of-40-65 ℃ and EMC (Electromagnetic Compatibility), and the like, the performance of some digital-to-analog conversion chips is not stable enough; meanwhile, the high-order digital-to-analog conversion chip is an imported device, is easy to be blocked by a neck, and cannot ensure that a supply chain is independently controllable.
The design and manufacturing process difficulty and the manufacturing cost of the digital-to-analog conversion chip with few digits are relatively low, the chip performance is more stable, and the environmental adaptability and the reliability are more advantageous; the digital-to-analog conversion chip with fewer digits has higher localization degree, and the supply chain is safer and more controllable.
Therefore, the resolution of the multi-bit chip is realized by using the few-bit digital-to-analog conversion chip, and the method is very significant for improving the performance stability of products, reducing the cost and ensuring the autonomous controllability of a supply chain.
Disclosure of Invention
The invention aims to provide a digital-to-analog conversion circuit and a control method for replacing multi-bit digital-to-analog conversion by using a few-bit digital-to-analog conversion chip with stable performance, controllable supply chain and advantageous cost.
In a first aspect, the invention provides a digital-to-analog conversion circuit with fewer digits instead of multiple digits, which comprises a micro control unit, a high-order digital-to-analog conversion unit, a low-order digital-to-analog conversion unit, a calibration digital-to-analog conversion unit and an operation unit circuit, wherein the micro control unit is connected with the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit, and the operation unit is connected with the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit and outputs analog voltage;
and a micro control unit: the data line is used for sending data to the data lines of the 8-bit high-order digital-to-analog conversion chip, the 8-bit low-order digital-to-analog conversion chip and the 8-bit calibration digital-to-analog conversion chip and providing control logic output;
an arithmetic unit: converting the analog voltage converted by the 8-bit high-order digital-to-analog conversion chip into the low-order digital-to-analog conversion chip with the high-order channel coefficient of 1 and 8 bits1/2 of the converted analog voltage according to the high-order channel coefficient 8 The analog voltage obtained by conversion of the 8-bit calibration digital-to-analog conversion chip is subjected to superposition operation according to 1/2-1/4 of the low-bit channel coefficient, and the reference source reference voltage is subjected to superposition operation according to 1/2 of the high-bit channel coefficient, so that a bidirectional analog voltage which is in linear relation with 16-bit data formed by 8-bit high-bit data and 8-bit low-bit data is output;
reference source: providing digital-to-analog conversion reference voltages for the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip, providing reference voltages for the middle position offset of the operation unit, and enabling the output analog voltage of the operation unit to be 0 when the data to be digital-to-analog converted is the middle position after the middle position offset provides the reference voltages are set according to coefficients.
Further, the three digital-to-analog conversion reference voltages of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are connected together, and the output V of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit is H 、V L 、V R And reference source V ref According to the coefficient K in turn H 、K L 、K R 、K M An adder input end connected to the arithmetic unit, K H ：K L ：K R ：K M ＝2 n :1:(1/4～1/2)：(2 n-1 )；
The high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are respectively composed of an 8-order digital-to-analog conversion chip DAC0832 and an operational amplifier OP2277, the high-order digital-to-analog conversion chip U1-H and the operational amplifier U4A, the low-order digital-to-analog conversion chip U2-L and the operational amplifier U4B are correspondingly connected with the input pins Iout1 and Iout2 of the calibration digital-to-analog conversion chip U3-R and the operational amplifier U5B, the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip linearly convert 00-FFH data into current, and the corresponding operational amplifier converts the corresponding current into VH, VL and VR analog voltage output of 0-Vref; the output ends VH, VL and VR of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are respectively connected with one end of an input resistor R1 of the operation unit, one end of an adjustment potentiometer W1 and one end of an adjustment potentiometer W2.
Further, the high-order digital-to-analog conversion unit comprises;
the high-order digital-to-analog conversion unit comprises a high-order digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; the micro control unit independently writes data into an input register of the high-order digital-to-analog conversion chip;
the low-order digital-to-analog conversion unit comprises a low-order digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; the micro control unit independently writes data into an input register of the low-order digital-to-analog conversion chip;
the calibration digital-to-analog conversion unit comprises a calibration digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; and the micro control unit independently writes data into an input register of the calibration digital-to-analog conversion chip.
Further, the writing control lines of the data register of the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip are correspondingly connected with the micro control unit, and the micro control unit synchronously starts the three digital-to-analog conversion chips.
Further, the micro control unit comprises a DSP or ARM single chip microcomputer and a corresponding memory, wherein high-order 8-bit DATA 15-8 of a 16-bit I/O port of the single chip microcomputer is connected with a DATA line of a high-order digital-to-analog conversion chip U1-H, low-order 8-bit DATA 7-0 is connected with a DATA line of a low-order digital-to-analog conversion chip U2-L and a DATA line of a calibration digital-to-analog conversion chip U3-R, and the micro control unit is respectively used for sending 00-FFH DATA to be converted to the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip; the 3-bit W-H, W-L, W-R of the other I/O port of the singlechip is respectively connected with an input register write control line WR1 of the high-bit digital-to-analog conversion chip, the low-bit digital-to-analog conversion chip and the calibration digital-to-analog conversion chip U1-H, U2-L, U3-R and is respectively used for controlling writing and latching of data to be converted into an input register of the corresponding digital-to-analog conversion chip; the other bit SYN of the I/O port of the singlechip is commonly connected with a data register write control line WR2 of the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip U1-H, U2-L, U-R and is used for synchronously controlling the starting of the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip.
Further, the operation unit includes; the other end of the input resistor R1, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected, the other end of the feedback resistor R7 is connected with the output pin of the operational amplifier U5A to form a high-order channel of the proportional adder, and the ratio of R7 to R1 determines the output coefficient KH of the high-order digital-to-analog conversion unit; the other end of the adjusting potentiometer W1 is connected with one end of a resistor R2, the other end of the resistor R2, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a low-order channel of a proportional adder, and the ratio of the R7 to the sum of the resistance values of W1 and R2 determines the output coefficient KL of the low-order digital-to-analog conversion unit; the other end of the adjusting potentiometer W2 is connected with a resistor R3, the other end of the resistor R3, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a calibration channel of the proportional adder, and the ratio of the R7 to the sum of the resistance values of W2 and R3 determines the output coefficient KR of the calibration digital-to-analog conversion unit; the other end of the resistor R5 at the input end is connected with one end of the adjusting potentiometer W3, the other end of the W3, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected to form a neutral bias channel of the proportional adder, and the output coefficient KM of the neutral bias is determined by the ratio of R7 to the sum of the R5 and W3 resistance values; the + pin of the operational amplifier U5A is grounded, and the output pin is output after passing through a resistor R8; the proportional adder formed by the operation unit superimposes the input VH, VL, VR, vref according to vh+vl+kl+vr+kr+vref and outputs the analog voltage Vo.
In a second aspect, a digital-to-analog conversion line control method for replacing a plurality of bits with a few bits, for controlling a digital-to-analog conversion line replacing a plurality of bits with a few bits, includes: the device comprises a micro control unit, a high-order digital-to-analog conversion unit, a low-order digital-to-analog conversion unit and a calibration digital-to-analog conversion unit;
the output coefficient KM of the high-order digital-to-analog conversion unit is predetermined, and the output coefficients of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit, the calibration digital-to-analog conversion unit and the middle-order offset are set to meet K H ：K L ：K R ：K M ＝2 n :1:(1/4～1/2)：(2 n-1 ) The method comprises the steps of carrying out a first treatment on the surface of the The method is also used for acquiring the theory that the superposition value of the high-order digital-to-analog conversion unit and the low-order digital-to-analog conversion unit formed by the few-bit devices corresponds to the multi-bit data to be converted in advanceThe calibration value required by the value deviation is finally used for dynamically outputting the bidirectional analog voltage which has a linear relation with the data to be converted;
device parameters of a high-order channel are preselected to determine an output coefficient KH of a high-order digital-to-analog conversion unit;
the output coefficient KL of the low-order digital-to-analog conversion unit is preset to be 1/2 of the high-order by adjusting the device parameters of the low-order channel n ；
Setting the output coefficient KR of the calibration digital-to-analog conversion unit to be (1/2-1/4) of the low order KL by adjusting the device parameters of the low order channel in advance;
in the process of setting KH, KL and KR, the output coefficients of the high-order, low-order and digital-to-analog conversion units are compared and adjusted according to the unit resolution coefficient obtained by fitting, namely: according to the data to be converted of other channels, the data to be converted of the channel is set to 0, the midpoint is offset to 0, the data to be converted of the channel is changed from 0 to 2 8 -1) changing, measuring the output voltage Vo of the operation unit one by one, calculating the ratio of Vo to the data of the channel, and fitting to obtain the resolution coefficient of the digital-to-analog conversion unit as the comparison and setting basis;
after finishing the above KH, KL, KR setting, the data to be converted of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit, and the calibration digital-to-analog conversion unit are all set to be median, namely DH=2 n-1 -1、DL＝2 m-1 -1、DR＝2 m-1 -1, in this embodiment n=m=8, dh=dl=dr=7fh, starting up three DACs and measuring the output voltage Vo of the arithmetic unit; since the ratio of R7 to the sum of R5 and W3 determines the output coefficient KM of the median bias, vo is made to be 0 (not more than Vref in engineering: KH/2 by repeatedly adjusting the W3 resistance to adjust KM n+m+1 ) Thereafter, the output coefficient KM of the median bias is set to about 1/2 of KH.
Further, the method also comprises a method for acquiring calibration data DR in advance;
the micro control unit uses the high bit data DH, the low bit data DL and the temporary calibration data DR to make the data DR have a median of 2 7 -1=7fh is sent to the high-order, low-order and calibrated digital-analog conversion unit to output VH, VL and VR, and the analog voltage Vo is output after passing through the operation unit; the desired output voltage vq=vref KH (-dn+m/2) of the data dn+m to be digital-to-analog converted n+m +1/2); obtaining the difference delta 1=vq-Vo between Vq and Vo, and calculating the voltage value KDR=Vref×KR/2 represented by each bit of data of the digital-to-analog conversion channel according to the calibration n+m Calibration data adjustment amount Δdr=Δ1/KDR; the DR-DeltaDR is used to replace the original calibration data DR to repeat the above process until Delta1 is less than or equal to Vref KH/2 n+m The current DR is the correction data under the data Dn+m to be converted, all DR calibration data tables from 0000H to FFFFH of D16 are obtained through the method, and the calibration data are stored into the micro control unit by taking D16 as a pointer.
Further, when the data dn+m needs to be dynamically digital-to-analog converted, the micro control unit searches the pre-stored calibration data DR according to dn+m, writes and latches the n-bit high-bit data DH, the m-bit low-bit data DL, and the calibration data DR into the input registers of the corresponding digital-to-analog conversion units independently, synchronously starts each digital-to-analog conversion unit by synchronously providing the high-bit, low-bit, and calibration digital-to-analog conversion unit data register writing control signals, outputs the analog voltages VH, VL, VR, and outputs vo=vref KH (-dn+m/2) after superposition according to (VH kh+vl+vr+kr+vref KM) by the operation unit n+m +1/2) of the bi-directional analog voltage.
The beneficial effects of the invention are as follows: the 8-bit digital-to-analog conversion chip DAC0832 is used for realizing the 16-bit resolution digital-to-analog conversion function, and the fewer-bit digital-to-analog conversion chip with stable performance, controllable supply chain and advantageous cost is adopted to replace the multiple-bit lower-bit digital-to-analog conversion chip; the output coefficients of the digital-to-analog conversion units are preset, calibration data required by superposition output deviation of the high-order digital-to-analog conversion units and the low-order digital-to-analog conversion units are obtained in advance, and the calibration of the digital-to-analog conversion units is performed, so that the weight deviation of the output coefficients and the systematic deviation caused by conversion deviation of the high-order digital-to-analog conversion units can be corrected, and the accuracy can be ensured; the data to be calibrated is pre-stored and dynamically searched, so that the data to be calibrated does not need to be measured and obtained in the digital-to-analog conversion process, and the digital-to-analog conversion speed can be ensured.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic diagram of a digital-to-analog conversion circuit with fewer digits instead of more digits.
Fig. 2 is a schematic diagram of another digital-to-analog conversion circuit with fewer digits instead of more digits.
Fig. 3 is a flowchart of a method for acquiring calibration data DR in advance.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The following describes in detail the technical solutions provided by the embodiments of the present invention with reference to the accompanying drawings.
The circuit of the present invention is as follows (see fig. 1).
The circuit of the invention is an n+m digital-to-analog conversion circuit composed of an n-bit high-order digital-to-analog conversion chip, an m-bit low-order digital-to-analog conversion chip, an m-bit calibration digital-to-analog conversion chip and an operation unit, and outputs analog voltage. The input side of the line is externally connected with a digital interface of an MCU unit, and the MCU unit is provided with a memory. The MCU unit is a micro control unit.
N+m input data lines of the circuit come from the MCU unit, and n data lines (DH) of the high-order digital-to-analog conversion chip are connected with a high-order IO port of the MCU; the low-level digital-to-analog conversion chip and m data lines (DL and DR) of the calibration digital-to-analog conversion chip are connected with a low-level IO port of the MCU together;
the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip are provided with independent input registers, data registers and corresponding writing control lines;
the input register write control lines WR-H, WR-L, WR-R of the high-order, low-order and calibration digital-to-analog conversion chips are respectively connected with the corresponding IO ports of the MCU, and each input register can independently write data;
the high-order, low-order and calibration digital-to-analog conversion chip data register write control lines SYN are commonly connected with the corresponding IO ports of the MCU, so that three digital-to-analog conversion chips can be synchronously started;
the reference voltages of the three digital-to-analog conversion reference sources Vref are commonly connected;
the outputs VH, VL and VR of the high-order, low-order and calibration digital-to-analog conversion units are sequentially connected to the input end of an adder of the operation unit according to coefficients KH, KL and KR;
the reference source reference voltage is also connected to the other input end of the adder of the operation unit according to the coefficient KM, and the VH, VL, VR and Vref output analog voltages after passing through the operation unit.
Referring to fig. 2, the high-order, low-order and calibration digital-to-analog conversion units of the present embodiment all adopt 8-bit digital-to-analog conversion chips DAC0832 to form a 16-bit digital-to-analog conversion circuit, and the circuit of the present embodiment is as follows.
And a micro control unit: the micro control unit comprises a DSP or ARM single chip microcomputer and a corresponding memory, wherein high-order 8-bit DATA 15-8 of one 16-bit I/O port of the single chip microcomputer is connected with a DATA line of a high-order digital-to-analog conversion chip U1-H, and low-order 8-bit DATA 7-0 is connected with a DATA line of a low-order digital-to-analog conversion chip U2-L and a DATA line of a calibration digital-to-analog conversion chip U3-R, and is respectively used for sending 00-FFH DATA to be converted to each digital-to-analog conversion chip; the 3-bit W-H, W-L, W-R of the other I/O port of the singlechip is respectively connected with the write control line WR1 of the input register of the high-bit, low-bit and calibration digital-to-analog conversion chip U1-H, U2-L, U3-R and is respectively used for controlling writing and latching of data to be converted into the input register of the corresponding digital-to-analog conversion chip; the other bit SYN of the I/O port of the singlechip is commonly connected with a data register write control line WR2 of the high-order, low-order and calibration digital-to-analog conversion chips U1-H, U2-L, U-R and is used for synchronously controlling the starting of the 3 digital-to-analog conversion chips.
High order, low order, calibrated digital to analog conversion unit: the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are respectively formed by an 8-bit digital-to-analog conversion chip DAC0832 and an operational amplifier OP2277, the high-order digital-to-analog conversion chip U1-H and the operational amplifier U4A, the low-order digital-to-analog conversion chip U2-L and the operational amplifier U4B, the calibration digital-to-analog conversion chip U3-R and output pins Iout1 and Iout2 of the operational amplifier U5B are correspondingly connected with input pins and +Out, each digital-to-analog conversion chip linearly converts 00-FFH data into current, and each operational amplifier converts the corresponding current into VH, VL and VR analog voltage output of 0-Vref; the output ends VH, VL and VR of the high-order, low-order and calibration digital-to-analog conversion units are respectively connected with one end of an input resistor R1 of the operation unit, one end of an adjustment potentiometer W1 and one end of an adjustment potentiometer W2.
The high-order, low-order, calibration digital-to-analog conversion chip DAC0832 of this embodiment has independent input register and write control line WR1, data register and write control line WR2, and the purpose is to write and latch the data to be converted to the input registers of a plurality of DACs through the WR1 logic of giving the input register in a time-sharing manner, and to synchronously start a plurality of digital-to-analog conversion chips through the write logic WR2 of giving the data register at the same time, so as to ensure synchronous superposition and precision of the output signals of a plurality of digital-to-analog conversion chips. Other digital-to-analog conversion chips having independent input registers, data registers, and independent write control lines WR1, WR2 may also be used.
The high-order and low-order calibration digital-to-analog conversion unit is used for outputting corresponding analog voltages VH and VL according to data to be converted, and the calibration conversion unit is used for calibrating output deviation of the high-order and low-order calibration digital-to-analog conversion unit and deviation of each output coefficient so as to ensure the accuracy of the device.
Reference unit: the reference unit of the embodiment is a high-precision 4.96V voltage reference chip, and an output pin Vref is connected with the reference Vref of the high-order, low-order and calibration digital-to-analog conversion chips to provide a voltage reference for each digital-to-analog conversion chip; vref is also connected to one end of resistor R5 at one input of the arithmetic unit to provide the arithmetic unit with the desired neutral bias for superposition to perform the bi-directional bias calibration and to output the bi-directional simulation.
An arithmetic unit: the other end of the input resistor R1, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected, the other end of the feedback resistor R7 is connected with the output pin of the operational amplifier U5A to form a high-order channel of the proportional adder, the ratio of R7 to R1 determines the output coefficient KH of the high-order digital-to-analog conversion unit, and in the embodiment, R7= K, R1 =1K, KH is about-2; the other end of the adjusting potentiometer W1 is connected with a resistor R2, the other end of the resistor R2, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a low-order channel of a proportional adder, the ratio of the R7 to the sum of the resistance values of W1 and R2 determines the output coefficient KL of the low-order digital-to-analog conversion unit, and in the embodiment, R7= K, W1+R2 is about 256K, KL to about-1/128; the other end of the adjusting potentiometer W2 is connected with a resistor R3, the other end of the resistor R3, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a calibration channel of the proportional adder, and the ratio of the R7 to the sum of the resistance values of W2 and R3 determines the output coefficient KR of the calibration digital-to-analog conversion unit, wherein in the embodiment, R7= K, W2+R3 is about 512K, KR to about-1/256; the other end of the resistor R5 at the input end is connected with one end of the adjusting potentiometer W3, the other end of the W3, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected to form a neutral bias channel of the proportional adder, and the ratio of R7 to the sum of R5 and W3 determines the output coefficient KM of the neutral bias, wherein R7 = 2K, R5+W3 is about 2K, KM and about-1; the + pin of the operational amplifier U5A is grounded, and the output pin is output after passing through a resistor R8; the proportional adder formed by the operation unit superimposes the input VH, VL, VR, vref according to vh+vl+kl+vr+kr+vref and outputs the analog voltage Vo.
In a second aspect, a digital-to-analog conversion line control method using a few digits to replace a plurality of digits is used for predetermining an output coefficient KM of a high-order digital-to-analog conversion unit, and setting the high-order, low-order, calibrated digital-to-analog conversion unit and the output coefficient of a median offset to satisfy K H ：K L ：K R ：K M ＝2 n :1:(1/4～1/2)：(2 n-1 ) The method comprises the steps of carrying out a first treatment on the surface of the And the device is also used for acquiring a calibration value required by deviation between an overlapped value of a high-order digital-to-analog conversion unit and a theoretical value corresponding to multi-bit data to be converted in advance, and finally is used for dynamically outputting a bidirectional analog voltage in a linear relation with the data to be converted.
The device parameters of the high-order channel are preselected to determine the output coefficient KH of the high-order digital-to-analog conversion unit. In this example, R7 and R1 have resistances of 2K and 1K, respectively, and KM is determined to be-2.
The output coefficient KL of the low-order digital-to-analog conversion unit is preset to be 1/2 of the high-order by adjusting the device parameters of the low-order channel n . Because the output coefficient KH of the high-order digital-to-analog conversion unit is determined according to the parameters of the device, in order to ensure the accurate ratio of KH to KLSatisfy 2 n 1 relation, firstly accurately measuring the resolution coefficient of the analog voltage Vo output by the operation unit when the high-order digital-to-analog conversion unit independently outputs the high-order data to be converted, namely: the data to be converted of the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are set to 0, the middle point is biased to 0 (R5 is disconnected), and the data to be converted of the high-order digital-to-analog conversion unit is from 0 to 2 8 -1) incrementally measuring the output voltage Vo of the operation unit one by one, calculating the ratio of Vo to data, and fitting to obtain the resolution coefficient; in this embodiment, vref=4.96V, KH is about-2.0, and the resolution is about 0.0389V/bit. Correspondingly, the data to be converted of the high-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are set to 0, the midpoint is offset to 0, and the data to be converted of the low-order digital-to-analog conversion unit is from 0 to (2 8 -1) increasing, measuring the output voltage Vo of the operation unit one by one, calculating the ratio of Vo to data, and fitting to obtain a low-order resolution coefficient; since the ratio of R7 to the sum of the values of W1 and R2 determines the output coefficient KL of the low-order digital-to-analog conversion unit, the low-order resolution coefficient is repeatedly measured by repeatedly adjusting W1 according to the method until the ratio of the value to 1/2 of the high-order resolution coefficient n The deviation is within an acceptable range, i.e. the setting of the output coefficient KL of the low-order digital-to-analog conversion unit is completed, in this embodiment n=8, and KL is set to 1/256 of KH. The deviation of 1/256 of the low-order resolution from the high-order resolution is acceptable at 0.5-2% due to the subsequent calibration compensation of the calibration digital-to-analog conversion unit.
Similarly, the output coefficient KR of the calibration digital-to-analog conversion unit is set to (1/2-1/4) of the low order KL in advance by adjusting the device parameters of the low order channel. Setting the data to be converted of the high-order digital-to-analog conversion unit and the low-order digital-to-analog conversion unit to be 0, biasing the middle point to be 0, and calibrating the data to be converted of the digital-to-analog conversion unit from 0 to 2 8 -1) changing, measuring the output voltage Vo of the operation unit one by one, calculating the ratio of Vo to data, and fitting to obtain the resolution coefficient of the calibration digital-to-analog conversion unit; because the ratio of R7 to the sum of the resistance values of W2 and R3 determines the output coefficient KR of the low-order digital-to-analog conversion unit, the low-order resolution coefficient is repeatedly measured according to the method by repeatedly adjusting W2 until the deviation between the value and the (1/2-1/4) of the low-order resolution coefficient is within an acceptable range, and the adjustment of the output coefficient KR of the calibration digital-to-analog conversion unit is completed. KR can be calculated according to actual conditions1/2-1/4) to affect the calibration resolution and the calibratable range, and the calibration standard dividing rate is 1/2bit and the calibratable range is 2 when 1/2 is taken m 1/2 of (C); taking 1/4 time calibration mark dividing rate of 1/4bit and calibration range of 2 m 1/4 of (C); in this embodiment, m=8, KR is 1/2, the calibration resolution is 1/2bit, and the calibratable range is 128.
The output coefficient KM of the centering bias is about 1/2 of KH, so that the digital-to-analog conversion unit outputs 0 when the data to be converted is the median. After finishing the above KH, KL, KR setting, the data to be converted of the high-order, low-order, calibration digital-to-analog conversion units are all set to be median, namely DH=2 n-1 -1、DL＝2 m-1 -1、DR＝2 m-1 -1, in this embodiment n=m=8, dh=dl=dr=7fh, starting the DAC and measuring the output voltage Vo of the arithmetic unit; because the ratio of R7 to the sum of R5 and W3 determines the output coefficient KM of the median bias, vo is less than or equal to Vref KH/2 by repeatedly adjusting the W3 resistance to adjust KM n+m+1 vref=4.96V, KH =2, n=m=8, and vo is equal to or less than 4.96×2/2 in this embodiment 17 = (76 uV) complete tuning.
The present embodiment acquires the calibration data DR (see fig. 3) in advance as follows:
for 16-bit data D16 (e.g. 68 FDH) to be digital-to-analog converted, the micro control unit temporarily corrects the high-bit data DH (68H), the low-bit data DL (FDH) and the intermediate-bit data 2 7 -1=7fhdr is sent to the high-order, low-order and calibrated digital-analog conversion units to output VH, VL and VR, and the analog voltage Vo is output after passing through the operation unit; the desired output voltage vq=vref KH (-dn+m/2) of the data 68FDH to be digital-to-analog converted n+m +1/2) =4.96 (-2) × (-26877/65526+1/2) = -0.890896936953436V; obtaining the difference delta 1=vq-Vo between Vq and Vo, and correcting the voltage value KDR=Vref of KH/2 represented by each bit of data of the digital-to-analog conversion channel n+m+1 Calibration data adjustment amount Δdr=Δ1/KDR; the DR-DeltaDR is used to replace DR, and the above process is repeated until Delta1 is less than or equal to Vref KH/2 n +m The current DR is the correction data at 68 FDH; similarly, all DR calibration data tables from 0000H to FFFFFFH of D16 are obtained, and the calibration data are stored in the MCU unit by taking D16 as a pointer.
The present embodiment dynamically obtains the output analog voltage Vo as follows:
when data Dn+m is required to be dynamically digital-to-analog converted, the micro control unit searches pre-stored calibration data DR according to Dn+m, independently writes and latches n-bit high-bit data DH, m-bit low-bit data DL and calibration data DR into corresponding digital-to-analog conversion unit input registers, synchronously starts each digital-to-analog conversion unit through synchronous giving of high-bit, low-bit and calibration digital-to-analog conversion unit data register writing control signals, outputs analog voltages VH, VL and VR, and outputs vo=Vref KH (-Dn+m/2) after superposition according to (VH KH+VL+VR+Vr+Vref KM) through an operation unit n+m +1/2) of the bi-directional analog voltage.
The n+m-bit to-digital conversion data dn+m, the n-bit high-order to-be-converted data DH, the m-bit low-order to-be-converted data DL, and the m-bit low-order high-order to-be-converted data DL are:
Dn+m＝D(n+m-1)*2 (n+m-1) +D(n+m-2)*2 (n+m-2) +...+Dm*2 m +D(m-1)*2 (m-1) +D(m-2)*2 (m -2) +...D*2 0
DH＝DH(n-1)*2 (n-1) +DH(n-2)*2 (n-2) +。。。。。。+DH0*2 0
DL＝DL(m-1)*2 (m-1) +DL(m-2)*2 (m-2) +。。。。。。+DL0*2 0
DR＝DR(m-1)*2 (m-1) +DR(m-2)*2 (m-2) +。。。。。。+DR0*2 0
the VH, VL, VR are:
VH＝-Vref*DH/2 n ，VL＝-Vref*DL/2 m ，VR＝-Vref*DR/2 m
Vo＝VH*KH+VL*KL+VR*KR+Vref*KM
＝-Vref*DH*KH/2 n -Vref*DL*KL/2 m -Vref*DR*KR/2 m +Vref*KM
determining KH and finishing KH: KL: KR: km=2 n :1:(1/4～1/2)：(2 n-1 ) Setting, 1/2 of KL is taken by KR in the embodiment, and the method comprises the following steps:
Vo＝Vref*KH(-DH/2 n -DL/2 n+m -DR/2 n+m+1 +1/2)
DR calibrates the deviation of the whole process to make the numbervalue-DH/2 n -DL/2 n+m -DR/2 n+m+1 The superposition value of the converted output voltage is equal to the value-Dn+m/2 n+m The corresponding theoretical value of the output voltage is: output bi-directional analog voltage vo=vref KH (-dn+m/2) n+m +1/2), resolution of 1/2 n+m 。
In this embodiment, vref=4.96V, KH = -2, n=8, m=8, vo=4.96 (-2) (-D16/2) 16 +1/2)＝4.96*(D16/2 15 -1) resolution of 1/2 16 . When d16=0000h, vo= -4.96V; when d16=ffffh, vo≡4.96V.
The preset coefficient KH, KL, KR, KM and the pre-acquired calibration data DR process can be realized through an instrument and a computer auxiliary test tool based on the prior art.
In summary, according to the above method, the present embodiment uses the 8-bit DAC chip DAC0832 to implement the 16-bit resolution DAC function, so as to implement the implementation of using the fewer-bit DAC chip with stable performance, controllable supply chain and advantageous cost to replace the multiple-bit lower-bit DAC chip.
The calibration data required by the deviation from the theoretical value caused by the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the output coefficients are obtained in advance, and the calibration data is calibrated by the calibration digital-to-analog conversion unit, so that the deviation of the high-order DAC and the low-order DAC is calibrated, the deviation of the output coefficients is calibrated, and the accuracy of the device can be ensured; meanwhile, in the DAC conversion process, only stored calibration data and high-order and low-order data to be converted are required to be called out from a memory for instant output, so that the conversion speed of the DAC is ensured, and the time delay of acquisition deviation, calculation and calibration in the DAC conversion process in the prior art is shortened.
Compared with the prior art, the invention has the following characteristics:
the invention uses 1-piece n-bit, 2-piece m-bit digital-to-analog conversion chip and corresponding peripheral circuit to realize the function of n+m-bit digital-to-analog conversion chip, and the resolution is improved to 1/2 n+m ；
The calibration data are prestored and dynamically calibrated, so that the MCU time is less, the refreshing speed is faster, and the conversion resolution is ensured;
the high-order digital-to-analog chip is often an imported chip, the supply chain of the low-order digital-to-analog chip is safer and more independent and controllable, and the cost is advantageous; the low-bit number die core piece has mature and stable performance and can meet the severe working environment.

Claims (9)

1. The digital-to-analog conversion circuit with few digits to replace a plurality of digits is characterized by comprising a micro control unit, a high-order digital-to-analog conversion unit, a low-order digital-to-analog conversion unit, a calibration digital-to-analog conversion unit and an operation unit, wherein the micro control unit is connected with the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit, and the operation unit is connected with the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit and outputs analog voltage;
and a micro control unit: the data line is used for sending data to the data lines of the 8-bit high-order digital-to-analog conversion chip, the 8-bit low-order digital-to-analog conversion chip and the 8-bit calibration digital-to-analog conversion chip and providing control logic output;
an arithmetic unit: the analog voltage obtained by converting the 8-bit high-order digital-to-analog conversion chip is 1/2 of the high-order channel coefficient according to the analog voltage obtained by converting the 8-bit low-order digital-to-analog conversion chip 8 The analog voltage obtained by conversion of the 8-bit calibration digital-to-analog conversion chip is subjected to superposition operation according to 1/2-1/4 of the low-bit channel coefficient, and the reference source reference voltage is subjected to superposition operation according to 1/2 of the high-bit channel coefficient, so that a bidirectional analog voltage which is in linear relation with 16-bit data formed by 8-bit high-bit data and 8-bit low-bit data is output;
reference source: providing digital-to-analog conversion reference voltages for the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip, providing reference voltages for the middle position offset of the operation unit, and enabling the output analog voltage of the operation unit to be 0 when the data to be digital-to-analog converted is the middle position after the middle position offset provides the reference voltages are set according to coefficients.
2. A digital to analog conversion circuit for replacing a plurality of digits with a fewer number of digits according to claim 1, comprising:
the three digital-to-analog conversion reference voltages of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are connected together, and the output V of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit is H 、V L 、V R And reference source V ref According to the coefficient K in turn H 、K L 、K R 、K M An adder input end connected to the arithmetic unit, K H ：K L ：K R ：K M ＝2 n :1:(1/4～1/2)：(2 n-1 )；
The high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are respectively composed of an 8-order digital-to-analog conversion chip DAC0832 and an operational amplifier OP2277, the high-order digital-to-analog conversion chip U1-H and the operational amplifier U4A, the low-order digital-to-analog conversion chip U2-L and the operational amplifier U4B are correspondingly connected with the input pins Iout1 and Iout2 of the calibration digital-to-analog conversion chip U3-R and the operational amplifier U5B, the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip linearly convert 00-FFH data into current, and the corresponding operational amplifier converts the corresponding current into VH, VL and VR analog voltage output of 0-Vref; the output ends VH, VL and VR of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit and the calibration digital-to-analog conversion unit are respectively connected with one end of an input resistor R1 of the operation unit, one end of an adjustment potentiometer W1 and one end of an adjustment potentiometer W2.
3. A digital to analog conversion circuit for replacing a plurality of digits with a fewer digits according to claim 1, wherein said higher digital to analog conversion unit comprises;
the high-order digital-to-analog conversion unit comprises a high-order digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; the micro control unit independently writes data into an input register of the high-order digital-to-analog conversion chip;
the low-order digital-to-analog conversion unit comprises a low-order digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; the micro control unit independently writes data into an input register of the low-order digital-to-analog conversion chip;
the calibration digital-to-analog conversion unit comprises a calibration digital-to-analog conversion chip and is provided with an independent input register, a data register and a corresponding write-in control line; and the micro control unit independently writes data into an input register of the calibration digital-to-analog conversion chip.
4. A digital-to-analog conversion circuit using a small number of bits to replace a plurality of bits according to claims 1-3, wherein the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip data register write control line are connected with the micro control unit correspondingly, and the micro control unit synchronously starts the three digital-to-analog conversion chips.
5. The digital-to-analog conversion circuit with few digits to replace a plurality of digits according to claim 1, wherein the micro control unit comprises a DSP or ARM single chip microcomputer and a corresponding memory, the high-order 8-bit DATA 15-8 of one 16-bit I/O port of the single chip microcomputer is connected with the DATA line of the high-order digital-to-analog conversion chip U1-H, the low-order 8-bit DATA 7-0 is connected with the DATA line of the low-order digital-to-analog conversion chip U2-L and the calibration digital-to-analog conversion chip U3-R, and the micro control unit is respectively used for sending 00-FFH DATA to be converted to the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip; the 3-bit W-H, W-L, W-R of the other I/O port of the singlechip is respectively connected with an input register write control line WR1 of the high-bit digital-to-analog conversion chip, the low-bit digital-to-analog conversion chip and the calibration digital-to-analog conversion chip U1-H, U2-L, U3-R and is respectively used for controlling writing and latching of data to be converted into an input register of the corresponding digital-to-analog conversion chip; the other bit SYN of the I/O port of the singlechip is commonly connected with a data register write control line WR2 of the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip U1-H, U2-L, U-R and is used for synchronously controlling the starting of the high-order digital-to-analog conversion chip, the low-order digital-to-analog conversion chip and the calibration digital-to-analog conversion chip.
6. A digital to analog conversion circuit for replacing a plurality of digits with a fewer digits according to claim 1, wherein said operation unit comprises; the other end of the input resistor R1, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected, the other end of the feedback resistor R7 is connected with the output pin of the operational amplifier U5A to form a high-order channel of the proportional adder, and the ratio of R7 to R1 determines the output coefficient KH of the high-order digital-to-analog conversion unit; the other end of the adjusting potentiometer W1 is connected with one end of a resistor R2, the other end of the resistor R2, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a low-order channel of a proportional adder, and the ratio of the R7 to the sum of the resistance values of W1 and R2 determines the output coefficient KL of the low-order digital-to-analog conversion unit; the other end of the adjusting potentiometer W2 is connected with a resistor R3, the other end of the resistor R3, one end of a feedback resistor R7 and a pin of an operational amplifier U5A are connected to form a calibration channel of the proportional adder, and the ratio of the R7 to the sum of the resistance values of W2 and R3 determines the output coefficient KR of the calibration digital-to-analog conversion unit; the other end of the resistor R5 at the input end is connected with one end of the adjusting potentiometer W3, the other end of the W3, one end of the feedback resistor R7 and a pin of the operational amplifier U5A are connected to form a neutral bias channel of the proportional adder, the ratio of R7 to the sum of R5 and W3 resistance values determines the output coefficient KM of the neutral bias, and the plus pin of the operational amplifier U5A is grounded and the output pin is output after passing through the resistor R8; the proportional adder formed by the operation unit superimposes the input VH, VL, VR, vref according to vh+vl+kl+vr+kr+vref and outputs the analog voltage Vo.
7. A digital-to-analog conversion circuit control method for replacing a plurality of bits with a small number of bits, characterized by comprising: the device comprises a micro control unit, a high-order digital-to-analog conversion unit, a low-order digital-to-analog conversion unit and a calibration digital-to-analog conversion unit;
the output coefficient KM of the high-order digital-to-analog conversion unit is predetermined, and the output coefficients of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit, the calibration digital-to-analog conversion unit and the middle-order offset are set to meet K H ：K L ：K R ：K M ＝2 n :1:(1/4～1/2)：(2 n-1 ) The method comprises the steps of carrying out a first treatment on the surface of the The method is also used for obtaining in advance the calibration value required by the deviation between the superposition value of the high-order digital-to-analog conversion unit and the low-order digital-to-analog conversion unit formed by the few-bit devices and the theoretical value corresponding to the multi-bit data to be converted, and finally is used for dynamically outputting the data to be convertedA bi-directional analog voltage in a linear relationship;
device parameters of a high-order channel are preselected to determine an output coefficient KH of a high-order digital-to-analog conversion unit;
the output coefficient KL of the low-order digital-to-analog conversion unit is preset to be 1/2 of the high-order by adjusting the device parameters of the low-order channel n ；
Setting the output coefficient KR of the calibration digital-to-analog conversion unit to be (1/2-1/4) of the low order KL by adjusting the device parameters of the low order channel in advance;
in the process of setting KH, KL and KR, the output coefficients of the high-order, low-order and calibrated digital-to-analog conversion units are compared and adjusted according to the unit resolution coefficient obtained by fitting, namely: according to the data to be converted of other channels, the data to be converted of the channel is set to 0, the midpoint is offset to 0, the data to be converted of the channel is changed from 0 to 2 8 -1) changing, measuring the output voltage Vo of the operation unit one by one, calculating the ratio of Vo to the data of the channel, and fitting to obtain the resolution coefficient of the digital-to-analog conversion unit as the comparison and setting basis;
after finishing the above KH, KL, KR setting, the data to be converted of the high-order digital-to-analog conversion unit, the low-order digital-to-analog conversion unit, and the calibration digital-to-analog conversion unit are all set to be median, namely DH=2 n-1 -1、DL＝2 m-1 -1、DR＝2 m-1 -1, in this embodiment n=m=8, dh=dl=dr=7fh, starting up three DACs and measuring the output voltage Vo of the arithmetic unit; since the ratio of R7 to the sum of R5 and W3 determines the output coefficient KM of the median bias, vo is made to be 0 (not more than Vref in engineering: KH/2 by repeatedly adjusting the W3 resistance to adjust KM n+m+1 ) Thereafter, the output coefficient KM of the median bias is set to about 1/2 of KH.
8. A digital-to-analog conversion line control method using a small number of bits instead of a large number of bits according to claim 7, further comprising a method of acquiring calibration data DR in advance;
the micro control unit uses the high bit data DH, the low bit data DL and the temporary calibration data DR to make the data DR have a median of 2 7 -1=7fh is sent to the high-order, low-order and calibrated digital-analog conversion unit to output VH, VL and VR, and the analog voltage Vo is output after passing through the operation unit; to be treatedDigital-to-analog conversion data dn+m desired output voltage vq=vref KH (-dn+m/2) n+m +1/2); obtaining the difference delta 1=vq-Vo between Vq and Vo, and calculating the voltage value KDR=Vref×KR/2 represented by each bit of data of the digital-to-analog conversion channel according to the calibration n+m Calibration data adjustment amount Δdr=Δ1/KDR; the DR-DeltaDR is used to replace the original calibration data DR to repeat the above process until Delta1 is less than or equal to Vref KH/2 n+m The current DR is the correction data under the data Dn+m to be converted, all DR calibration data tables from 0000H to FFFFH of D16 are obtained through the method, and the calibration data are stored into the micro control unit by taking D16 as a pointer.
9. The digital-to-analog conversion line control method using a small number of bits instead of a large number of bits according to claim 7, further comprising a superposition method of digital-to-analog conversion dynamic calibration;
when the data Dn+m is required to be digital-to-analog converted, the micro control unit searches the pre-stored calibration data DR according to the Dn+m, independently writes and latches n-bit high-bit data DH, m-bit low-bit data DL and the calibration data DR into the input registers of the corresponding digital-to-analog conversion units, synchronously starts each digital-to-analog conversion unit by synchronously giving the writing control signals of the high-bit, low-bit and calibration digital-to-analog conversion unit data registers, outputs analog voltages VH, VL and VR, and presses the data into the corresponding digital-to-analog conversion unit through the operation unit
After superposition (vh+vl+kl+vr+vref+km), the output vo=vref+kh (-dn+m/2) n+m +1/2) of the bi-directional analog voltage.
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