CN113517891B - Linear calibration system and method applied to digital-to-analog converter - Google Patents
Linear calibration system and method applied to digital-to-analog converter Download PDFInfo
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- CN113517891B CN113517891B CN202111065960.2A CN202111065960A CN113517891B CN 113517891 B CN113517891 B CN 113517891B CN 202111065960 A CN202111065960 A CN 202111065960A CN 113517891 B CN113517891 B CN 113517891B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
Abstract
The invention discloses a linear calibration system and method applied to a digital-to-analog converter, and relates to the technical field of electronics. The linear calibration system comprises a digital circuit and an analog circuit, wherein the analog circuit comprises an auxiliary digital-to-analog converter, a main digital-to-analog converter and a voltage comparator, and the voltage comparator is used for determining a device deviation voltage information signal corresponding to the main digital-to-analog converter based on the first voltage signal and a reference signal; the digital circuit is used for determining a calibration code value corresponding to the main digital-to-analog converter based on the device offset voltage information signal, and the auxiliary digital-to-analog converter calibrates the main digital-to-analog converter based on the calibration code value; the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode, so that the digital-to-analog converter can be calibrated without increasing the area of the core part of a device, and the performance of the digital-to-analog converter is optimized.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a linear calibration system and method for a digital-to-analog converter.
Background
A Digital to Analog converter (DAC) is a circuit that converts a Digital signal into an Analog signal. With the increasing requirement of the modern society on information capacity, electronic systems put forward higher requirements on data transmission rate, and the DAC has wide application prospects in the fields of wireless and wired communication, digital signal processing, measurement and control instruments and meters, radars and the like.
The requirement for the precision of the digital-to-analog converter is higher and higher along with the development of an industrial control system, and at present, in order to realize the high-precision digital-to-analog converter, the precision of the digital-to-analog converter is generally improved by increasing the area of a device. For the resolution of the digital-to-analog converter, the resolution is increased by 1 bit, the area of the core part of the device needs to be increased by 4 times, the increase of the area can lead to the complexity of the routing of the device, the parasitic capacitance of the routing is large, the precision of the high-precision digital-to-analog converter is limited, and the matching precision of the process has certain limit performance, and the digital-to-analog converter circuit with higher precision cannot be realized only by increasing the area of the device to improve the matching precision.
Disclosure of Invention
The invention aims to provide a linear calibration system and method applied to a digital-to-analog converter, so as to solve the problem that the precision of the digital-to-analog converter is improved by increasing the area of a device at present, and the increase of the area causes the routing of the device to be complex, so that the speed of the high-precision digital-to-analog converter is limited.
In a first aspect, the present invention provides a linear calibration system applied to a digital-to-analog converter, the linear calibration system includes a digital circuit and an analog circuit, the analog circuit includes an auxiliary digital-to-analog converter, a main digital-to-analog converter and a voltage comparator, wherein an output terminal of the auxiliary digital-to-analog converter is connected to an input terminal of a compensation current of the main digital-to-analog converter, an output terminal of the main digital-to-analog converter is connected to an input terminal of the voltage comparator, a first output terminal of the digital circuit is connected to an input terminal of the auxiliary digital-to-analog converter, a second output terminal of the digital circuit is connected to an input terminal of the main digital-to-analog converter, and an input terminal of the digital circuit is connected to an output terminal of the voltage comparator;
the main digital-to-analog converter is used for receiving a calibration control signal transmitted by the digital circuit in a calibration mode, receiving a calibration current value transmitted by the auxiliary digital-to-analog converter and determining a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value;
and the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode.
Under the condition of adopting the technical scheme, the main digital-to-analog converter is used for receiving the calibration control signal transmitted by the digital circuit in the calibration mode, receiving the calibration current value transmitted by the auxiliary digital-to-analog converter and determining a first voltage signal based on the calibration current value and the calibration control signal; the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value; the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode, so that the calibration and compensation of the precision of the main digital-to-analog converter are realized, the calibration of the digital-to-analog converter can be realized without increasing the area of the core part of a device, the optimization of the performance of the digital-to-analog converter is realized, and the precision of the digital-to-analog converter can be further improved.
In one possible implementation, the digital circuit includes a correction logic unit and a lookup unit; the output end of the correction logic unit is connected with the input end of the search unit; the input end of the auxiliary digital-to-analog converter is connected with the output end of the searching unit, and the output end of the voltage comparator is connected with the input end of the correction logic unit; the digital circuit also comprises a successive approximation calibration logic unit, wherein the input end of the successive approximation calibration logic unit is connected with the output end of the voltage comparator, and the output end of the successive approximation calibration logic unit is connected with the input end of the searching unit;
the main digital-to-analog converter is used for receiving a calibration control signal transmitted by the digital circuit in a calibration mode, receiving a calibration current value transmitted by the auxiliary digital-to-analog converter, and determining a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator is configured to determine, based on the first voltage signal and the reference signal, the device offset voltage information signal corresponding to the main digital-to-analog converter corresponding to a preset period through a successive approximation calibration logic unit in cooperation with the correction logic unit, convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, and send the calibration code value to the search unit;
the auxiliary digital-to-analog converter is used for receiving the calibration code value transmitted by the searching unit in a normal mode and determining the calibration current value based on the calibration code value;
and the main digital-to-analog converter is also used for receiving the calibration current value in a normal mode and completing the error compensation of the main digital-to-analog converter based on the calibration current value.
In a possible implementation manner, the linear calibration system further includes a control unit respectively connected to the input end of the correction logic unit, the input end of the search unit, and the input end of the main digital-to-analog converter; the main digital-to-analog converter comprises a plurality of units to be calibrated;
the control unit is used for generating a calibration control signal corresponding to the unit to be calibrated in a calibration mode and controlling the correction logic unit to receive the device deviation voltage information signal output by the voltage comparator;
the correction logic unit is used for determining the calibration code value based on the device offset voltage information signal and sending the calibration code value to the searching unit;
the searching unit is used for inputting the calibration code value to the auxiliary digital-to-analog converter;
the auxiliary digital-to-analog converter determines the calibration current value based on the calibration code value;
the control unit is further configured to perform error compensation on the main dac based on the calibration code value in the lookup unit in a normal mode.
In one possible implementation, the reference signal includes a reference resistance signal and a reference voltage signal; the analog circuit further comprises a reference resistance unit and a reference voltage unit, wherein the output end of the reference voltage unit and the output end of the reference resistance unit are both connected with the input end of the voltage comparator; the reference resistance unit is used for providing a reference resistance signal;
the reference voltage unit is used for providing a reference voltage signal.
In one possible implementation manner, the main digital-to-analog converter includes a first decoding logic unit, a low-stage resistor array and a high-stage resistor array connected in pairs; the low-section resistor array is a low-section resistor unit to be calibrated; the high-section resistor array comprises a plurality of high-section resistor units to be calibrated;
in a calibration mode, the auxiliary digital-to-analog converter is configured to send the calibration current value to the main digital-to-analog converter; the main digital-to-analog converter is used for determining a first voltage signal based on the calibration current value and the calibration control signal;
under the condition of calibrating the unit to be calibrated of the low-section resistance or the unit to be calibrated of the high-section resistance, the voltage comparator is used for determining the device deviation voltage information signal corresponding to the unit to be calibrated corresponding to a preset period based on the first voltage signal, the reference resistance signal and the reference voltage signal;
the calibration logic unit is used for determining a target calibration current value based on the device offset voltage information signal, determining the calibration code value based on the target calibration current value, and inputting the calibration code value to the search unit;
the auxiliary digital-to-analog converter is used for receiving the calibration code value transmitted by the searching unit in a normal mode and determining the calibration current value based on the calibration code value;
and the main digital-to-analog converter is also used for receiving the calibration current value in a normal mode and completing the calibration of the low-section resistance unit to be calibrated or the high-section resistance unit to be calibrated based on the calibration current value.
In a possible implementation manner, the voltage comparator is configured to determine, by a successive approximation calibration logic unit, the device offset voltage information signal corresponding to a plurality of units to be calibrated corresponding to a preset period based on the first voltage signal and the reference signal, and includes:
the voltage comparator is used for determining the device deviation voltage information signals corresponding to the units to be calibrated corresponding to a preset period through a successive approximation calibration logic unit based on the first voltage signal, the reference resistance signal and the reference voltage signal.
In one possible implementation manner, the low-segment resistor array includes a lowest resistor unit, and the lowest resistor unit includes a tri-state switch, a first resistor, and a second resistor connected in series in this order.
In a possible implementation manner, the reference resistance unit and one branch of the high-segment resistance array have the same structure, and a resistance value corresponding to the reference resistance unit is smaller than a resistance value corresponding to the high-segment resistance array.
In a possible implementation manner, the linear calibration system further includes a second decoding logic unit, an input end of which is connected to the output end of the control unit, and an output end of which is connected to the input end of the search unit.
In a second aspect, the present invention further provides a nonlinear calibration method applied to a digital-to-analog converter, which is applied to any one of the linear calibration systems applied to a digital-to-analog converter in the first aspect, and the method includes:
controlling the main digital-to-analog converter to receive a calibration control signal transmitted by the digital circuit in a calibration mode and receive a calibration current value transmitted by the auxiliary digital-to-analog converter, and determining a first voltage signal based on the calibration current value and the calibration control signal;
controlling the voltage comparator to determine a device offset voltage information signal corresponding to the main digital-to-analog converter under the coordination of the digital circuit based on the first voltage signal and a reference signal, and converting the device offset voltage information signal into a calibration code value corresponding to the calibration current value;
controlling the digital circuit to store the calibration code value;
controlling the auxiliary digital-to-analog converter to calibrate the main digital-to-analog converter based on the calibration code value;
and controlling the auxiliary digital-to-analog converter to carry out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode.
The beneficial effects of the linear calibration method applied to the digital-to-analog converter provided by the second aspect are the same as the beneficial effects of the linear calibration system applied to the digital-to-analog converter described in the first aspect or any possible implementation manner of the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram illustrating a linear calibration system applied to a digital-to-analog converter according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram illustrating another linear calibration system applied to a digital-to-analog converter according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram illustrating a partial structure of a main digital-to-analog converter according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram illustrating a tristate switch according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating a circuit structure of a resistor divider during calibration according to an embodiment of the present disclosure;
FIG. 6 is a circuit schematic diagram of a calibration loop provided by an embodiment of the present application;
fig. 7 is a schematic diagram illustrating a core portion circuit structure of an auxiliary digital-to-analog converter according to an embodiment of the present application;
FIG. 8 is a schematic structural diagram illustrating a linear calibration system in a normal operating state according to an embodiment of the present disclosure;
fig. 9 is a flowchart illustrating a linear calibration method applied to a digital-to-analog converter according to an embodiment of the present disclosure.
Description of the drawings:
10-a digital circuit; 20-analog circuitry; 201-an auxiliary digital-to-analog converter; 202-a main digital-to-analog converter; 203-a voltage comparator; 101-a correction logic unit; 102-a lookup unit; 103-a control unit; 204-a reference resistance unit; 205-reference voltage unit; 202 a-a first decode logic unit; 202 b-low section resistor array; 202 c-high section resistor array; 104-second decode logic unit.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
Fig. 1 shows a schematic structural diagram of a linear calibration system applied to a digital-to-analog converter according to an embodiment of the present application, as shown in fig. 1, the linear calibration system includes a digital circuit 10 and an analog circuit 20, the analog circuit 20 includes an auxiliary digital-to-analog converter 201, a main digital-to-analog converter 202 and a voltage comparator 203, wherein an output terminal of the auxiliary digital-to-analog converter 201 is connected to a compensation current input terminal of the main digital-to-analog converter 202, an output terminal of the main digital-to-analog converter 202 is connected to an input terminal of the voltage comparator 203, a first output terminal of the digital circuit 10 is connected to an input terminal of the auxiliary digital-to-analog converter 201, a second output terminal of the digital circuit 10 is connected to an input terminal of the main digital-to-analog converter 202, and an input terminal of the digital circuit 10 is connected to an output terminal of the voltage comparator 203;
the main digital-to-analog converter 202 is configured to receive, in a calibration mode, a calibration control signal transmitted by the digital circuit 10, receive a calibration current value transmitted by the auxiliary digital-to-analog converter 201, and determine a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator 203 is configured to determine, based on the first voltage signal and the reference signal, a device offset voltage information signal corresponding to the main dac under the cooperation of the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, where the digital circuit is configured to store the calibration code value, and the auxiliary dac is configured to calibrate the main dac based on the calibration code value;
the auxiliary dac 201 is further configured to perform error compensation on the main dac based on the calibration code value sent by the digital circuit in a normal mode.
In summary, with the linear calibration system applied to the digital-to-analog converter provided in the embodiment of the present application, the main digital-to-analog converter is configured to receive the calibration control signal transmitted by the digital circuit in the calibration mode, receive the calibration current value transmitted by the auxiliary digital-to-analog converter, and determine the first voltage signal based on the calibration current value and the calibration control signal; the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value; the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode, so that the calibration and compensation of the precision of the main digital-to-analog converter are realized, the calibration of the digital-to-analog converter can be realized without increasing the area of the core part of a device, the optimization of the performance of the digital-to-analog converter is realized, and the precision of the digital-to-analog converter can be further improved.
Fig. 2 shows a schematic structural diagram of another linear calibration system applied to a digital-to-analog converter according to an embodiment of the present application, as shown in fig. 2, the linear calibration system includes a digital circuit 10 and an analog circuit 20, the analog circuit 20 includes an auxiliary digital-to-analog converter 201, a main digital-to-analog converter 202 and a voltage comparator 203, wherein an output terminal of the auxiliary digital-to-analog converter 201 is connected to a compensation current input terminal of the main digital-to-analog converter 202, an output terminal of the main digital-to-analog converter 202 is connected to an input terminal of the voltage comparator 203, a first output terminal of the digital circuit 10 is connected to an input terminal of the auxiliary digital-to-analog converter 201, a second output terminal of the digital circuit 10 is connected to an input terminal of the main digital-to-analog converter 202, and an input terminal of the digital circuit 10 is connected to an output terminal of the voltage comparator 203;
the main digital-to-analog converter 202 is configured to receive, in a calibration mode, a calibration control signal transmitted by the digital circuit 10, receive a calibration current value transmitted by the auxiliary digital-to-analog converter 201, and determine a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator 203 is configured to determine, based on the first voltage signal and the reference signal, a device offset voltage information signal corresponding to the main dac under the cooperation of the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, where the digital circuit is configured to store the calibration code value, and the auxiliary dac is configured to calibrate the main dac based on the calibration code value;
the auxiliary dac 201 is further configured to perform error compensation on the main dac based on the calibration code value sent by the digital circuit in a normal mode.
Alternatively, the main digital-to-analog converter may be a resistive type digital-to-analog converter and the auxiliary digital-to-analog converter may be a current type digital-to-analog converter.
Optionally, the digital circuit further includes a successive approximation calibration logic unit, an input end of the successive approximation calibration logic unit is connected to an output end of the voltage comparator, and an output end of the successive approximation calibration logic unit is connected to an input end of the search unit;
the voltage comparator is configured to determine, by a successive approximation calibration logic unit, the device offset voltage information signals corresponding to a plurality of units to be calibrated corresponding to a preset period based on the first voltage signal and the reference signal, and send the device offset voltage information signals to the calibration logic unit.
Optionally, referring to fig. 2, the digital circuit 10 includes a correction logic unit 101 and a lookup unit 102; the output end of the correction logic unit 101 is connected with the input end of the search unit 102; the input end of the auxiliary digital-to-analog converter 201 is connected with the output end of the search unit 102, and the output end of the voltage comparator 203 is connected with the input end of the correction logic unit 101;
the main digital-to-analog converter 202 is configured to receive, in a calibration mode, a calibration control signal transmitted by the digital circuit 10, and receive a calibration current value transmitted by the auxiliary digital-to-analog converter 201, and determine a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator 203 is configured to determine, based on the first voltage signal and the reference signal, the device offset voltage information signal corresponding to the main digital-to-analog converter corresponding to a preset period through a successive approximation calibration logic unit in cooperation with the correction logic unit, convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, and send the calibration code value to the search unit;
the auxiliary digital-to-analog converter 201 is configured to receive the calibration code value transmitted by the lookup unit in a normal mode, and determine the calibration current value based on the calibration code value;
the main dac 202 is further configured to receive the calibration current value in a normal mode, and perform error compensation on the main dac 202 based on the calibration current value.
Optionally, the voltage at the output end of the main digital-to-analog converter is connected to the output end of the reference resistor, and the connected node is a common mode node connected to the input end of the voltage comparator.
Optionally, referring to fig. 2, the linear calibration system further includes a control unit 103 respectively connected to the input terminal of the correction logic unit 101, the input terminal of the search unit 102, and the input terminal of the main digital-to-analog converter 202; the main digital-to-analog converter 202 comprises a plurality of units to be calibrated;
the control unit 103 is configured to generate a calibration control signal corresponding to the unit to be calibrated in a calibration mode, and control the correction logic unit 101 to receive the device offset voltage information signal output by the voltage comparator 203;
the correction logic unit 101 is configured to determine the calibration code value based on the device offset voltage information signal, and send the calibration code value to the lookup unit 102;
the lookup unit 102 is configured to input the calibration code value to the auxiliary digital-to-analog converter 201;
the auxiliary digital-to-analog converter 201 determines the calibration current value based on the calibration code value;
the control unit 103 is further configured to perform error compensation on the main dac 202 in the normal mode based on the calibration code value in the lookup unit 102.
Optionally, the reference signal includes a reference resistance signal and a reference voltage signal; referring to fig. 2, the analog circuit 20 further includes a reference resistance unit 204 and a reference voltage unit 205, and an output terminal of the reference resistance unit 205 and an output terminal of the reference resistance unit 204 are both connected to an input terminal of the voltage comparator 203. The reference resistance unit 204 is used for providing a reference resistance signal; the reference voltage unit 205 is used for providing a reference voltage signal.
Optionally, the unit to be calibrated is also a resistor array in the main digital-to-analog converter.
Optionally, referring to fig. 2, the linear calibration system further includes a second decoding logic unit 104 having an input terminal connected to the output terminal of the control unit 103 and an output terminal connected to the input terminal of the search unit 102.
Optionally, referring to fig. 2, the main dac 202 includes two connected first decoding logic units 202a, a low-stage resistor array 202b, and a high-stage resistor array 202 c; the low-section resistor array 202b is a unit to be calibrated for low-section resistors; the high-section resistor array 202c comprises a plurality of high-section resistor units to be calibrated; the unit to be calibrated comprises at least one unit to be calibrated for low-section resistance and/or at least one unit to be calibrated for high-section resistance.
In the low-band resistor array (LSB CELL) and the high-band resistor array (MSB CELL), the low-band resistor array refers to a Least Significant Bit (LSB) resistor array, and the high-band resistor array refers to a Most Significant Bit (MSB) resistor array.
In a binary number, the MSB is the highest weighted bit. Similar to the leftmost digit in a decimal number. Typically, the MSB is located at the leftmost side of the binary number and the LSB is located at the rightmost side of the binary number. That is, in the present application, the low-section resistance array and the high-section resistance array refer to processing according to the least significant bit or processing according to the most significant bit during data processing. The low resistance to be calibrated cell refers to a resistance cell processed according to the least significant bit, and the high resistance to be calibrated cell refers to a resistance cell processed according to the most significant bit.
In a calibration mode, the auxiliary digital-to-analog converter is configured to send the calibration current value to the main digital-to-analog converter; the main digital-to-analog converter is used for determining a first voltage signal based on the calibration current value and the calibration control signal;
under the condition of calibrating the unit to be calibrated of the low-section resistance or the unit to be calibrated of the high-section resistance, the voltage comparator is used for determining the device deviation voltage information signal corresponding to the unit to be calibrated corresponding to a preset period based on the first voltage signal, the reference resistance signal and the reference voltage signal;
the calibration logic unit is used for determining a target calibration current value based on the device offset voltage information signal, determining the calibration code value based on the target calibration current value, and inputting the calibration code value to the search unit;
the auxiliary digital-to-analog converter is used for receiving the calibration code value transmitted by the searching unit in a normal mode and determining the calibration current value based on the calibration code value;
and the main digital-to-analog converter is also used for receiving the calibration current value in a normal mode and completing the calibration of the low-section resistance to-be-calibrated unit or the high-section resistance to-be-calibrated unit based on the calibration current value.
Optionally, the voltage comparator is configured to determine, by a successive approximation calibration logic unit, the device offset voltage information signal corresponding to the multiple units to be calibrated corresponding to a preset period based on the first voltage signal, the reference resistance signal, and the reference voltage signal.
Optionally, the lookup unit may include a lookup table, where the lookup table stores a plurality of calibration code values corresponding to the unit to be calibrated, and the calibration code value may include a deviation between a sum of the low-segment resistances and the high-segment resistances, and may also include a deviation between the high-segment resistances and the high-segment resistances.
Optionally, the main digital-to-analog converter may read the calibration code value in the lookup table in a normal operating state, and send the calibration code value and the calibration code value of the low-stage sum to the main digital-to-analog converter after subtraction, and compensate for the deviation between the resistors in a current manner, thereby achieving the purpose of high-precision digital-to-analog call-up.
Optionally, the low-section resistor (LSB) array (R2R array) of the main dac may be L bits, and the high-section thermometer-coded resistor array, that is, the high-section resistor (MSB) array, is M bits. Wherein VREFP is the positive reference voltage, VREFN is the negative reference voltage.
Since the resistance is not biased, the output of the low-section sum is expressed as
Output of more than one high section
Reduce one by one
When calibrating, it is necessary to connect all the resistors in the low segment to VREFP and then
And then compared with a reference device.
Further, the sum of the voltages of the low-section resistor array is weighted more heavily than the sum of the voltages of the low-section resistor arrayThe weight of the segment is less than 1LSB, and the total of the low-segment devices plus 1LSB needs to be compared with the reference device during calibration. When calibrating the high section, directly comparing with the reference device, after calibration, comparing the low section sum plus 1LSB and all high section resistor arrays with the reference resistor part, the total number of the calibrated devices is
And (4) respectively.
Optionally, the low-section resistor array includes a lowest resistor unit, and the lowest resistor unit includes a tri-state switch, a first resistor, and a second resistor connected in series in sequence.
Fig. 3 shows a circuit diagram of a partial structure of a main digital-to-analog converter according to an embodiment of the present application, as shown in fig. 3, where the low-section resistor array (LSB CELL) is L bits, the high-section resistor array (MSB CELL) is M bits, a switch bc is added at the lowest resistor that is normally connected to VREFN, and when an error of a low-section device is calibrated, the switch bc is connected to VREFP, and at this time, a weight of a sum of the low-section R2R digital-to-analog converter is the same as a weight of the high-section device. During calibration, except that the resistor to be calibrated is connected with the VREFP, other resistors are all suspended; in normal operation, switch bc is connected to VREFN, as is conventional R2R circuit connection, VCORERepresenting the core voltage.
In order to meet the above calibration requirement, a three-state switch is designed, and fig. 4 shows a schematic circuit structure diagram of a three-state switch provided in an embodiment of the present application, as shown in fig. 4, when calibration is performed, that is, when TRIS =1, code =0, all switches are off, at this time, the switches are three-state switches, code =1, and a resistor is connected to VREFP, at this time, the branch is being calibrated; in normal operation, i.e., when TRIS =0, code =0, resistance is connected to VREFN, code =1, and resistance is connected to VREFP. Wherein CODE represents an input CODE value, and TRIS represents a tri-state enable control signal; SN is the grid control signal of the N-type field effect transistor, and SP is the grid control signal of the P-type field effect transistor.
Optionally, the reference resistance unit and the high-segment resistance array have the same branch structure, the resistance value corresponding to the reference resistance unit is smaller than the resistance value corresponding to the high-segment resistance array, during calibration, the to-be-calibrated unit is connected to a reference voltage positive electrode (VREFP), the reference resistance unit is connected to a reference voltage negative electrode (VREFN), and the reference voltage of the voltage comparator during calibration is: (VREFP-VREFN)/2; the input of the voltage comparator is a common mode node, and the reference voltage is (VREFP-VREFN)/2.
In the application, the bit width of the auxiliary digital-to-analog converter is lower than that of the main digital-to-analog converter, the auxiliary digital-to-analog converter is used for quantifying the device deviation of the main digital-to-analog converter, the auxiliary digital-to-analog converter can receive data output by the searching unit, and the output end of the auxiliary digital-to-analog converter is connected to the main digital-to-analog converter and the reference resistance unit.
Furthermore, the reference resistance unit is the same as one branch of the high-section resistance array, and the resistance value of the reference resistance unit is smaller than that of the high-section resistance array. Fig. 5 is a schematic diagram illustrating a circuit structure of a resistor divider during calibration according to an embodiment of the present application, as shown in fig. 5, VCORERepresenting core voltage, V at calibrationCOREThe voltage is (VREFP-VREFN)/2, in order to ensure that the low-stage sum and any one of the high-stage resistance values are larger than the reference resistance, and the calibration current flows into the reference resistance during calibration, the resistance value of the reference resistance part is smaller than that of any resistance to be calibrated, and in order to ensure the design margin, the resistance value of the reference resistance can be designed to be a certain percentage of the high-stage resistance. Wherein the content of the first and second substances,
which represents a reference resistance, is shown,R cal,i is the resistance of the high-section,
representing the cell current to be calibrated.
For example, fig. 6 shows a circuit schematic diagram of a calibration loop provided in an embodiment of the present application, and as shown in fig. 6, the calibration loop includes a main digital-to-analog converter core, that is, the main digital-to-analog converter in the present application, a reference resistance unit, and a voltage comparatorAnd a reference voltage generating circuit (i.e., a reference voltage unit in the present application), a calibration digital-to-analog converter (i.e., an auxiliary digital-to-analog converter in the present application), a successive approximation calibration logic unit, a lookup table, a decoding logic, a control unit, and the like, where a unit to be calibrated in the main digital-to-analog converter includes a low-stage resistor array and a high-stage resistor array. Optionally, the low-section resistor (LSB) array (R2R array) of the main dac may be an L bit, and the high-section thermometer-coded resistor array, that is, the high-section resistor (MSB) array, is an M bit. Comp denotes a comparator, VREF _ COMP denotes a reference voltage of the comparator, VCORERepresenting the core voltage.
During calibration, the current of the auxiliary digital-to-analog converter flows into the reference resistor, the sum of the low section is calibrated for the first time, all switches of the low section are connected with the VREFP at the moment, all switches of the high section are disconnected, and the calculation formula of Ical, i can be obtained according to the resistance voltage division principle:
i=0，1，2，…，
(1)；
wherein, cal represents the unit to be calibrated,
which is representative of the cell current to be calibrated,
representing the reference resistance, VREFP representing the positive reference voltage and VREFN representing the negative reference voltage, the minimum resolution of the auxiliary dac may be set to 1/8 of the minimum resolution of the resistive dac for better calibrationResolution is LSB0, and the minimum resolution of the auxiliary DAC is LSB0
The calibration loop has the following formula:
the unit current of the auxiliary digital-to-analog converter can be obtained as follows:
the calibration of the high-section resistor array is similar to that of the low-section sum, when the high-section resistor array is calibrated, one high-section resistor is connected with the VREFP, and all other switches are disconnected; sequentially calibrating each resistor to be calibrated to obtain the calibration value I of all resistors to be calibratedcal,0,Ical,1,…,
(ii) a The calibration current for each device, if operating normally, is Ical, i, i =0,1, …,
in order to solve the problem that the range of the auxiliary digital-to-analog converter is extremely large after the code values are accumulated, the calibration current of each high-segment resistor is subtracted by the calibration current of the sum of the low segments during normal operation, that is:
wherein R is0Is the equivalent resistance of the sum of the low segments, and Rcal, i is the resistance of the high segment. Since the equivalent resistances of the high-section resistance and the low-section sum are relatively close, the trimming current is comparedSmall, without causing an increase in the range of the auxiliary digital-to-analog converter.
Further, when the high-precision resistance type digital-to-analog converter works normally, the calibration current flows into one high-section resistance branch in the resistance type digital-to-analog converter.
Fig. 7 is a schematic diagram illustrating a circuit structure of a core portion of an auxiliary digital-to-analog converter according to an embodiment of the present disclosure, as shown in fig. 7, the auxiliary digital-to-analog converter includes a voltage-to-current circuit and a calibration digital-to-analog converter portion, where the voltage-to-current circuit uses an adjustable resistor, and when a resistance of the adjustable resistor is large, an output current is small, and when the resistance of the adjustable resistor is small, the output current is large, so that current fine tuning of the auxiliary digital-to-analog converter is achieved. The operational amplifier circuit is connected with two P-type field effect transistors (PM 1, PM 2).
In this application, when the main dac is operating normally, if only the low stage R2R circuit part is operating, the calibration current is a constant current IDC, and when the high stage resistor is operating, the calibration current is the original calibration current minus the low stage calibration current.
When only the low-section resistor works, the calibration current can be set as IDC, the IDC can be 1/2 full swing output current of the auxiliary digital-to-analog converter, or any other value, as long as the main digital-to-analog converter is ensured not to exceed the measuring range during calibration; when each high-section resistor works, the compensated current is
，i=1,2，…,
. If the weight of each high-section resistor relative to the sum of the low-section resistors is large, the calibration current is a negative value when any one high-section resistor works, so that the current of the auxiliary digital-to-analog converter needs to satisfy the following requirements:
if the total current of the auxiliary digital-to-analog converter is IFS, and if the weight of each high-stage resistor relative to the sum of the low-stage resistors is small, the calibration current is positive when any one of the high-stage resistors works, so that the current of the auxiliary digital-to-analog converter needs to satisfy:
according to IFS current sum
The accuracy and bit width of the auxiliary digital-to-analog converter can be determined.
Compared with the prior art, the invention has the following beneficial effects: the area of the high-section resistance part is reduced, the overall precision is improved, and the high-precision resistance type digital-to-analog converter can be realized.
For example, according to the 14-bit high-precision resistance digital-to-analog converter with digital calibration, as shown in the correction loop shown in fig. 6, for an embodiment, the low-stage R2R array is set to be 8 bits, and is implemented by using a binary coding method; the high-section resistor array is 6bit and is realized by using a thermometer coding mode; the auxiliary digital-to-analog converter is 8 bit; the data bit width of the lookup table is 8 bits, the data number comprises 1 calibration code value of low-section sum plus 1LSB, and the high-section resistor array calibration code value
There are 64 calibration code values in total.
In calibration, the circuit is under the control of the controller, and the auxiliary digital-to-analog converter sends an intermediate code value, namely 8' b1000, 0000; the switch of the reference resistor is grounded; the reference voltage of the comparator is
(ii) a The main digital-to-analog converter is in a calibration mode; when the first cell to be calibrated is calibrated, the low-stage R2R resistor part and the bc switch are all connected with VREFP, and other switches are all disconnected.
In a first comparison period, the comparison result is A, if A is 1, the calibration current is larger at the moment, and the successive approximation calibration logic reduces the current of the auxiliary digital-to-analog converter; if A is 0, the calibration current is smaller at the moment, and the successive approximation calibration logic increases the current of the auxiliary digital-to-analog converter; after the first compare cycle is complete, the calibration code value is modified to 8' bA100, 0000.
In the second comparison period, the comparison result is B, if B is 1, the calibration current is larger at the moment, and the successive approximation calibration logic reduces the current of the auxiliary digital-to-analog converter; if B is 0, the calibration current is smaller at the moment, and the successive approximation calibration logic increases the current of the auxiliary digital-to-analog converter; after the second compare cycle is complete, the calibration code value is modified to 8' bAB10, 0000.
Similarly, in the third to eighth comparison periods, the comparison result of the comparator in each comparison period is set to be C, D, E, F, G, H, and the final calibration code value is 8' bABCD, EFGH; therefore, after 8 comparison cycles, the calibration CODE value CODE of the first unit to be calibrated is obtained1。
When the second unit to be calibrated is calibrated, the first resistance unit at the high section is connected with the VREFP, other switches are all disconnected, and the calibration CODE value CODE of the second unit to be calibrated is obtained through eight comparison periods which are the same as those of the first unit to be calibrated2。
When the ith unit to be calibrated is calibrated, the (i-1) th resistance unit at the high section is connected with the VREFP, all other switches are disconnected, and the calibration code value CODei of the ith unit to be calibrated is obtained through eight comparison periods which are the same as those of the first unit to be calibrated.
Through
After the calibration logic described above, all calibration code values are obtained. The calibration logic stores all calibration code values in a look-up table to compensate the main digital-to-analog converter with the calibration code values during normal operation.
In normal operation, fig. 8 shows a schematic structural diagram of a linear calibration system in a normal operating state according to an embodiment of the present application, as shown in fig. 8, a circuit is in a normal operating mode under the control of a controller, a signal generated by decoding logic is used as an address selection signal of a lookup table (lookup unit), and a corresponding calibration code value is selected and sent to an auxiliary digital-to-analog converter (calibration digital-to-analog converter); the auxiliary digital-to-analog converter performs specific conversion on the calibration code value, and then sends the calibration current generated by the converted code value to the high-section resistor array of the main digital-to-analog converter, and the mode selection circuit shown in fig. 6 is referred to and sends the calibration current to the high-section resistor array.
When the digital-to-analog converter works normally, if the main digital-to-analog converter does not have the high-section resistor array, the code value of the auxiliary digital-to-analog converter is a fixed valueCODE 0 In the examplesCODE 0 May be 8' b1000, 0000; if the first resistor of the high-section resistor array works, the calibration code value at the moment is
(ii) a If the second resistor of the high-section resistor array works, the calibration code value at the moment is
(ii) a Similarly, if the first of the high-section resistor arraykWhen the resistor works, the calibration code value is
. Therefore, all resistance deviations in the main digital-to-analog converter are compensated by using the auxiliary current type digital-to-analog converter, and the high-precision digital-to-analog converter is obtained.
In summary, the main dac is configured to receive, in a calibration mode, a calibration control signal transmitted by the digital circuit, receive a calibration current value transmitted by the auxiliary dac, and determine a first voltage signal based on the calibration current value and the calibration control signal; the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value; the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode, so that the calibration and compensation of the precision of the main digital-to-analog converter are realized, the calibration of the digital-to-analog converter can be realized without increasing the area of the core part of a device, the optimization of the performance of the digital-to-analog converter is realized, and the precision of the digital-to-analog converter can be further improved.
Fig. 9 is a schematic flowchart illustrating a linear calibration method applied to a digital-to-analog converter according to an embodiment of the present application, where the linear calibration method is applied to the linear calibration system applied to the digital-to-analog converter according to any one of fig. 1 to fig. 8, and as shown in fig. 9, the linear calibration method applied to the digital-to-analog converter includes:
step 301: and controlling the main digital-to-analog converter to receive a calibration control signal transmitted by the digital circuit in a calibration mode, receiving a calibration current value transmitted by the auxiliary digital-to-analog converter, and determining a first voltage signal based on the calibration current value and the calibration control signal.
After controlling the main dac to receive the calibration control signal transmitted by the digital circuit in the calibration mode and receive the calibration current value transmitted by the auxiliary dac, and determining the first voltage signal based on the calibration current value and the calibration control signal, step 302 is performed.
Step 302: and controlling the voltage comparator to determine a device deviation voltage information signal corresponding to the main digital-to-analog converter under the coordination of the digital circuit based on the first voltage signal and the reference signal, and converting the device deviation voltage information signal into a calibration code value corresponding to the calibration current value.
After controlling the voltage comparator to determine the device offset voltage information signal corresponding to the main dac based on the first voltage signal and the reference signal in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, step 303 is executed.
Step 303: controlling the digital circuit to store the calibration code value.
After controlling the digital circuitry to store the calibration code value, step 304 is performed.
Step 304: and controlling the auxiliary digital-to-analog converter to calibrate the main digital-to-analog converter based on the calibration code value.
After controlling the auxiliary dac to calibrate the main dac based on the calibration code value, step 305 is performed.
Step 305: and controlling the auxiliary digital-to-analog converter to carry out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode.
In summary, with the linear calibration method applied to the digital-to-analog converter provided in the embodiment of the present application, the main digital-to-analog converter is configured to receive the calibration control signal transmitted by the digital circuit in the calibration mode, receive the calibration current value transmitted by the auxiliary digital-to-analog converter, and determine the first voltage signal based on the calibration current value and the calibration control signal; the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value; the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode, so that the calibration and compensation of the precision of the main digital-to-analog converter are realized, the calibration of the digital-to-analog converter can be realized without increasing the area of the core part of a device, the optimization of the performance of the digital-to-analog converter is realized, and the precision of the digital-to-analog converter can be further improved.
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A linear calibration system applied to a digital-to-analog converter is characterized by comprising a digital circuit and an analog circuit, wherein the analog circuit comprises an auxiliary digital-to-analog converter, a main digital-to-analog converter and a voltage comparator, wherein the output end of the auxiliary digital-to-analog converter is connected with the compensation current input end of the main digital-to-analog converter, the output end of the main digital-to-analog converter is connected with the input end of the voltage comparator, the first output end of the digital circuit is connected with the input end of the auxiliary digital-to-analog converter, the second output end of the digital circuit is connected with the input end of the main digital-to-analog converter, and the input end of the digital circuit is connected with the output end of the voltage comparator;
the main digital-to-analog converter is used for receiving a calibration control signal transmitted by the digital circuit in a calibration mode, receiving a calibration current value transmitted by the auxiliary digital-to-analog converter and determining a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator is configured to determine, based on the first voltage signal and a reference signal, a device offset voltage information signal corresponding to the main digital-to-analog converter in cooperation with the digital circuit, and convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, the digital circuit is configured to store the calibration code value, and the auxiliary digital-to-analog converter is configured to calibrate the main digital-to-analog converter based on the calibration code value;
the auxiliary digital-to-analog converter is also used for carrying out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode;
wherein the reference signal comprises a reference resistance signal and a reference voltage signal; the analog circuit further comprises a reference resistance unit and a reference voltage unit, wherein the output end of the reference voltage unit and the output end of the reference resistance unit are both connected with the input end of the voltage comparator; the reference resistance unit is used for providing a reference resistance signal;
the reference voltage unit is used for providing a reference voltage signal;
the main digital-to-analog converter comprises a first decoding logic unit, a low-section resistor array and a high-section resistor array which are connected in pairs; the low-section resistor array is a low-section resistor unit to be calibrated; the high-section resistor array comprises a plurality of high-section resistor units to be calibrated;
in a calibration mode, the auxiliary digital-to-analog converter is configured to send the calibration current value to the main digital-to-analog converter; the main digital-to-analog converter is used for determining a first voltage signal based on the calibration current value and the calibration control signal;
under the condition of calibrating the unit to be calibrated of the low-section resistance or the unit to be calibrated of the high-section resistance, the voltage comparator is used for determining the device deviation voltage information signal corresponding to the unit to be calibrated corresponding to a preset period based on the first voltage signal, the reference resistance signal and the reference voltage signal;
the calibration logic unit is used for determining a target calibration current value based on the device deviation voltage information signal, determining the calibration code value based on the target calibration current value, and inputting the calibration code value to the searching unit;
the auxiliary digital-to-analog converter is used for receiving the calibration code value transmitted by the searching unit in a normal mode and determining the calibration current value based on the calibration code value;
the main digital-to-analog converter is further used for receiving the calibration current value in a normal mode, and completing calibration of the low-section resistance unit to be calibrated or the high-section resistance unit to be calibrated based on the calibration current value;
the bit width of the auxiliary digital-to-analog converter is less than that of the main digital-to-analog converter; the low-section resistor array comprises a lowest resistor unit, and the lowest resistor unit comprises a three-state switch, a first resistor and a second resistor which are sequentially connected in series; the main digital-to-analog converter is a resistance type digital-to-analog converter, and the auxiliary digital-to-analog converter is a current type digital-to-analog converter.
2. The linear calibration system applied to digital-to-analog converters according to claim 1, characterized in that said digital circuit comprises a correction logic unit and a lookup unit; the output end of the correction logic unit is connected with the input end of the search unit; the input end of the auxiliary digital-to-analog converter is connected with the output end of the searching unit, and the output end of the voltage comparator is connected with the input end of the correction logic unit; the digital circuit also comprises a successive approximation calibration logic unit, wherein the input end of the successive approximation calibration logic unit is connected with the output end of the voltage comparator, and the output end of the successive approximation calibration logic unit is connected with the input end of the searching unit;
the main digital-to-analog converter is used for receiving a calibration control signal transmitted by the digital circuit in a calibration mode, receiving a calibration current value transmitted by the auxiliary digital-to-analog converter, and determining a first voltage signal based on the calibration current value and the calibration control signal;
the voltage comparator is configured to determine, based on the first voltage signal and the reference signal, the device offset voltage information signal corresponding to the main digital-to-analog converter corresponding to a preset period through a successive approximation calibration logic unit in cooperation with the correction logic unit, convert the device offset voltage information signal into a calibration code value corresponding to the calibration current value, and send the calibration code value to the search unit;
the auxiliary digital-to-analog converter is used for receiving the calibration code value transmitted by the searching unit in a normal mode and determining the calibration current value based on the calibration code value;
and the main digital-to-analog converter is also used for receiving the calibration current value in a normal mode and completing the error compensation of the main digital-to-analog converter based on the calibration current value.
3. The linear calibration system applied to digital-to-analog converter according to claim 2, further comprising a control unit respectively connected to the input of said correction logic unit, the input of said lookup unit and the input of said main digital-to-analog converter; the main digital-to-analog converter comprises a plurality of units to be calibrated;
the control unit is used for generating a calibration control signal corresponding to the unit to be calibrated in a calibration mode and controlling the correction logic unit to receive the device deviation voltage information signal output by the voltage comparator;
the correction logic unit is used for determining the calibration code value based on the device offset voltage information signal and sending the calibration code value to the searching unit;
the searching unit is used for inputting the calibration code value to the auxiliary digital-to-analog converter;
the auxiliary digital-to-analog converter determines the calibration current value based on the calibration code value;
the control unit is further configured to perform error compensation on the main dac based on the calibration code value in the lookup unit in a normal mode.
4. The linear calibration system applied to the dac of claim 1, wherein the voltage comparator is configured to determine the device offset voltage information signals corresponding to a plurality of units to be calibrated corresponding to a preset period through a successive approximation calibration logic unit based on the first voltage signal and the reference signal, and the system includes:
the voltage comparator is used for determining the device deviation voltage information signals corresponding to the units to be calibrated corresponding to a preset period through a successive approximation calibration logic unit based on the first voltage signal, the reference resistance signal and the reference voltage signal.
5. The linear calibration system for digital-to-analog converters according to claim 1, wherein the reference resistor unit and the high-section resistor array have the same branch structure, and the resistance value of the reference resistor unit is smaller than that of the high-section resistor array.
6. The linear calibration system for digital-to-analog converters according to claim 3, further comprising a second decoding logic unit having an input connected to the output of said control unit and an output connected to the input of said search unit.
7. A linear calibration method applied to a digital-to-analog converter, characterized in that, the method is applied to the linear calibration system applied to the digital-to-analog converter of any one of claims 1 to 6, and the method comprises:
controlling the main digital-to-analog converter to receive a calibration control signal transmitted by the digital circuit in a calibration mode and receive a calibration current value transmitted by the auxiliary digital-to-analog converter, and determining a first voltage signal based on the calibration current value and the calibration control signal;
controlling the voltage comparator to determine a device offset voltage information signal corresponding to the main digital-to-analog converter under the coordination of the digital circuit based on the first voltage signal and a reference signal, and converting the device offset voltage information signal into a calibration code value corresponding to the calibration current value;
controlling the digital circuit to store the calibration code value;
controlling the auxiliary digital-to-analog converter to calibrate the main digital-to-analog converter based on the calibration code value;
controlling the auxiliary digital-to-analog converter to carry out error compensation on the main digital-to-analog converter based on the calibration code value sent by the digital circuit in a normal mode;
controlling the auxiliary digital-to-analog converter to send the calibration current value to the main digital-to-analog converter in a calibration mode;
controlling the main digital-to-analog converter to determine a first voltage signal based on the calibration current value and the calibration control signal;
under the condition of calibrating the unit to be calibrated of the low-section resistance or the unit to be calibrated of the high-section resistance, controlling the voltage comparator to determine the device deviation voltage information signal corresponding to the unit to be calibrated corresponding to a preset period based on the first voltage signal, the reference resistance signal and the reference voltage signal;
controlling a calibration logic unit to determine a target calibration current value based on the device offset voltage information signal, determining a calibration code value based on the target calibration current value, and inputting the calibration code value to a searching unit;
wherein the controlling the auxiliary dac to perform error compensation on the main dac based on the calibration code value sent by the digital circuit in a normal mode includes:
controlling the auxiliary digital-to-analog converter to receive the calibration code value transmitted by the searching unit in a normal mode, and determining the calibration current value based on the calibration code value;
and controlling the main digital-to-analog converter to receive the calibration current value in a normal mode, and completing the calibration of the low-section resistance to-be-calibrated unit or the high-section resistance to-be-calibrated unit based on the calibration current value.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368575A (en) * | 2013-07-17 | 2013-10-23 | 电子科技大学 | Digital correction circuit and digital-to-analog converter of current-steering structure and with same |
| CN107994904A (en) * | 2018-01-29 | 2018-05-04 | 北京特邦微电子科技有限公司 | Digital analog converter |
| CN112202448A (en) * | 2020-09-28 | 2021-01-08 | 上海艾为电子技术股份有限公司 | Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153592A (en) * | 1991-04-30 | 1992-10-06 | Texas Instruments Incorporated | 16 bit error-correcting digital-to-analog converter |
| KR100546412B1 (en) * | 2004-06-04 | 2006-01-26 | 삼성전자주식회사 | Digital to analog converter and digital to analog converting method |
| US7095351B2 (en) * | 2004-09-20 | 2006-08-22 | Analog Devices, Inc. | Digital-to-analog converter structures |
| US7248192B2 (en) * | 2005-11-03 | 2007-07-24 | Analog Devices, Inc. | Digital to analog converter and a ground offset compensation circuit |
| US7443323B2 (en) * | 2007-01-10 | 2008-10-28 | Freescale Semiconductor, Inc. | Calibrating a digital-to-analog converter |
| CN102832946B (en) * | 2012-08-23 | 2016-05-18 | 昆腾微电子股份有限公司 | Digital to analog converter |
| US9136866B2 (en) * | 2013-10-09 | 2015-09-15 | Analog Devices Global | Digital-to-analog converter and a method of operating a digital-to-analog converter |
| US10574247B1 (en) * | 2018-09-14 | 2020-02-25 | Analog Devices Global Unlimited Company | Digital-to-analog converter transfer function modification |
-
2021
- 2021-09-13 CN CN202111065960.2A patent/CN113517891B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368575A (en) * | 2013-07-17 | 2013-10-23 | 电子科技大学 | Digital correction circuit and digital-to-analog converter of current-steering structure and with same |
| CN107994904A (en) * | 2018-01-29 | 2018-05-04 | 北京特邦微电子科技有限公司 | Digital analog converter |
| CN112202448A (en) * | 2020-09-28 | 2021-01-08 | 上海艾为电子技术股份有限公司 | Successive approximation type analog-to-digital converter, calibration method thereof and electronic equipment |
Non-Patent Citations (2)
| Title |
|---|
| "A self-calibrated binary weighted DAC in 90nm CMOS technology";Daniel Arbet等;《2014 29th International Conference on Microelectronics Proceedings - MIEL 2014》;20140626;383-386 * |
| "一款直流偏移自校准的多模数模转换器";林雁飞 等;《半导体技术》;20190731;第44卷(第7期);511-519 * |
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