CN113938135B - Successive approximation type analog-to-digital converter and calibration method - Google Patents
Successive approximation type analog-to-digital converter and calibration method Download PDFInfo
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- H03M1/12—Analogue/digital converters
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The present disclosure provides a successive approximation analog-to-digital converter comprising: the signal sampling module is used for sampling the analog signals; the differential capacitor array comprises a segmented capacitor array, wherein the low-stage capacitor array is formed by a binary coded capacitor array, and the high Duan Dianrong array is formed by a non-binary coded capacitor array with integer weight; the signal sampling module realizes sampling through a lower polar plate of the high-stage capacitor; the disturbance signal injection module is used for carrying out disturbance signal injection on the sampling signals; the digital calibration module is used for quantizing the sampling signal injected with the disturbance signal to obtain two different digital codes and quantized values corresponding to the disturbance signal, and carrying out iterative calculation according to the two different digital codes and the quantized values until the error between the two digital codes and the quantized values tends to zero; the comparator module is used for comparing signals input by the differential capacitor array and outputting a comparison result; and the logic control module is used for controlling the switching mode of the lower plate of the capacitor array according to the output result of the comparator.
Description
Technical Field
The disclosure relates to the technical field of analog-to-digital conversion, and in particular relates to a successive approximation type analog-to-digital converter and a calibration method.
Background
With the rapid development of integrated circuits and communication industry, analog-to-digital converters (ADCs) are widely used, and high-resolution ADCs can be widely used in Wi-Fi, image processing, smart antenna systems, and other fields. Due to the comprehensive advantages of the SAR ADC in the aspects of precision, speed, power consumption, cost and the like, the SAR ADC becomes one of the optional structures for realizing the high-speed and high-precision ADC in the industry and academia.
The precision of the high-precision SAR ADC is mainly influenced by non-ideal factors such as circuit element mismatch, parasitic effect and the like, so that calibration is essential in the use process of the SAR ADC. In the prior art, a capacitor array based on binary base r=1.86 is proposed and calibrated by combining disturbance signal injection, and in the mode, each bit capacitor adopts a sub-radix-2 fractional capacitor, and the sub-radix-2 fractional capacitors exist independently of each other and cannot form matching. There is proposed a 10bit SAR ADC in which the upper 8 bit capacitance is controlled by a thermometer code, the lower 2 bits are binary structures, and the upper 8 bit thermometer code requires a large number of encoding and control circuits, increasing the complexity of the circuit structure. It has also been proposed to implement a 16-bit 1Msps SAR ADC using a Split (Split) calibration method of a successive approximation ADC, but Split analog-to-digital converter calibration requires the generation of multiple different decision paths and doubles the number of comparators and some signal paths.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
Based on this, the present disclosure provides in one aspect a successive approximation analog-to-digital converter comprising: the signal sampling module is used for sampling the analog signals to obtain sampled signals; the differential capacitor array comprises a low-stage capacitor array, a high Duan Dianrong array and a disturbance signal injection capacitor, wherein the low-stage capacitor array is formed by a binary coded capacitor array, and the high Duan Dianrong array is formed by a non-binary coded capacitor array with integer weight; the signal sampling module realizes sampling through a lower polar plate of the high-stage capacitor; the disturbance signal injection module is used for injecting positive disturbance signals and negative disturbance signals into the sampling signals; the digital calibration module is used for quantizing the sampled signals injected with the positive disturbance signals and the negative disturbance signals to obtain a first digital code corresponding to the sampled signals injected with the positive disturbance signals, a second digital code corresponding to the sampled signals injected with the negative disturbance signals and quantized values corresponding to the disturbance signals, and carrying out iterative computation according to the quantized values corresponding to the first digital code, the second digital code and the disturbance signals based on an LMS iterative algorithm until errors among the quantized values corresponding to the first digital code, the second digital code and the disturbance signals tend to zero; the error among the quantized values corresponding to the first digital code, the second digital code and the disturbance signal is a capacitance weight error of the differential capacitance array; the comparator module is used for comparing signals input by the differential capacitor array and outputting a comparison result; and the logic control module is used for switching the signal access mode of the differential capacitor array according to the comparison result.
Optionally, the digital calibration module includes: the error calculation unit is used for calculating errors among quantization values corresponding to the first digital code, the second digital code and the disturbance signal; the weight iteration unit is used for calculating updated capacitance weights according to errors among quantization values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the updated capacitance weights into the error calculation unit for iterative calculation; and the disturbance iteration unit is used for calculating the quantization value corresponding to the updated disturbance signal according to the error among the quantization values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the quantization value corresponding to the updated disturbance signal into the error calculation unit for iterative calculation.
Optionally, the calculating the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal includes: according to the following:
E error ＝D + -D - -2Δd
calculating the error E error ，D + D for injecting quantized values corresponding to the sampled signal of the positive disturbance signal - For the quantized value corresponding to the sampled signal of the injected negative perturbation signal, Δd is the quantized value corresponding to the perturbation signal, where:
wherein n is the total number of quantization times, i is the number of single quantization times, k is the number of weight capacitor, ω k An initial weight of the kth weight capacitance, b i+ B) binary coding quantized for a sample signal injected for a positive perturbation signal i- A binary code quantized by the sampling signal injected for the negative disturbance signal;
the calculating the updated capacitance weight according to the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises: according to
ω′ k ＝ω k ×u ω ×E error ×(b i+ -b i- )
Calculate updated capacitance weight ω' k ，u ω The iteration step length of the capacitor weight is set;
the calculating the updated quantized value corresponding to the disturbance signal according to the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises: according to
Δd′＝Δd×u d ×E error
Calculating updated capacitance weights Δd', u d The iteration step length of the quantized value corresponding to the disturbance signal.
Optionally, the perturbation signal injection module is used for realizing switching between positive perturbation signal injection and negative perturbation signal injection by changing a lower polar plate connection method of the perturbation signal injection capacitor.
Optionally, the lower electrode plate of the disturbance signal injection capacitor at the p side of the differential capacitor array is connected with a reference voltage, and the lower electrode plate of the disturbance signal injection capacitor at the n side is grounded, so that the injection of the positive disturbance signal is realized; and grounding the lower polar plate of the disturbance signal injection capacitor at the p side of the differential capacitor array, and connecting the lower polar plate of the disturbance signal injection capacitor at the n side with a reference voltage to realize the injection of the negative disturbance signal.
Optionally, the operation mode of the successive approximation analog-to-digital converter includes a calibration mode and a normal operation mode, and the normal operation mode includes a sampling phase, a holding phase and a quantization phase; in the sampling stage, an upper plate of the high Duan Dianrong array and a lower plate of the low-stage capacitor array are connected with a common-mode voltage, and a lower plate of the high Duan Dianrong array is connected with a sampling signal; in the holding stage, the upper plates of the high Duan Dianrong array are disconnected from the common mode voltage, and the lower plates of all the weight capacitors are connected to the common mode voltage; in the quantization stage, the lower polar plates of all the weight capacitors are connected to reference voltage or ground; the calibration mode comprises a sampling phase, a positive disturbance signal injection phase, a sampling signal quantization phase with positive injection, a disturbance signal resetting phase, a negative disturbance signal injection phase and a sampling signal quantization phase with negative injection; in the sampling stage, an upper plate of the high Duan Dianrong array and a lower plate of the low-stage capacitor array are connected with a common-mode voltage, and a lower plate of the high Duan Dianrong array is connected with a sampling signal; in the injection stage of the positive disturbance signals, the upper plate of the high Duan Dianrong array is disconnected from the common mode voltage, the lower plate of the disturbance signal injection capacitor at the p side of the differential capacitor array is connected with the reference voltage, the lower plate of the disturbance signal injection capacitor at the n side is grounded, and the lower plates of all the other capacitors are connected with the common mode voltage; in the quantization stage with the sampling signal being injected, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor at the p side of the differential capacitor array is connected with the reference voltage by the common-mode voltage, and the lower electrode plate of the capacitor at the n side is grounded by the common-mode voltage; in the reset stage of the disturbance signals, the disturbance signals on the p side and the n side of the differential capacitor array are injected into the lower polar plate of the capacitor to be grounded; in the injection stage of the negative disturbance signals, the disturbance signals at the p side of the differential capacitor array are injected into the lower electrode plate of the capacitor to be grounded, the lower electrode plate of the disturbance signal injection capacitor at the n side is connected with a reference voltage, and the lower electrode plates of all the other capacitors are connected with a common mode voltage; in the quantization stage of the sampling signal with negative injection, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor on the p side of the differential capacitor array is connected with the reference voltage by the common mode voltage, and the lower electrode plate of the capacitor on the n side is grounded by the common mode voltage.
Optionally, the signal sampling module value performs signal sampling once in the process of injecting the positive disturbance signal and the negative disturbance signal completely once.
Optionally, after the quantization of the sampling signal injected with the positive disturbance signal is completed, the sampling signal is reset, and the injection of the negative disturbance signal is performed.
Optionally, the weight of any one of the next-lower to highest weighted capacitors in the array of high Duan Dianrong is less than the sum of the weights of all weighted capacitors lower than that capacitor.
In another aspect, the present disclosure further provides a calibration method based on a successive approximation type analog-to-digital converter, including: sampling by using a signal sampling module to obtain a sampling signal; the differential capacitor array and the disturbance signal injection module are utilized to carry out positive disturbance signal and negative disturbance signal injection on the sampling signals, the digital calibration module is utilized to quantize the sampling signals injected with the positive disturbance signal and the negative disturbance signal, two different digital codes and quantized values corresponding to the disturbance signals are obtained, and the initial value of the capacitance weight error of the differential capacitor array is calculated by utilizing the two different digital codes and the quantized values corresponding to the disturbance signals; calculating updated capacitance weight and quantized values corresponding to the updated disturbance signals according to initial values of the capacitance weight errors, and calculating capacitance weight errors according to the updated capacitance weight and the quantized values corresponding to the updated disturbance signals, wherein the steps are performed in a circulating mode until the capacitance weight errors tend to zero.
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The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof with reference to the accompanying drawings in which:
fig. 1 schematically illustrates a block diagram of a differential capacitive array provided in accordance with an embodiment of the present disclosure.
Fig. 2 schematically illustrates a block diagram of a digital calibration module provided in accordance with an embodiment of the present disclosure.
FIG. 3 schematically illustrates a timing diagram for disturbance-based digital calibration provided in accordance with an embodiment of the present disclosure.
Fig. 4 schematically illustrates a graph of the number of significant bits versus the number of corrections provided by an embodiment of the present disclosure.
Fig. 5 schematically illustrates a diagram of FFT simulation results before and after calibration provided by an embodiment of the present disclosure.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
In the description of the present disclosure, it should be understood that the terms "longitudinal," "length," "circumferential," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, merely to facilitate description of the present disclosure and to simplify the description, and do not indicate or imply that the subsystem or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.
Like elements are denoted by like or similar reference numerals throughout the drawings. Conventional structures or constructions will be omitted when they may obscure the understanding of this disclosure. And the shape, size and position relation of each component in the figure do not reflect the actual size, proportion and actual position relation. In addition, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Similarly, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. The description of the reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
The disclosed embodiments provide a successive approximation analog-to-digital converter, comprising: and the signal sampling module is used for sampling the analog signal to obtain a sampled signal. The differential capacitor array comprises a low-stage capacitor array, a high Duan Dianrong array and a disturbance signal injection capacitor, wherein the low-stage capacitor array is formed by a binary coded capacitor array, and the high Duan Dianrong array is formed by a non-binary coded capacitor array with integer weight. The signal sampling module realizes sampling through the lower polar plate of the high-stage capacitor. And the disturbance signal injection module is used for injecting positive disturbance signals and negative disturbance signals into the sampling signals. The digital calibration module is used for quantizing the sampled signals injected with the positive disturbance signals and the negative disturbance signals to obtain a first digital code corresponding to the sampled signals injected with the positive disturbance signals, a second digital code corresponding to the sampled signals injected with the negative disturbance signals and quantized values corresponding to the disturbance signals, and carrying out iterative computation according to the quantized values corresponding to the first digital code, the second digital code and the disturbance signals based on an LMS iterative algorithm until errors among the quantized values corresponding to the first digital code, the second digital code and the disturbance signals tend to zero; the error among the quantized values corresponding to the first digital code, the second digital code and the disturbance signal is a capacitance weight error of the differential capacitance array; the comparator module is used for comparing signals input by the differential capacitor array and outputting a comparison result; and the logic control module is used for switching the signal access mode of the differential capacitor array according to the comparison result. The following detailed description refers to the accompanying drawings.
Fig. 1 schematically illustrates a block diagram of a differential capacitive array provided in accordance with an embodiment of the present disclosure.
As shown in fig. 1, the differential capacitor array includes a low-stage capacitor array, a high Duan Dianrong array and a disturbance signal injection capacitor, wherein the low-stage capacitor array is formed by a binary-coded capacitor array, and the high Duan Dianrong array is formed by a non-binary-coded capacitor array with integer weights. All capacitors of the DAC are numbered and denoted as C i (i=0, 1,2,) 15, 16), and C tp 、C tn 、C bp 、C bn Wherein C 0 -C 4 Is low-stage capacitance, C 5 -C 16 For the high-section weight capacitance, C tp And C tn Capacitors for injecting disturbance signals are respectively arranged on the p side and the n side, the high-stage array and the low-stage array are connected through bridging capacitors, C bp And C bn The bridge capacitances on the n-side and p-side, respectively. The output of the differential capacitor array is connected to the comparator module.
According to the embodiment of the disclosure, the adopted capacitor is split in the way of C 16 And C 15 Splitting and respectively superposing to C 5 -C 14 Such that a high Duan Dianrong array, which would otherwise require 9 binary capacitive representations, now requires 12 non-binary coded capacitive representations, and requires non-binary weights (from C 6 -C 16 ) Any one capacitor C in the capacitor array of (a) i Less than the sum of the weights of their lower capacitances, namely:
equivalent to the fact that,
the method of scaling and reorganization does not change the total capacitance value, so that the input signal range which can be quantized by the SAR ADC is not affected by the split capacitance.
According to an embodiment of the present disclosure, the perturbation signal injection is a switching between positive and negative perturbation signal injection by a bottom plate connection of a varying perturbation signal injection capacitance. The lower electrode plate of the disturbance signal injection capacitor at the p side of the differential capacitor array is connected with a reference voltage, and the lower electrode plate of the disturbance signal injection capacitor at the n side is grounded, so that the injection of the positive disturbance signal is realized. And grounding the lower polar plate of the disturbance signal injection capacitor at the p side of the differential capacitor array, and connecting the lower polar plate of the disturbance signal injection capacitor at the n side with a reference voltage to realize the injection of the negative disturbance signal.
According to an embodiment of the present disclosure, the signal sampling module value performs one signal sample during one complete injection of the positive perturbation signal and the negative perturbation signal. That is, the injection of the positive disturbance signal and the injection of the negative disturbance signal adopt the same sampling signal, so as to improve the precision of the successive approximation type analog-digital converter.
Fig. 2 schematically illustrates a block diagram of a digital calibration module provided in accordance with an embodiment of the present disclosure.
As shown in fig. 2, the digital calibration module includes an error calculation unit, a weight iteration unit, and a disturbance iteration unit. The error calculation unit is used for calculating errors among quantized values corresponding to the first digital code, the second digital code and the disturbance signal. The weight iteration unit is used for calculating updated capacitance weights according to errors among quantized values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the updated capacitance weights to the error calculation unit for iterative calculation. The disturbance iteration unit is used for calculating the quantization value corresponding to the updated disturbance signal according to the error among the quantization values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the quantization value corresponding to the updated disturbance signal into the error calculation unit for iterative calculation.
The error calculation and the weight iterative calculation both need an initial value of weight, and when calibration is realized by the Verilog language, the bit width of the initial weight needs to be determined. If the bit width of the weight is such that floating point operations are used, the circuit is extremely complex and also does not facilitate high speed operations, so fixed point operations can be used to implement the correction algorithm. The fixed point operation is adopted, and the amplification coefficient of each capacitance weight value needs to be considered. Simulating different weight bit widths in MATLAB, executing the whole calibration procedure to obtain FFT results, drawing a change trend graph of a plurality of groups of effective digits along with the increase of iteration times, and selecting the value of the capacitance weight value amplification coefficient corresponding to the group with the largest value as the final weight bit width when the effective digits (enob) finally tend to be stable.
The specific calculation process can be as follows: the calculating of the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises the following steps: according to
E error ＝D + -D - -2Δd
Calculation error E error ，D + D for injecting quantized values corresponding to the sampled signal of the positive disturbance signal - For the quantized value corresponding to the sampled signal of the injected negative perturbation signal, Δd is the quantized value corresponding to the perturbation signal, where:
wherein n is the total number of quantization times, i is the number of word quantization times, k is the number of weight capacitor, ω k An initial weight of the kth weight capacitance, b i+ Quantized binary coding of sampled signals injected for positive perturbation signals，b i- A binary code quantized by the sampling signal injected for the negative disturbance signal;
calculating updated capacitance weights according to errors among quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises:
according to
ω′ k ＝ω k ×u ω ×E error ×(b i+ -b i- )
Calculating updated capacitance weight omega k ，u ω The iteration step length of the capacitor weight is set;
calculating the updated quantized value corresponding to the disturbance signal according to the error among the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises:
according to
Δd′＝Δd×u d ×E error
Calculating updated capacitance weights Δd', u d The iteration step length of the quantized value corresponding to the disturbance signal.
According to embodiments of the present disclosure, the operation modes of the successive approximation analog-to-digital converter include a calibration mode and a normal operation mode.
The normal working mode comprises a sampling stage, a holding stage and a quantization stage. In the sampling stage, the upper plate of the high Duan Dianrong array and the lower plate of the low-stage capacitor array are connected with a common-mode voltage, and the lower plate of the high Duan Dianrong array is connected with a sampling signal. In the holding stage, the upper plates of the high Duan Dianrong array are disconnected from the common mode voltage, and the lower plates of all the weight capacitors are connected to the common mode voltage. In the quantization stage, the lower polar plates of all the weight capacitors are connected to reference voltage or ground.
The calibration mode comprises a sampling phase, a positive disturbance signal injection phase, a sampling signal quantization phase with positive injection, a disturbance signal reset phase, a negative disturbance signal injection phase and a sampling signal quantization phase with negative injection. In the sampling stage, the upper plate of the high Duan Dianrong array and the lower plate of the low-stage capacitor array are connected with a common-mode voltage, and the lower plate of the high Duan Dianrong array is connected with a sampling signal. In the injection stage of the positive disturbance signals, the upper plate of the high Duan Dianrong array is disconnected from the common mode voltage, the lower plate of the disturbance signal injection capacitor at the p side of the differential capacitor array is connected with the reference voltage, the lower plate of the disturbance signal injection capacitor at the n side is grounded, and the lower plates of all the other capacitors are connected with the common mode voltage. In the quantization stage with the sampling signal being injected, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor on the p side of the differential capacitor array is connected with the reference voltage by the common mode voltage, and the lower electrode plate of the capacitor on the n side is grounded by the common mode voltage. And in the reset stage of the disturbance signals, the disturbance signals on the p side and the n side of the differential capacitor array are injected into the lower polar plate of the capacitor to be grounded. In the injection stage of the negative disturbance signals, the disturbance signals at the p side of the differential capacitor array are injected into the lower electrode plate of the capacitor to be grounded, the lower electrode plate of the disturbance signals at the n side of the differential capacitor array is connected with a reference voltage, and the lower electrode plates of all the other capacitors are connected with a common mode voltage. In the quantization stage of the sampling signal with negative injection, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor on the p side of the differential capacitor array is connected with the reference voltage by the common mode voltage, and the lower electrode plate of the capacitor on the n side is grounded by the common mode voltage.
To more clearly aid in understanding the technical content of the present disclosure, the following describes the operation of the successive approximation type analog-to-digital converter provided in the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 3 schematically illustrates a timing diagram for disturbance-based digital calibration provided in accordance with an embodiment of the present disclosure.
As shown in fig. 3, in the calibration mode, the analog signal is sampled during the sampling phase, i.e., t 1 -t 2 In the time period, the sampling value is recorded as V 1 Assume that the analog voltage values for positive and negative injections are + -Deltaa. Next, during the injection phase of the positive disturbance signal, i.e., t 2 -t 3 During the time period, the upper electrode plate of the capacitor array is connected with V cm Breaking, disturbance injection capacitor C in P-side capacitor array tp Lower poleBoard connected reference voltage V ref Disturbance injection capacitor C in N-side capacitor array tn Lower polar plate GND, all other lower polar plates of capacitor are connected with V cm . Next, in the quantization phase with the sample signal being injected, i.e. t 3 4 4 In the time period, the first comparison is directly carried out without switching the capacitor array during the first comparison, and the connection method of the lower electrode plates of the capacitors on the P side and the N side is determined according to the comparison result. If the comparator P side outputs the result V outp =1, the P-side capacitance is defined by V cm GND, N side capacitance is formed by V cm Connect V ref The method comprises the steps of carrying out a first treatment on the surface of the If V outp =0, the P-side capacitance is defined by V cm Connect V ref The N side capacitance is formed by V cm And (5) connecting GND. This is repeated until all bit quantization ends. Next, in the reset phase of the disturbance signal, i.e. t 4 -t 5 During the period of time, C tp And C tn Lower polar plate is connected with V cm Restoring the value of the sampled signal to V, which is the value before the injection of the positive disturbance signal i . Next, during the injection phase of the negative perturbation signal, i.e. t 5 4 6 During the period of time, C tp The lower polar plate is connected with GND, C tn Lower polar plate V ref All other lower electrode plates of the capacitor are connected with V cm . Next, in the quantization phase with negative injection of the sampled signal, i.e. t 6 -t 7 And in the time period, the switching mode of the lower polar plate of the capacitor is the same as the switching mode of the quantization stage when the positive disturbance signal is injected.
The result after positive and negative injection quantization is input to an error calculation unit shown in fig. 2. The error calculation unit will perform the following calculations:
E error ＝D + -D - -2Δd
if ADC is ideal, D + And D - The difference in the digital threshold should be only 2Δd, but D is due to non-ideal factors such as capacitance mismatch and parasitics + And D - With deviations, the digital calibration module will execute repeatedly until E error Approaching 0.
Specifically, the weight of each bit is continuously optimized by adopting an LMS-based iterative algorithm. And transmitting the result of the error calculation unit to the weight iteration calculation unit and the disturbance iteration unit. The weight iteration calculation unit and the disturbance iteration unit will perform the following calculations, respectively:
ω′ k ＝ω k ×u ω ×E error ×(b i+ -b i- )
Δd′＝Δd×u d ×E error
the updated weight w i And Deltad' is input into an error calculation module to obtain updated E error Value, iterate so far error Approaching 0, the optimum value of the weight is obtained, and the calibration ends.
Fig. 4 schematically illustrates a graph of the number of significant bits versus the number of corrections provided by an embodiment of the present disclosure.
As shown in fig. 4, when the number of iterations reaches 50000, the ADC's effectiveness will stabilize and fluctuate between 13.3 to 13.4, at which point calibration can be ended.
After calibration is finished, the ADC enters a normal working mode, and the optimal weight obtained in the calibration stage is used in the normal working mode.
In the sampling phase, i.e. t 8 -t 9 In the time period, the upper-level plate of the capacitor is connected with V cm Low-stage capacitor array (C) 0 -C 4 ) Lower polar plate is connected with V cm V is connected with the lower polar plate of the high-stage array capacitor i The method comprises the steps of carrying out a first treatment on the surface of the The charge stored by the entire capacitive array can be expressed as:
Q 1 ＝(V cm -V i )·C msb
wherein C is msb Is the sum of the high-section capacitances. In the holding stage, the upper polar plate is connected with V cm Disconnecting all the lower polar plates of the capacitor are connected with V cm 。
In the hold phase, i.e. t 9 -t 10 The charge stored throughout the capacitive array over a period of time can be expressed as:
Q 2 ＝(V x -V cm )(C msb +C lsb //C b )
wherein C is lsb Is the sum of low-stage capacitance, C b Is a bridgeCapacitance of V x Is the upper plate voltage of the capacitor. According to the conservation of charge, the plate voltage V on the hold-order capacitor can be obtained by the two corresponding formulas of the sampling stage and the hold stage x ：
In the quantization phase, i.e. t 10 -t 11 And in the time period, the switching mode of the polar plate under the capacitor is the same as the switching mode of the quantization stage under the calibration mode. In combination with the switching mode of the quantization stage, the comparator outputs the result D i (i=16, 15,.,. 1), V can be obtained x The general expression throughout the conversion process is:
and (3) using the optimal weight obtained in the calibration stage for digital output obtained by quantization in a normal working mode, and carrying out weighted summation. And intercepting the first 14 bits as the final output of the 14-bit ADC to obtain the output result of the ADC.
Fig. 5 schematically illustrates a diagram of FFT simulation results before and after calibration provided by an embodiment of the present disclosure.
As shown in fig. 5, the correction method improves the Spurious Free Dynamic Range (SFDR) from 67.2dB to 96.0dB and the effective number of bits (enob) from 9.83bit to 13.36bit, for comparison of the ADC dynamic performance before and after calibration. The effectiveness of the calibration algorithm was demonstrated.
Based on the same inventive concept, the embodiment of the present disclosure also provides a calibration method.
The calibration method comprises the steps of sampling by using a signal sampling module to obtain a sampling signal. And injecting positive disturbance signals and negative disturbance signals into the sampling signals by using a differential capacitor array and a disturbance signal injection module. And quantizing the sampling signals injected with the positive disturbance signals and the negative disturbance signals by using a digital calibration module to obtain two different digital codes and quantized values corresponding to the disturbance signals, and calculating the initial value of the capacitance weight error of the differential capacitance array by using the two different digital codes and the quantized values corresponding to the disturbance signals. Calculating updated capacitance weight and quantized values corresponding to the updated disturbance signals according to initial values of the capacitance weight errors, and calculating capacitance weight errors according to the updated capacitance weight and the quantized values corresponding to the updated disturbance signals, wherein the steps are performed in a circulating mode until the capacitance weight errors tend to zero.
It should be noted that the embodiment part of the calibration method corresponds to the embodiment part of the successive approximation type analog-to-digital converter, and please refer to the above embodiment for details.
In summary, the successive approximation type analog-to-digital converter provided by the embodiment of the disclosure adopts the segmented capacitor array with the non-binary structure of the integer weight, and the structure is internally provided with the redundancy function, so that compared with the traditional redundancy technology, the error tolerance function is realized without adding additional redundancy capacitors, the swing amplitude of an input signal is ensured, and meanwhile, the area of the capacitor array is reduced. The disturbance injection can be realized only through two injection capacitors and some simple digital logic, so that the complexity is obviously lower than that of a calibration mode based on a reference ADC. It is also much simpler than the split analog to digital converter calibration. And the digital weight of the weight capacitor is corrected to reduce the capacitor mismatch caused by parasitic capacitance and process manufacturing errors, so that the effective bit number of the ADC is improved. In the aspect of algorithm realization, the LMS algorithm has low calculation complexity, low hardware cost and easy realization.
While the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be understood that the foregoing embodiments are merely illustrative of the invention and are not intended to limit the invention, and that any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (8)
1. A successive approximation analog-to-digital converter comprising:
the signal sampling module is used for sampling the analog signals to obtain sampled signals;
the differential capacitor array comprises a low-stage capacitor array, a high Duan Dianrong array and a disturbance signal injection capacitor, wherein the low-stage capacitor array is formed by a binary coded capacitor array, and the high Duan Dianrong array is formed by a non-binary coded capacitor array with integer weight; the signal sampling module realizes sampling through a lower polar plate of the high-stage capacitor;
the disturbance signal injection module is used for injecting positive disturbance signals and negative disturbance signals into the sampling signals;
the digital calibration module is used for quantizing the sampled signals injected with the positive disturbance signals and the negative disturbance signals to obtain a first digital code corresponding to the sampled signals injected with the positive disturbance signals, a second digital code corresponding to the sampled signals injected with the negative disturbance signals and quantized values corresponding to the disturbance signals, and carrying out iterative computation according to the quantized values corresponding to the first digital code, the second digital code and the disturbance signals based on an LMS iterative algorithm until errors among the quantized values corresponding to the first digital code, the second digital code and the disturbance signals tend to zero; the error among the quantized values corresponding to the first digital code, the second digital code and the disturbance signal is a capacitance weight error of the differential capacitance array;
the comparator module is used for comparing signals input by the differential capacitor array and outputting a comparison result;
the logic control module is used for switching the signal access mode of the differential capacitor array according to the comparison result; wherein the digital calibration module comprises: the error calculation unit is used for calculating errors among quantization values corresponding to the first digital code, the second digital code and the disturbance signal; the weight iteration unit is used for calculating updated capacitance weights according to errors among quantization values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the updated capacitance weights into the error calculation unit for iterative calculation; the disturbance iteration unit is used for calculating the quantization value corresponding to the updated disturbance signal according to the error among the quantization values corresponding to the first digital code, the second digital code and the disturbance signal, and inputting the quantization value corresponding to the updated disturbance signal into the error calculation unit for iterative calculation;
the calculating the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises:
according to the following:
E error ＝D + -D - -2Δd
calculating the error E error ，D + D for injecting quantized values corresponding to the sampled signal of the positive disturbance signal - For the quantized value corresponding to the sampled signal of the injected negative perturbation signal, Δd is the quantized value corresponding to the perturbation signal, where:
wherein n is the total number of quantization times, i is the number of single quantization times, k is the number of weight capacitor, ω k An initial weight of the kth weight capacitance, b i+ B) binary coding quantized for a sample signal injected for a positive perturbation signal i- A binary code quantized by the sampling signal injected for the negative disturbance signal;
the calculating the updated capacitance weight according to the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises:
according to
ω′ k ＝ω k ×u ω ×E error ×(b i+ -b i- )
Calculate updated capacitance weight ω' k ，u ω The iteration step length of the capacitor weight is set;
the calculating the updated quantized value corresponding to the disturbance signal according to the error between the quantized values corresponding to the first digital code, the second digital code and the disturbance signal comprises:
according to
Δd′＝Δd×u d ×E error
Calculating updated capacitance weights Δd', u d The iteration step length of the quantized value corresponding to the disturbance signal.
2. The successive approximation analog-to-digital converter of claim 1, wherein the perturbation signal injection module effects switching between positive perturbation signal injection and negative perturbation signal injection by changing a bottom plate junction of the perturbation signal injection capacitance.
3. The successive approximation type analog-to-digital converter according to claim 2, wherein the lower electrode plate of the disturbance signal injection capacitor on the p side of the differential capacitor array is connected with a reference voltage, and the lower electrode plate of the disturbance signal injection capacitor on the n side is grounded, so that the injection of the positive disturbance signal is realized;
and grounding the lower polar plate of the disturbance signal injection capacitor at the p side of the differential capacitor array, and connecting the lower polar plate of the disturbance signal injection capacitor at the n side with a reference voltage to realize the injection of the negative disturbance signal.
4. The successive approximation analog-to-digital converter of claim 1, wherein the operational modes of the successive approximation analog-to-digital converter include a calibration mode and a normal operation mode, the normal operation mode including a sampling phase, a holding phase, and a quantization phase;
in the sampling stage, an upper plate of the high Duan Dianrong array and a lower plate of the low-stage capacitor array are connected with a common-mode voltage, and a lower plate of the high Duan Dianrong array is connected with a sampling signal;
in the holding stage, the upper plates of the high Duan Dianrong array are disconnected from the common mode voltage, and the lower plates of all the weight capacitors are connected to the common mode voltage;
in the quantization stage, the lower polar plates of all the weight capacitors are connected to reference voltage or ground;
the calibration mode comprises a sampling phase, a positive disturbance signal injection phase, a sampling signal quantization phase with positive injection, a disturbance signal resetting phase, a negative disturbance signal injection phase and a sampling signal quantization phase with negative injection;
in the sampling stage, an upper plate of the high Duan Dianrong array and a lower plate of the low-stage capacitor array are connected with a common-mode voltage, and a lower plate of the high Duan Dianrong array is connected with a sampling signal;
in the injection stage of the positive disturbance signals, the upper plate of the high Duan Dianrong array is disconnected from the common mode voltage, the lower plate of the disturbance signal injection capacitor at the p side of the differential capacitor array is connected with the reference voltage, the lower plate of the disturbance signal injection capacitor at the n side is grounded, and the lower plates of all the other capacitors are connected with the common mode voltage;
in the quantization stage with the sampling signal being injected, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor at the p side of the differential capacitor array is connected with the reference voltage by the common-mode voltage, and the lower electrode plate of the capacitor at the n side is grounded by the common-mode voltage;
in the reset stage of the disturbance signals, the disturbance signals on the p side and the n side of the differential capacitor array are injected into the lower polar plate of the capacitor to be grounded;
in the injection stage of the negative disturbance signals, the disturbance signals at the p side of the differential capacitor array are injected into the lower electrode plate of the capacitor to be grounded, the lower electrode plate of the disturbance signal injection capacitor at the n side is connected with a reference voltage, and the lower electrode plates of all the other capacitors are connected with a common mode voltage;
in the quantization stage of the sampling signal with negative injection, if the comparison result is 1, the lower electrode plate of the capacitor at the p side of the differential capacitor array is grounded by a common mode voltage, and the lower electrode plate of the capacitor at the n side is connected with a reference voltage by the common mode voltage; if the comparison result is 0, the lower electrode plate of the capacitor on the p side of the differential capacitor array is connected with the reference voltage by the common mode voltage, and the lower electrode plate of the capacitor on the n side is grounded by the common mode voltage.
5. The successive approximation analog-to-digital converter of claim 1, wherein the signal sampling module value performs one signal sample during one complete injection of the positive and negative perturbation signals.
6. The successive approximation type analog-to-digital converter according to claim 4, wherein after the sample signal to which the positive disturbance signal is injected is quantized, the sample signal is reset and the injection of the negative disturbance signal is performed.
7. The successive approximation analog-to-digital converter of claim 1, wherein any one of the next-to-highest weighted capacitors in the array of high Duan Dianrong has a weight less than the sum of the weights of all weighted capacitors lower than that capacitor.
8. A method of calibrating a successive approximation analog-to-digital converter according to any of claims 1-7, comprising:
sampling by using a signal sampling module to obtain a sampling signal;
injecting positive disturbance signals and negative disturbance signals to the sampling signals by using a differential capacitor array and a disturbance signal injection module
Quantizing the sampling signals injected with the positive disturbance signals and the negative disturbance signals by using a digital calibration module to obtain two different digital codes and quantized values corresponding to the disturbance signals, and calculating the initial value of the capacitance weight error of the differential capacitance array by using the quantized values corresponding to the two different digital codes and the disturbance signals; calculating updated capacitance weight and quantized values corresponding to the updated disturbance signals according to initial values of the capacitance weight errors, and calculating capacitance weight errors according to the updated capacitance weight and the quantized values corresponding to the updated disturbance signals, wherein the steps are performed in a circulating mode until the capacitance weight errors tend to zero.
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